About the Execution of LoLA for Diffusion2D-PT-D50N010
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16198.327 | 913589.00 | 1618137.00 | 2731.50 | ??TT??F??TT???F? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r137-tall-171631134000330.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is Diffusion2D-PT-D50N010, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r137-tall-171631134000330
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 7.8M
-rw-r--r-- 1 mcc users 9.6K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 97K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.6K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 51K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.5K Apr 22 14:40 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Apr 22 14:40 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.9K Apr 22 14:40 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Apr 22 14:40 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Apr 11 14:22 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 118K Apr 11 14:22 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.0K Apr 11 14:22 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 52K Apr 11 14:22 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Apr 22 14:40 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Apr 22 14:40 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 8 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 7.3M May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME Diffusion2D-PT-D50N010-CTLFireability-2024-00
FORMULA_NAME Diffusion2D-PT-D50N010-CTLFireability-2024-01
FORMULA_NAME Diffusion2D-PT-D50N010-CTLFireability-2024-02
FORMULA_NAME Diffusion2D-PT-D50N010-CTLFireability-2024-03
FORMULA_NAME Diffusion2D-PT-D50N010-CTLFireability-2024-04
FORMULA_NAME Diffusion2D-PT-D50N010-CTLFireability-2024-05
FORMULA_NAME Diffusion2D-PT-D50N010-CTLFireability-2024-06
FORMULA_NAME Diffusion2D-PT-D50N010-CTLFireability-2024-07
FORMULA_NAME Diffusion2D-PT-D50N010-CTLFireability-2024-08
FORMULA_NAME Diffusion2D-PT-D50N010-CTLFireability-2024-09
FORMULA_NAME Diffusion2D-PT-D50N010-CTLFireability-2024-10
FORMULA_NAME Diffusion2D-PT-D50N010-CTLFireability-2024-11
FORMULA_NAME Diffusion2D-PT-D50N010-CTLFireability-2023-12
FORMULA_NAME Diffusion2D-PT-D50N010-CTLFireability-2023-13
FORMULA_NAME Diffusion2D-PT-D50N010-CTLFireability-2023-14
FORMULA_NAME Diffusion2D-PT-D50N010-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717024088210
FORMULA Diffusion2D-PT-D50N010-CTLFireability-2024-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Diffusion2D-PT-D50N010-CTLFireability-2024-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Diffusion2D-PT-D50N010-CTLFireability-2024-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Diffusion2D-PT-D50N010-CTLFireability-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Diffusion2D-PT-D50N010-CTLFireability-2024-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Diffusion2D-PT-D50N010-CTLFireability-2023-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717025001799
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-00: DISJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-03: DISJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-06: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-07: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-09: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-10: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2023-12: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.]
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[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
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[[35mlola[0m][.]
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[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-00: DISJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-01: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-03: DISJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-07: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-09: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-10: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2023-12: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 13 secs. Pages in use: 0
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[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-00: DISJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-01: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-03: DISJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-07: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-09: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-10: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2023-12: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
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[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-00: DISJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-01: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-03: DISJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-07: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-09: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-10: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2023-12: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
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[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-00: DISJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-01: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-03: DISJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-07: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-09: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-10: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2023-12: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] Time elapsed: 28 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 76 (type EXCL) for 41 Diffusion2D-PT-D50N010-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 123 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 79 (type EQUN) for 41 Diffusion2D-PT-D50N010-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 79 (type EQUN) for Diffusion2D-PT-D50N010-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
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[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-00: DISJ 0 0 0 0 2 0 0 0
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[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 76 EG EXCL 0/123 1/2000 Diffusion2D-PT-D50N010-CTLFireability-2024-07 --
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[[35mlola[0m][I] FINISHED task # 76 (type EXCL) for Diffusion2D-PT-D50N010-CTLFireability-2024-07
[[35mlola[0m][I] result : true
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[[35mlola[0m][I] LAUNCH task # 65 (type EXCL) for 60 Diffusion2D-PT-D50N010-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 132 sec
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[[35mlola[0m][I] FINISHED task # 65 (type EXCL) for Diffusion2D-PT-D50N010-CTLFireability-2023-12
[[35mlola[0m][I] result : true
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[[35mlola[0m][I] LAUNCH task # 82 (type EXCL) for 51 Diffusion2D-PT-D50N010-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 161 sec
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[[35mlola[0m][I] LAUNCH task # 80 (type FNDP) for 51 Diffusion2D-PT-D50N010-CTLFireability-2024-09
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[[35mlola[0m][I] LAUNCH task # 81 (type EQUN) for 51 Diffusion2D-PT-D50N010-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 32000000 sec
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[[35mlola[0m][I] FINISHED task # 82 (type EXCL) for Diffusion2D-PT-D50N010-CTLFireability-2024-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 1
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[[35mlola[0m][W] CANCELED task # 80 (type FNDP) for Diffusion2D-PT-D50N010-CTLFireability-2024-09 (obsolete)
[[35mlola[0m][W] CANCELED task # 81 (type EQUN) for Diffusion2D-PT-D50N010-CTLFireability-2024-09 (obsolete)
[[35mlola[0m][I] LAUNCH task # 16 (type EXCL) for 7 Diffusion2D-PT-D50N010-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 169 sec
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[[35mlola[0m][I] FINISHED task # 80 (type FNDP) for Diffusion2D-PT-D50N010-CTLFireability-2024-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
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[[35mlola[0m][I] FINISHED task # 16 (type EXCL) for Diffusion2D-PT-D50N010-CTLFireability-2024-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] fired transitions : 2
[[35mlola[0m][I] time used : 0
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[[35mlola[0m][I] LAUNCH task # 39 (type EXCL) for 38 Diffusion2D-PT-D50N010-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 178 sec
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[[35mlola[0m][I] FINISHED task # 81 (type EQUN) for Diffusion2D-PT-D50N010-CTLFireability-2024-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 39 (type EXCL) for Diffusion2D-PT-D50N010-CTLFireability-2024-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 268
[[35mlola[0m][I] fired transitions : 1046
[[35mlola[0m][I] time used : 0
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[[35mlola[0m][I] LAUNCH task # 24 (type EXCL) for 21 Diffusion2D-PT-D50N010-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 197 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 83 (type FNDP) for 54 Diffusion2D-PT-D50N010-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
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[[35mlola[0m][I] LAUNCH task # 84 (type EQUN) for 54 Diffusion2D-PT-D50N010-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 24 (type EXCL) for Diffusion2D-PT-D50N010-CTLFireability-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 66
[[35mlola[0m][I] fired transitions : 551
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 85 (type EXCL) for 54 Diffusion2D-PT-D50N010-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 222 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 84 (type EQUN) for Diffusion2D-PT-D50N010-CTLFireability-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][W] CANCELED task # 83 (type FNDP) for Diffusion2D-PT-D50N010-CTLFireability-2024-10 (obsolete)
[[35mlola[0m][W] CANCELED task # 85 (type EXCL) for Diffusion2D-PT-D50N010-CTLFireability-2024-10 (obsolete)
[[35mlola[0m][I] FINISHED task # 83 (type FNDP) for Diffusion2D-PT-D50N010-CTLFireability-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
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[[35mlola[0m][I] LAUNCH task # 88 (type EXCL) for 18 Diffusion2D-PT-D50N010-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 254 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 86 (type FNDP) for 18 Diffusion2D-PT-D50N010-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 87 (type EQUN) for 18 Diffusion2D-PT-D50N010-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 88 (type EXCL) for Diffusion2D-PT-D50N010-CTLFireability-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 1
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[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 86 (type FNDP) for Diffusion2D-PT-D50N010-CTLFireability-2024-02 (obsolete)
[[35mlola[0m][W] CANCELED task # 87 (type EQUN) for Diffusion2D-PT-D50N010-CTLFireability-2024-02 (obsolete)
[[35mlola[0m][I] LAUNCH task # 71 (type EXCL) for 70 Diffusion2D-PT-D50N010-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 273 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 86 (type FNDP) for Diffusion2D-PT-D50N010-CTLFireability-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] FINISHED task # 71 (type EXCL) for Diffusion2D-PT-D50N010-CTLFireability-2023-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 968
[[35mlola[0m][I] fired transitions : 4805
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] FINISHED task # 87 (type EQUN) for Diffusion2D-PT-D50N010-CTLFireability-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 33 (type EXCL) for 32 Diffusion2D-PT-D50N010-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 296 sec
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[[35mlola[0m][I] LAUNCH task # 92 (type EQUN) for 41 Diffusion2D-PT-D50N010-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
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[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D50N010-CTLFireability-2024-02: EF true state space[0m
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[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-07: CONJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2023-12: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2023-15: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 3/296 1/2000 Diffusion2D-PT-D50N010-CTLFireability-2024-04 6381 m, 1276 m/sec, 20366 t fired, .
[[35mlola[0m][.] 92 EF STEQ 0/3555 0/5 Diffusion2D-PT-D50N010-CTLFireability-2024-07 sara not yet started (preprocessing).
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[[35mlola[0m][I] FINISHED task # 92 (type EQUN) for Diffusion2D-PT-D50N010-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D50N010-CTLFireability-2024-02: EF true state space[0m
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[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D50N010-CTLFireability-2023-14: CTL false CTL model checker[0m
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[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-00: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-01: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-07: CONJ 0 1 0 0 5 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2023-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 8/296 1/2000 Diffusion2D-PT-D50N010-CTLFireability-2024-04 16997 m, 2123 m/sec, 57333 t fired, .
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[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-01: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-07: CONJ 0 1 0 0 5 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2023-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D50N010-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 13/296 1/2000 Diffusion2D-PT-D50N010-CTLFireability-2024-04 26548 m, 1910 m/sec, 91027 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 28/296 1/2000 Diffusion2D-PT-D50N010-CTLFireability-2024-04 54461 m, 1866 m/sec, 189058 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 33/296 1/2000 Diffusion2D-PT-D50N010-CTLFireability-2024-04 63951 m, 1898 m/sec, 222269 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 38/296 1/2000 Diffusion2D-PT-D50N010-CTLFireability-2024-04 73454 m, 1900 m/sec, 255650 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 58/296 2/2000 Diffusion2D-PT-D50N010-CTLFireability-2024-04 110888 m, 1592 m/sec, 386936 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 63/296 2/2000 Diffusion2D-PT-D50N010-CTLFireability-2024-04 118955 m, 1613 m/sec, 415186 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 68/296 2/2000 Diffusion2D-PT-D50N010-CTLFireability-2024-04 127294 m, 1667 m/sec, 444134 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 73/296 2/2000 Diffusion2D-PT-D50N010-CTLFireability-2024-04 135201 m, 1581 m/sec, 471835 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 78/296 2/2000 Diffusion2D-PT-D50N010-CTLFireability-2024-04 143228 m, 1605 m/sec, 499552 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 83/296 2/2000 Diffusion2D-PT-D50N010-CTLFireability-2024-04 151707 m, 1695 m/sec, 529264 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 88/296 2/2000 Diffusion2D-PT-D50N010-CTLFireability-2024-04 160376 m, 1733 m/sec, 560017 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 93/296 2/2000 Diffusion2D-PT-D50N010-CTLFireability-2024-04 170214 m, 1967 m/sec, 594569 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 98/296 3/2000 Diffusion2D-PT-D50N010-CTLFireability-2024-04 179808 m, 1918 m/sec, 629168 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 158/296 4/2000 Diffusion2D-PT-D50N010-CTLFireability-2024-04 289651 m, 1624 m/sec, 1030714 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 163/296 4/2000 Diffusion2D-PT-D50N010-CTLFireability-2024-04 298949 m, 1859 m/sec, 1066005 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 168/296 4/2000 Diffusion2D-PT-D50N010-CTLFireability-2024-04 308996 m, 2009 m/sec, 1103582 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 193/296 5/2000 Diffusion2D-PT-D50N010-CTLFireability-2024-04 350876 m, 1687 m/sec, 1257360 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 198/296 5/2000 Diffusion2D-PT-D50N010-CTLFireability-2024-04 360086 m, 1842 m/sec, 1292505 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 203/296 5/2000 Diffusion2D-PT-D50N010-CTLFireability-2024-04 369067 m, 1796 m/sec, 1325841 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 208/296 5/2000 Diffusion2D-PT-D50N010-CTLFireability-2024-04 378181 m, 1822 m/sec, 1360583 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 278/296 7/2000 Diffusion2D-PT-D50N010-CTLFireability-2024-04 495492 m, 1607 m/sec, 1800240 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 15/296 1/5 Diffusion2D-PT-D50N010-CTLFireability-2024-04 29796 m, 1865 m/sec, 102125 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 20/296 1/5 Diffusion2D-PT-D50N010-CTLFireability-2024-04 38966 m, 1834 m/sec, 134294 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 25/296 1/5 Diffusion2D-PT-D50N010-CTLFireability-2024-04 48148 m, 1836 m/sec, 166594 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 30/296 1/5 Diffusion2D-PT-D50N010-CTLFireability-2024-04 57321 m, 1834 m/sec, 199013 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 35/296 1/5 Diffusion2D-PT-D50N010-CTLFireability-2024-04 66530 m, 1841 m/sec, 231598 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 40/296 1/5 Diffusion2D-PT-D50N010-CTLFireability-2024-04 75613 m, 1816 m/sec, 263517 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 45/296 2/5 Diffusion2D-PT-D50N010-CTLFireability-2024-04 86258 m, 2129 m/sec, 300945 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 50/296 2/5 Diffusion2D-PT-D50N010-CTLFireability-2024-04 95743 m, 1897 m/sec, 334528 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 55/296 2/5 Diffusion2D-PT-D50N010-CTLFireability-2024-04 104658 m, 1783 m/sec, 365343 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 60/296 2/5 Diffusion2D-PT-D50N010-CTLFireability-2024-04 112374 m, 1543 m/sec, 392299 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 65/296 2/5 Diffusion2D-PT-D50N010-CTLFireability-2024-04 120417 m, 1608 m/sec, 420171 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 70/296 2/5 Diffusion2D-PT-D50N010-CTLFireability-2024-04 128733 m, 1663 m/sec, 449301 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 75/296 2/5 Diffusion2D-PT-D50N010-CTLFireability-2024-04 136497 m, 1552 m/sec, 476622 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 80/296 2/5 Diffusion2D-PT-D50N010-CTLFireability-2024-04 144387 m, 1578 m/sec, 503570 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 85/296 2/5 Diffusion2D-PT-D50N010-CTLFireability-2024-04 152698 m, 1662 m/sec, 532640 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 90/296 2/5 Diffusion2D-PT-D50N010-CTLFireability-2024-04 161545 m, 1769 m/sec, 564080 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 95/296 2/5 Diffusion2D-PT-D50N010-CTLFireability-2024-04 171366 m, 1964 m/sec, 598988 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 100/296 3/5 Diffusion2D-PT-D50N010-CTLFireability-2024-04 180827 m, 1892 m/sec, 632976 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 105/296 3/5 Diffusion2D-PT-D50N010-CTLFireability-2024-04 190848 m, 2004 m/sec, 670153 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 110/296 3/5 Diffusion2D-PT-D50N010-CTLFireability-2024-04 200541 m, 1938 m/sec, 705848 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 115/296 3/5 Diffusion2D-PT-D50N010-CTLFireability-2024-04 209806 m, 1853 m/sec, 739074 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 135/296 3/5 Diffusion2D-PT-D50N010-CTLFireability-2024-04 245692 m, 2005 m/sec, 869880 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 140/296 4/5 Diffusion2D-PT-D50N010-CTLFireability-2024-04 253818 m, 1625 m/sec, 898925 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 145/296 4/5 Diffusion2D-PT-D50N010-CTLFireability-2024-04 262118 m, 1660 m/sec, 928366 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 150/296 4/5 Diffusion2D-PT-D50N010-CTLFireability-2024-04 270809 m, 1738 m/sec, 961276 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 155/296 4/5 Diffusion2D-PT-D50N010-CTLFireability-2024-04 279634 m, 1765 m/sec, 994053 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 160/296 4/5 Diffusion2D-PT-D50N010-CTLFireability-2024-04 287484 m, 1570 m/sec, 1022680 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 170/296 4/5 Diffusion2D-PT-D50N010-CTLFireability-2024-04 305776 m, 1930 m/sec, 1091467 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 175/296 4/5 Diffusion2D-PT-D50N010-CTLFireability-2024-04 314529 m, 1750 m/sec, 1123994 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 180/296 4/5 Diffusion2D-PT-D50N010-CTLFireability-2024-04 322471 m, 1588 m/sec, 1152140 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 185/296 5/5 Diffusion2D-PT-D50N010-CTLFireability-2024-04 330299 m, 1565 m/sec, 1181562 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 190/296 5/5 Diffusion2D-PT-D50N010-CTLFireability-2024-04 338496 m, 1639 m/sec, 1211834 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 195/296 5/5 Diffusion2D-PT-D50N010-CTLFireability-2024-04 346522 m, 1605 m/sec, 1241373 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 200/296 5/5 Diffusion2D-PT-D50N010-CTLFireability-2024-04 355060 m, 1707 m/sec, 1273520 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 205/296 5/5 Diffusion2D-PT-D50N010-CTLFireability-2024-04 363917 m, 1771 m/sec, 1306535 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 210/296 5/5 Diffusion2D-PT-D50N010-CTLFireability-2024-04 373029 m, 1822 m/sec, 1341431 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 215/296 5/5 Diffusion2D-PT-D50N010-CTLFireability-2024-04 381148 m, 1623 m/sec, 1372204 t fired, .
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/home/mcc/BenchKit/BenchKit_head.sh: line 23: 408 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Diffusion2D-PT-D50N010"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is Diffusion2D-PT-D50N010, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r137-tall-171631134000330"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/Diffusion2D-PT-D50N010.tgz
mv Diffusion2D-PT-D50N010 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;