About the Execution of LoLA for Diffusion2D-PT-D05N150
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
16202.796 | 546220.00 | 738925.00 | 2123.30 | T????????????T?? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r137-tall-171631133600154.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is Diffusion2D-PT-D05N150, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r137-tall-171631133600154
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 536K
-rw-r--r-- 1 mcc users 8.0K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 74K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.2K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 63K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.2K Apr 22 14:40 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Apr 22 14:40 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.7K Apr 22 14:40 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Apr 22 14:40 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Apr 11 14:18 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 115K Apr 11 14:18 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Apr 11 14:18 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 84K Apr 11 14:18 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Apr 22 14:40 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Apr 22 14:40 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 8 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 55K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME Diffusion2D-PT-D05N150-CTLFireability-2024-00
FORMULA_NAME Diffusion2D-PT-D05N150-CTLFireability-2024-01
FORMULA_NAME Diffusion2D-PT-D05N150-CTLFireability-2024-02
FORMULA_NAME Diffusion2D-PT-D05N150-CTLFireability-2024-03
FORMULA_NAME Diffusion2D-PT-D05N150-CTLFireability-2024-04
FORMULA_NAME Diffusion2D-PT-D05N150-CTLFireability-2024-05
FORMULA_NAME Diffusion2D-PT-D05N150-CTLFireability-2024-06
FORMULA_NAME Diffusion2D-PT-D05N150-CTLFireability-2024-07
FORMULA_NAME Diffusion2D-PT-D05N150-CTLFireability-2024-08
FORMULA_NAME Diffusion2D-PT-D05N150-CTLFireability-2024-09
FORMULA_NAME Diffusion2D-PT-D05N150-CTLFireability-2024-10
FORMULA_NAME Diffusion2D-PT-D05N150-CTLFireability-2024-11
FORMULA_NAME Diffusion2D-PT-D05N150-CTLFireability-2023-12
FORMULA_NAME Diffusion2D-PT-D05N150-CTLFireability-2023-13
FORMULA_NAME Diffusion2D-PT-D05N150-CTLFireability-2023-14
FORMULA_NAME Diffusion2D-PT-D05N150-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717014027128
FORMULA Diffusion2D-PT-D05N150-CTLFireability-2024-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Diffusion2D-PT-D05N150-CTLFireability-2023-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717014573348
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 Diffusion2D-PT-D05N150-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 97 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for Diffusion2D-PT-D05N150-CTLFireability-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 764
[[35mlola[0m][I] fired transitions : 2169
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 64 (type EXCL) for 63 Diffusion2D-PT-D05N150-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 116 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 64 (type EXCL) for Diffusion2D-PT-D05N150-CTLFireability-2023-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 302
[[35mlola[0m][I] fired transitions : 605
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 47 (type EXCL) for 46 Diffusion2D-PT-D05N150-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 133 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 75 (type EQUN) for 6 Diffusion2D-PT-D05N150-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 76 (type FNDP) for 6 Diffusion2D-PT-D05N150-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 77 (type EQUN) for 6 Diffusion2D-PT-D05N150-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 75 (type EQUN) for Diffusion2D-PT-D05N150-CTLFireability-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 76 (type FNDP) for Diffusion2D-PT-D05N150-CTLFireability-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 77 (type EQUN) for Diffusion2D-PT-D05N150-CTLFireability-2024-02 (obsolete)
[[35mlola[0m][I] FINISHED task # 77 (type EQUN) for Diffusion2D-PT-D05N150-CTLFireability-2024-02
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 5/200 7/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-10 1633299 m, 326659 m/sec, 11039956 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 10/200 13/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-10 3193738 m, 312087 m/sec, 21082213 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 15/200 19/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-10 4719974 m, 305247 m/sec, 30762742 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 19
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 20/200 25/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-10 6216565 m, 299318 m/sec, 40243908 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 25
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 25/200 31/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-10 7704130 m, 297513 m/sec, 49506945 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 31
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 30/200 37/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-10 9173519 m, 293877 m/sec, 58865608 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 37
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 35/200 43/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-10 10652309 m, 295758 m/sec, 68037571 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 43
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 40/200 49/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-10 12126736 m, 294885 m/sec, 77277427 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 49
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 45/200 55/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-10 13639190 m, 302490 m/sec, 86784851 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 55
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 50/200 61/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-10 15132276 m, 298617 m/sec, 96136275 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 61
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 55/200 67/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-10 16645747 m, 302694 m/sec, 105549137 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 67
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 60/200 73/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-10 18161039 m, 303058 m/sec, 115017742 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 73
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 65/200 80/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-10 19705535 m, 308899 m/sec, 124675167 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 80
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 70/200 86/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-10 21279319 m, 314756 m/sec, 134485987 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 86
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 75/200 91/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-10 22464977 m, 237131 m/sec, 145085683 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 80/200 91/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-10 22479815 m, 2967 m/sec, 155998667 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 85/200 91/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-10 22486644 m, 1365 m/sec, 166183449 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 90/200 91/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-10 22492292 m, 1129 m/sec, 176446840 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 95/200 91/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-10 22495441 m, 629 m/sec, 186227714 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 100/200 91/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-10 22499709 m, 853 m/sec, 196014245 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 105/200 91/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-10 22502709 m, 600 m/sec, 205581182 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 110/200 91/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-10 22506019 m, 662 m/sec, 215395491 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 115/200 91/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-10 22508700 m, 536 m/sec, 224566066 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 120/200 91/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-10 22511543 m, 568 m/sec, 234110199 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 125/200 91/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-10 22513808 m, 453 m/sec, 243386423 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 130/200 91/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-10 22516040 m, 446 m/sec, 252603546 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 135/200 91/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-10 22517959 m, 383 m/sec, 261646208 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 140/200 91/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-10 22519858 m, 379 m/sec, 271042791 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 140 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 145/200 91/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-10 22521965 m, 421 m/sec, 280592719 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 145 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 150/200 91/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-10 22523513 m, 309 m/sec, 289680122 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 155/200 91/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-10 22526581 m, 613 m/sec, 299072953 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 155 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 160/200 91/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-10 22527294 m, 142 m/sec, 308586010 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 160 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 165/200 91/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-10 22529951 m, 531 m/sec, 317869040 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 165 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 170/200 91/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-10 22531489 m, 307 m/sec, 327489884 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 170 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 175/200 91/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-10 22532682 m, 238 m/sec, 337371973 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 175 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 180/200 91/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-10 22532974 m, 58 m/sec, 347716121 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 180 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 185/200 91/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-10 22533126 m, 30 m/sec, 358619983 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 185 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 190/200 91/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-10 22533126 m, 0 m/sec, 369451666 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 190 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 195/200 91/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-10 22533126 m, 0 m/sec, 379632339 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 195 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 200/200 91/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-10 22533126 m, 0 m/sec, 389441586 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 200 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 47 (type EXCL) for Diffusion2D-PT-D05N150-CTLFireability-2024-10 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 205 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 67 (type EXCL) for 66 Diffusion2D-PT-D05N150-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 199 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 47 (type EXCL) for 46 Diffusion2D-PT-D05N150-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 3395 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 67 (type EXCL) for Diffusion2D-PT-D05N150-CTLFireability-2023-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] CANCELED task # 47 (type EXCL) for Diffusion2D-PT-D05N150-CTLFireability-2024-10 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 210 secs. Pages in use: 96
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 61 (type EXCL) for 60 Diffusion2D-PT-D05N150-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 61 (type EXCL) for Diffusion2D-PT-D05N150-CTLFireability-2023-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 58 (type EXCL) for 49 Diffusion2D-PT-D05N150-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 226 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 58 (type EXCL) for Diffusion2D-PT-D05N150-CTLFireability-2024-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 8
[[35mlola[0m][I] fired transitions : 15
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 56 (type EXCL) for 49 Diffusion2D-PT-D05N150-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 242 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 56 (type EXCL) for Diffusion2D-PT-D05N150-CTLFireability-2024-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 301
[[35mlola[0m][I] fired transitions : 904
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 44 (type EXCL) for 43 Diffusion2D-PT-D05N150-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 282 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 5/282 3/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 594246 m, 118849 m/sec, 6261211 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 215 secs. Pages in use: 96
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 10/282 6/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 1208778 m, 122906 m/sec, 11532138 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 220 secs. Pages in use: 97
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 15/282 8/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 1692052 m, 96654 m/sec, 17094603 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 225 secs. Pages in use: 99
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 20/282 10/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 2197267 m, 101043 m/sec, 22379422 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 230 secs. Pages in use: 101
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 25/282 12/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 2747706 m, 110087 m/sec, 27273009 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 235 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 30/282 14/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 3216883 m, 93835 m/sec, 32323839 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 240 secs. Pages in use: 105
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 35/282 16/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 3710289 m, 98681 m/sec, 37636134 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 245 secs. Pages in use: 107
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 40/282 18/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 4190603 m, 96062 m/sec, 42669139 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 250 secs. Pages in use: 109
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 45/282 20/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 4682820 m, 98443 m/sec, 47373117 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 255 secs. Pages in use: 111
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 50/282 22/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 5257832 m, 115002 m/sec, 51807377 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 260 secs. Pages in use: 113
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 55/282 24/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 5770863 m, 102606 m/sec, 56402149 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 265 secs. Pages in use: 115
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 60/282 26/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 6131777 m, 72182 m/sec, 61713658 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 270 secs. Pages in use: 117
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 65/282 28/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 6579813 m, 89607 m/sec, 66868165 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 275 secs. Pages in use: 119
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 70/282 30/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 7079742 m, 99985 m/sec, 71721232 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 280 secs. Pages in use: 121
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 75/282 31/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 7490260 m, 82103 m/sec, 76626143 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 285 secs. Pages in use: 122
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 80/282 34/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 8069019 m, 115751 m/sec, 81081178 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 290 secs. Pages in use: 125
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 85/282 35/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 8429197 m, 72035 m/sec, 85964863 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 295 secs. Pages in use: 126
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 90/282 37/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 8868396 m, 87839 m/sec, 90847669 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 300 secs. Pages in use: 128
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 95/282 39/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 9436851 m, 113691 m/sec, 95096623 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 305 secs. Pages in use: 130
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 100/282 41/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 9800681 m, 72766 m/sec, 100038200 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 310 secs. Pages in use: 132
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 105/282 43/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 10242062 m, 88276 m/sec, 104700286 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 315 secs. Pages in use: 134
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 110/282 44/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 10648488 m, 81285 m/sec, 109383860 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 320 secs. Pages in use: 135
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 115/282 46/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 11061659 m, 82634 m/sec, 114606523 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 325 secs. Pages in use: 137
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 120/282 49/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 11656524 m, 118973 m/sec, 118396185 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 330 secs. Pages in use: 140
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 125/282 51/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 12146568 m, 98008 m/sec, 123336814 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 335 secs. Pages in use: 142
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 130/282 53/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 12706344 m, 111955 m/sec, 127902839 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 340 secs. Pages in use: 144
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 135/282 55/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 13294931 m, 117717 m/sec, 132280889 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 345 secs. Pages in use: 146
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 140/282 57/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 13578367 m, 56687 m/sec, 137518802 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 350 secs. Pages in use: 148
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 145/282 58/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 13975778 m, 79482 m/sec, 142031221 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 355 secs. Pages in use: 149
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 150/282 60/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 14352597 m, 75363 m/sec, 146924691 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 360 secs. Pages in use: 151
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 47 (type EXCL) for Diffusion2D-PT-D05N150-CTLFireability-2024-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1242602
[[35mlola[0m][I] fired transitions : 8496059
[[35mlola[0m][I] time used : 159
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 155/282 61/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 14723347 m, 74150 m/sec, 151716865 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 365 secs. Pages in use: 152
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 160/282 63/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 15228011 m, 100932 m/sec, 155907228 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 370 secs. Pages in use: 154
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 165/282 65/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 15597927 m, 73983 m/sec, 160849642 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 375 secs. Pages in use: 156
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 170/282 67/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 15988679 m, 78150 m/sec, 165668050 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 380 secs. Pages in use: 158
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 175/282 68/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 16384579 m, 79180 m/sec, 170400978 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 385 secs. Pages in use: 159
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 180/282 70/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 16877628 m, 98609 m/sec, 174798115 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 390 secs. Pages in use: 161
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 185/282 72/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 17255259 m, 75526 m/sec, 179869868 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 395 secs. Pages in use: 163
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 190/282 73/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 17661026 m, 81153 m/sec, 184756733 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 400 secs. Pages in use: 164
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 195/282 75/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 17961099 m, 60014 m/sec, 189626966 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 405 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 200/282 76/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 18386263 m, 85032 m/sec, 194132307 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 410 secs. Pages in use: 167
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 205/282 79/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 18900125 m, 102772 m/sec, 198052597 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 415 secs. Pages in use: 170
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 210/282 81/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 19503028 m, 120580 m/sec, 202348214 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 420 secs. Pages in use: 172
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 215/282 84/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 20106360 m, 120666 m/sec, 206319972 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 425 secs. Pages in use: 175
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 220/282 85/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 20498658 m, 78459 m/sec, 210786070 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 430 secs. Pages in use: 176
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 225/282 87/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 20895564 m, 79381 m/sec, 215260626 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 435 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 230/282 88/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 21230113 m, 66909 m/sec, 220009740 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 440 secs. Pages in use: 179
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 235/282 90/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 21678619 m, 89701 m/sec, 224464389 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 445 secs. Pages in use: 181
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 240/282 92/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 22084676 m, 81211 m/sec, 229086292 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 450 secs. Pages in use: 183
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 245/282 94/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 22535354 m, 90135 m/sec, 233225036 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 455 secs. Pages in use: 185
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 250/282 95/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 22866227 m, 66174 m/sec, 238285331 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 460 secs. Pages in use: 186
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 255/282 97/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 23320591 m, 90872 m/sec, 242176462 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 465 secs. Pages in use: 188
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 260/282 98/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 23584342 m, 52750 m/sec, 247286076 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 470 secs. Pages in use: 189
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 265/282 99/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 23862063 m, 55544 m/sec, 252627493 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 475 secs. Pages in use: 190
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 270/282 101/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 24308183 m, 89224 m/sec, 257176200 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 480 secs. Pages in use: 192
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 275/282 102/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 24638158 m, 65995 m/sec, 261804634 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 485 secs. Pages in use: 193
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 280/282 104/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-09 25015803 m, 75529 m/sec, 265935056 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 490 secs. Pages in use: 195
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 44 (type EXCL) for Diffusion2D-PT-D05N150-CTLFireability-2024-09 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 495 secs. Pages in use: 196
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 41 (type EXCL) for 40 Diffusion2D-PT-D05N150-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 282 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 44 (type EXCL) for 43 Diffusion2D-PT-D05N150-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 3105 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 41 (type EXCL) for Diffusion2D-PT-D05N150-CTLFireability-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 299
[[35mlola[0m][I] fired transitions : 298
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 5/282 3/5 Diffusion2D-PT-D05N150-CTLFireability-2024-09 586665 m, -4885827 m/sec, 6070827 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 500 secs. Pages in use: 201
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 10/282 5/5 Diffusion2D-PT-D05N150-CTLFireability-2024-09 1189303 m, 120527 m/sec, 11252824 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 505 secs. Pages in use: 205
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 44 (type EXCL) for Diffusion2D-PT-D05N150-CTLFireability-2024-09 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 510 secs. Pages in use: 205
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 38 (type EXCL) for 33 Diffusion2D-PT-D05N150-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 309 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 5/309 5/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-07 1058690 m, 211738 m/sec, 7689594 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 515 secs. Pages in use: 208
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 10/309 9/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-07 1962473 m, 180756 m/sec, 14592104 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 520 secs. Pages in use: 214
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 15/309 12/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-07 2810691 m, 169643 m/sec, 21246157 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 525 secs. Pages in use: 218
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 20/309 16/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-07 3721341 m, 182130 m/sec, 28040982 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 530 secs. Pages in use: 225
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 25/309 20/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-07 4630993 m, 181930 m/sec, 34789621 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 535 secs. Pages in use: 231
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDiffusion2D-PT-D05N150-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDiffusion2D-PT-D05N150-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-02: CONJ 0 2 0 0 7 0 0 2
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Diffusion2D-PT-D05N150-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 35/309 20/2000 Diffusion2D-PT-D05N150-CTLFireability-2024-07 4743311 m, 22463 m/sec, 35777753 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 545 secs. Pages in use: 231
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 403 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Diffusion2D-PT-D05N150"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is Diffusion2D-PT-D05N150, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r137-tall-171631133600154"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/Diffusion2D-PT-D05N150.tgz
mv Diffusion2D-PT-D05N150 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;