About the Execution of 2023-gold for DLCround-PT-07b
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 6472.031 | 128709.00 | 356609.00 | 535.70 | TFTTFTFTTFTTFFFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r131-smll-171624288400119.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool gold2023
Input is DLCround-PT-07b, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r131-smll-171624288400119
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.5M
-rw-r--r-- 1 mcc users 7.7K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 87K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.5K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 48K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.9K Apr 22 14:38 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Apr 22 14:38 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Apr 22 14:38 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Apr 22 14:38 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Apr 13 12:32 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 154K Apr 13 12:32 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.5K Apr 13 12:31 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 51K Apr 13 12:31 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 22 14:38 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Apr 22 14:38 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 4 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 963K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-07b-ReachabilityCardinality-2024-00
FORMULA_NAME DLCround-PT-07b-ReachabilityCardinality-2024-01
FORMULA_NAME DLCround-PT-07b-ReachabilityCardinality-2024-02
FORMULA_NAME DLCround-PT-07b-ReachabilityCardinality-2024-03
FORMULA_NAME DLCround-PT-07b-ReachabilityCardinality-2024-04
FORMULA_NAME DLCround-PT-07b-ReachabilityCardinality-2024-05
FORMULA_NAME DLCround-PT-07b-ReachabilityCardinality-2024-06
FORMULA_NAME DLCround-PT-07b-ReachabilityCardinality-2024-07
FORMULA_NAME DLCround-PT-07b-ReachabilityCardinality-2024-08
FORMULA_NAME DLCround-PT-07b-ReachabilityCardinality-2024-09
FORMULA_NAME DLCround-PT-07b-ReachabilityCardinality-2024-10
FORMULA_NAME DLCround-PT-07b-ReachabilityCardinality-2024-11
FORMULA_NAME DLCround-PT-07b-ReachabilityCardinality-2024-12
FORMULA_NAME DLCround-PT-07b-ReachabilityCardinality-2024-13
FORMULA_NAME DLCround-PT-07b-ReachabilityCardinality-2024-14
FORMULA_NAME DLCround-PT-07b-ReachabilityCardinality-2024-15
=== Now, execution of the tool begins
BK_START 1716394987673
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=gold2023
BK_EXAMINATION=ReachabilityCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCround-PT-07b
Applying reductions before tool lola
Invoking reducer
Running Version 202304061127
[2024-05-22 16:23:10] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -timeout, 360, -rebuildPNML]
[2024-05-22 16:23:10] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2024-05-22 16:23:10] [INFO ] Load time of PNML (sax parser for PT used): 406 ms
[2024-05-22 16:23:10] [INFO ] Transformed 2703 places.
[2024-05-22 16:23:10] [INFO ] Transformed 4071 transitions.
[2024-05-22 16:23:10] [INFO ] Found NUPN structural information;
[2024-05-22 16:23:10] [INFO ] Parsed PT model containing 2703 places and 4071 transitions and 11073 arcs in 593 ms.
Parsed 16 properties from file /home/mcc/execution/ReachabilityCardinality.xml in 32 ms.
Working with output stream class java.io.PrintStream
FORMULA DLCround-PT-07b-ReachabilityCardinality-2024-02 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA DLCround-PT-07b-ReachabilityCardinality-2024-07 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA DLCround-PT-07b-ReachabilityCardinality-2024-14 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Incomplete random walk after 10000 steps, including 2 resets, run finished after 702 ms. (steps per millisecond=14 ) properties (out of 13) seen :7
FORMULA DLCround-PT-07b-ReachabilityCardinality-2024-15 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-07b-ReachabilityCardinality-2024-11 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-07b-ReachabilityCardinality-2024-10 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-07b-ReachabilityCardinality-2024-06 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-07b-ReachabilityCardinality-2024-05 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-07b-ReachabilityCardinality-2024-04 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-07b-ReachabilityCardinality-2024-01 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 51 ms. (steps per millisecond=196 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=333 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 42 ms. (steps per millisecond=238 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 43 ms. (steps per millisecond=232 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 111 ms. (steps per millisecond=90 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 38 ms. (steps per millisecond=263 ) properties (out of 6) seen :0
Running SMT prover for 6 properties.
// Phase 1: matrix 4071 rows 2703 cols
[2024-05-22 16:23:12] [INFO ] Computed 132 invariants in 59 ms
[2024-05-22 16:23:13] [INFO ] After 1512ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:6
[2024-05-22 16:23:14] [INFO ] [Nat]Absence check using 132 positive place invariants in 161 ms returned sat
[2024-05-22 16:23:18] [INFO ] After 3435ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :6
[2024-05-22 16:23:19] [INFO ] Deduced a trap composed of 107 places in 954 ms of which 32 ms to minimize.
[2024-05-22 16:23:19] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 1317 ms
[2024-05-22 16:23:21] [INFO ] Deduced a trap composed of 160 places in 695 ms of which 2 ms to minimize.
[2024-05-22 16:23:21] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 1070 ms
[2024-05-22 16:23:23] [INFO ] Deduced a trap composed of 163 places in 723 ms of which 3 ms to minimize.
[2024-05-22 16:23:23] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 1073 ms
[2024-05-22 16:23:23] [INFO ] After 8342ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :6
Attempting to minimize the solution found.
Minimization took 1078 ms.
[2024-05-22 16:23:24] [INFO ] After 10887ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :6
FORMULA DLCround-PT-07b-ReachabilityCardinality-2024-12 FALSE TECHNIQUES TOPOLOGICAL PARIKH_WALK
FORMULA DLCround-PT-07b-ReachabilityCardinality-2024-00 TRUE TECHNIQUES TOPOLOGICAL PARIKH_WALK
FORMULA DLCround-PT-07b-ReachabilityCardinality-2024-03 TRUE TECHNIQUES TOPOLOGICAL PARIKH_WALK
FORMULA DLCround-PT-07b-ReachabilityCardinality-2024-13 FALSE TECHNIQUES TOPOLOGICAL PARIKH_WALK
Parikh walk visited 4 properties in 236 ms.
Support contains 21 out of 2703 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 2703/2703 places, 4071/4071 transitions.
Graph (trivial) has 2507 edges and 2703 vertex of which 489 / 2703 are part of one of the 37 SCC in 23 ms
Free SCC test removed 452 places
Drop transitions removed 507 transitions
Reduce isomorphic transitions removed 507 transitions.
Drop transitions removed 987 transitions
Trivial Post-agglo rules discarded 987 transitions
Performed 987 trivial Post agglomeration. Transition count delta: 987
Iterating post reduction 0 with 987 rules applied. Total rules applied 988 place count 2251 transition count 2577
Reduce places removed 987 places and 0 transitions.
Ensure Unique test removed 35 transitions
Reduce isomorphic transitions removed 35 transitions.
Drop transitions removed 28 transitions
Trivial Post-agglo rules discarded 28 transitions
Performed 28 trivial Post agglomeration. Transition count delta: 28
Iterating post reduction 1 with 1050 rules applied. Total rules applied 2038 place count 1264 transition count 2514
Reduce places removed 28 places and 0 transitions.
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Drop transitions removed 4 transitions
Trivial Post-agglo rules discarded 4 transitions
Performed 4 trivial Post agglomeration. Transition count delta: 4
Iterating post reduction 2 with 36 rules applied. Total rules applied 2074 place count 1236 transition count 2506
Reduce places removed 4 places and 0 transitions.
Performed 11 Post agglomeration using F-continuation condition.Transition count delta: 11
Iterating post reduction 3 with 15 rules applied. Total rules applied 2089 place count 1232 transition count 2495
Reduce places removed 11 places and 0 transitions.
Iterating post reduction 4 with 11 rules applied. Total rules applied 2100 place count 1221 transition count 2495
Performed 4 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 4 Pre rules applied. Total rules applied 2100 place count 1221 transition count 2491
Deduced a syphon composed of 4 places in 11 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 5 with 8 rules applied. Total rules applied 2108 place count 1217 transition count 2491
Discarding 328 places :
Symmetric choice reduction at 5 with 328 rule applications. Total rules 2436 place count 889 transition count 2163
Iterating global reduction 5 with 328 rules applied. Total rules applied 2764 place count 889 transition count 2163
Performed 137 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 137 Pre rules applied. Total rules applied 2764 place count 889 transition count 2026
Deduced a syphon composed of 137 places in 28 ms
Reduce places removed 137 places and 0 transitions.
Iterating global reduction 5 with 274 rules applied. Total rules applied 3038 place count 752 transition count 2026
Discarding 58 places :
Symmetric choice reduction at 5 with 58 rule applications. Total rules 3096 place count 694 transition count 1412
Iterating global reduction 5 with 58 rules applied. Total rules applied 3154 place count 694 transition count 1412
Ensure Unique test removed 21 transitions
Reduce isomorphic transitions removed 21 transitions.
Iterating post reduction 5 with 21 rules applied. Total rules applied 3175 place count 694 transition count 1391
Performed 184 Post agglomeration using F-continuation condition with reduction of 8 identical transitions.
Deduced a syphon composed of 184 places in 1 ms
Reduce places removed 184 places and 0 transitions.
Iterating global reduction 6 with 368 rules applied. Total rules applied 3543 place count 510 transition count 1199
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed 7 transitions.
Iterating post reduction 6 with 7 rules applied. Total rules applied 3550 place count 510 transition count 1192
Discarding 1 places :
Symmetric choice reduction at 7 with 1 rule applications. Total rules 3551 place count 509 transition count 1181
Iterating global reduction 7 with 1 rules applied. Total rules applied 3552 place count 509 transition count 1181
Performed 46 Post agglomeration using F-continuation condition.Transition count delta: -406
Deduced a syphon composed of 46 places in 2 ms
Reduce places removed 46 places and 0 transitions.
Iterating global reduction 7 with 92 rules applied. Total rules applied 3644 place count 463 transition count 1587
Drop transitions removed 43 transitions
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 47 transitions.
Iterating post reduction 7 with 47 rules applied. Total rules applied 3691 place count 463 transition count 1540
Discarding 19 places :
Symmetric choice reduction at 8 with 19 rule applications. Total rules 3710 place count 444 transition count 1127
Iterating global reduction 8 with 19 rules applied. Total rules applied 3729 place count 444 transition count 1127
Ensure Unique test removed 15 transitions
Reduce isomorphic transitions removed 15 transitions.
Iterating post reduction 8 with 15 rules applied. Total rules applied 3744 place count 444 transition count 1112
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -20
Deduced a syphon composed of 3 places in 1 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 9 with 6 rules applied. Total rules applied 3750 place count 441 transition count 1132
Drop transitions removed 117 transitions
Redundant transition composition rules discarded 117 transitions
Iterating global reduction 9 with 117 rules applied. Total rules applied 3867 place count 441 transition count 1015
Discarding 8 places :
Symmetric choice reduction at 9 with 8 rule applications. Total rules 3875 place count 433 transition count 919
Iterating global reduction 9 with 8 rules applied. Total rules applied 3883 place count 433 transition count 919
Ensure Unique test removed 8 transitions
Reduce isomorphic transitions removed 8 transitions.
Iterating post reduction 9 with 8 rules applied. Total rules applied 3891 place count 433 transition count 911
Free-agglomeration rule applied 247 times with reduction of 138 identical transitions.
Iterating global reduction 10 with 247 rules applied. Total rules applied 4138 place count 433 transition count 526
Reduce places removed 247 places and 0 transitions.
Drop transitions removed 283 transitions
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 287 transitions.
Graph (complete) has 383 edges and 186 vertex of which 130 are kept as prefixes of interest. Removing 56 places using SCC suffix rule.2 ms
Discarding 56 places :
Also discarding 22 output transitions
Drop transitions removed 22 transitions
Iterating post reduction 10 with 535 rules applied. Total rules applied 4673 place count 130 transition count 217
Drop transitions removed 23 transitions
Ensure Unique test removed 22 transitions
Reduce isomorphic transitions removed 45 transitions.
Iterating post reduction 11 with 45 rules applied. Total rules applied 4718 place count 130 transition count 172
Discarding 38 places :
Symmetric choice reduction at 12 with 38 rule applications. Total rules 4756 place count 92 transition count 134
Iterating global reduction 12 with 38 rules applied. Total rules applied 4794 place count 92 transition count 134
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 2 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 12 with 2 rules applied. Total rules applied 4796 place count 91 transition count 133
Drop transitions removed 12 transitions
Redundant transition composition rules discarded 12 transitions
Iterating global reduction 12 with 12 rules applied. Total rules applied 4808 place count 91 transition count 121
Reduce places removed 1 places and 0 transitions.
Graph (complete) has 190 edges and 90 vertex of which 87 are kept as prefixes of interest. Removing 3 places using SCC suffix rule.0 ms
Discarding 3 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Iterating post reduction 12 with 2 rules applied. Total rules applied 4810 place count 87 transition count 120
Drop transitions removed 1 transitions
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 13 with 3 rules applied. Total rules applied 4813 place count 87 transition count 117
Discarding 3 places :
Symmetric choice reduction at 14 with 3 rule applications. Total rules 4816 place count 84 transition count 114
Iterating global reduction 14 with 3 rules applied. Total rules applied 4819 place count 84 transition count 114
Partial Free-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 14 with 1 rules applied. Total rules applied 4820 place count 84 transition count 114
Applied a total of 4820 rules in 797 ms. Remains 84 /2703 variables (removed 2619) and now considering 114/4071 (removed 3957) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 797 ms. Remains : 84/2703 places, 114/4071 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 50 ms. (steps per millisecond=200 ) properties (out of 2) seen :1
FORMULA DLCround-PT-07b-ReachabilityCardinality-2024-09 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Finished Best-First random walk after 3547 steps, including 1 resets, run visited all 1 properties in 10 ms. (steps per millisecond=354 )
FORMULA DLCround-PT-07b-ReachabilityCardinality-2024-08 TRUE TECHNIQUES TOPOLOGICAL BESTFIRST_WALK
Parikh walk visited 0 properties in 0 ms.
All properties solved without resorting to model-checking.
Total runtime 15604 ms.
starting LoLA
BK_INPUT DLCround-PT-07b
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution
ReachabilityCardinality
FORMULA DLCround-PT-07b-ReachabilityCardinality-2024-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07b-ReachabilityCardinality-2024-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07b-ReachabilityCardinality-2024-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07b-ReachabilityCardinality-2024-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07b-ReachabilityCardinality-2024-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07b-ReachabilityCardinality-2024-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07b-ReachabilityCardinality-2024-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07b-ReachabilityCardinality-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07b-ReachabilityCardinality-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07b-ReachabilityCardinality-2024-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07b-ReachabilityCardinality-2024-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07b-ReachabilityCardinality-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07b-ReachabilityCardinality-2024-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07b-ReachabilityCardinality-2024-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07b-ReachabilityCardinality-2024-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07b-ReachabilityCardinality-2024-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1716395116382
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202304061127.jar
+ VERSION=202304061127
+ echo 'Running Version 202304061127'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination ReachabilityCardinality -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/ReachabilityCardinality.xml
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 56 (type EXCL) for 0 DLCround-PT-07b-ReachabilityCardinality-2024-00
lola: time limit : 222 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 58 (type FNDP) for 9 DLCround-PT-07b-ReachabilityCardinality-2024-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 59 (type EQUN) for 9 DLCround-PT-07b-ReachabilityCardinality-2024-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 61 (type SRCH) for 9 DLCround-PT-07b-ReachabilityCardinality-2024-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 61 (type SRCH) for DLCround-PT-07b-ReachabilityCardinality-2024-03
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: CANCELED task # 58 (type FNDP) for DLCround-PT-07b-ReachabilityCardinality-2024-03 (obsolete)
lola: CANCELED task # 59 (type EQUN) for DLCround-PT-07b-ReachabilityCardinality-2024-03 (obsolete)
lola: LAUNCH task # 51 (type FNDP) for 0 DLCround-PT-07b-ReachabilityCardinality-2024-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 53 (type EQUN) for 0 DLCround-PT-07b-ReachabilityCardinality-2024-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 55 (type SRCH) for 0 DLCround-PT-07b-ReachabilityCardinality-2024-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 58 (type FNDP) for DLCround-PT-07b-ReachabilityCardinality-2024-03
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 51 (type FNDP) for DLCround-PT-07b-ReachabilityCardinality-2024-00
lola: result : true
lola: fired transitions : 66
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 53 (type EQUN) for DLCround-PT-07b-ReachabilityCardinality-2024-00 (obsolete)
lola: CANCELED task # 55 (type SRCH) for DLCround-PT-07b-ReachabilityCardinality-2024-00 (obsolete)
lola: CANCELED task # 56 (type EXCL) for DLCround-PT-07b-ReachabilityCardinality-2024-00 (obsolete)
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-59.sara.
sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-53.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 76 (type EXCL) for 45 DLCround-PT-07b-ReachabilityCardinality-2024-15
lola: time limit : 508 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 72 (type FNDP) for 45 DLCround-PT-07b-ReachabilityCardinality-2024-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 73 (type EQUN) for 45 DLCround-PT-07b-ReachabilityCardinality-2024-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 75 (type SRCH) for 45 DLCround-PT-07b-ReachabilityCardinality-2024-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 59 (type EQUN) for DLCround-PT-07b-ReachabilityCardinality-2024-03
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 76 (type EXCL) for DLCround-PT-07b-ReachabilityCardinality-2024-15
lola: result : true
lola: markings : 93
lola: fired transitions : 92
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 72 (type FNDP) for DLCround-PT-07b-ReachabilityCardinality-2024-15 (obsolete)
lola: CANCELED task # 73 (type EQUN) for DLCround-PT-07b-ReachabilityCardinality-2024-15 (obsolete)
lola: CANCELED task # 75 (type SRCH) for DLCround-PT-07b-ReachabilityCardinality-2024-15 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 119 (type EXCL) for 33 DLCround-PT-07b-ReachabilityCardinality-2024-11
lola: time limit : 395 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 97 (type SRCH) for 27 DLCround-PT-07b-ReachabilityCardinality-2024-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 123 (type SRCH) for 27 DLCround-PT-07b-ReachabilityCardinality-2024-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 49 (type FNDP) for 3 DLCround-PT-07b-ReachabilityCardinality-2024-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 53 (type EQUN) for DLCround-PT-07b-ReachabilityCardinality-2024-00
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 97 (type SRCH) for DLCround-PT-07b-ReachabilityCardinality-2024-09
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 123 (type SRCH) for DLCround-PT-07b-ReachabilityCardinality-2024-09
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 99 (type FNDP) for 21 DLCround-PT-07b-ReachabilityCardinality-2024-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 110 (type EQUN) for 21 DLCround-PT-07b-ReachabilityCardinality-2024-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 72 (type FNDP) for DLCround-PT-07b-ReachabilityCardinality-2024-15
lola: result : true
lola: fired transitions : 4
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 49 (type FNDP) for DLCround-PT-07b-ReachabilityCardinality-2024-01
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: LAUNCH task # 121 (type FNDP) for 6 DLCround-PT-07b-ReachabilityCardinality-2024-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 119 (type EXCL) for DLCround-PT-07b-ReachabilityCardinality-2024-11
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 133 (type EXCL) for 18 DLCround-PT-07b-ReachabilityCardinality-2024-06
lola: time limit : 356 sec
lola: memory limit: 32 pages
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-73.sara.
lola: FINISHED task # 133 (type EXCL) for DLCround-PT-07b-ReachabilityCardinality-2024-06
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 137 (type EXCL) for 39 DLCround-PT-07b-ReachabilityCardinality-2024-13
lola: time limit : 395 sec
lola: memory limit: 32 pages
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-110.sara.
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-ReachabilityCardinality-2024-00: EF true findpath
DLCround-PT-07b-ReachabilityCardinality-2024-01: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-2024-03: EF true tandem / insertion
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lola: FINISHED task # 73 (type EQUN) for DLCround-PT-07b-ReachabilityCardinality-2024-15
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-ReachabilityCardinality-2024-00: EF true findpath
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCround-PT-07b-ReachabilityCardinality-2024-00: EF true findpath
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DLCround-PT-07b-ReachabilityCardinality-2024-00: EF true findpath
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DLCround-PT-07b-ReachabilityCardinality-2024-00: EF true findpath
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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110 EF STEQ 27/274 0/5 DLCround-PT-07b-ReachabilityCardinality-2024-07 sara is running.
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DLCround-PT-07b-ReachabilityCardinality-2024-00: EF true findpath
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
99 EF FNDP 32/269 0/5 DLCround-PT-07b-ReachabilityCardinality-2024-07 1794941 t fired, 2 attempts, .
110 EF STEQ 32/269 0/5 DLCround-PT-07b-ReachabilityCardinality-2024-07 sara is running.
121 EF FNDP 32/269 0/5 DLCround-PT-07b-ReachabilityCardinality-2024-02 178491903 t fired, 89245952 attempts, .
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DLCround-PT-07b-ReachabilityCardinality-2024-00: EF true findpath
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DLCround-PT-07b-ReachabilityCardinality-2024-03: EF true tandem / insertion
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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121 EF FNDP 37/264 0/5 DLCround-PT-07b-ReachabilityCardinality-2024-02 208928114 t fired, 104464058 attempts, .
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lola: rewrite Frontend/Parser/formula_rewrite.k:787
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sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-90.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-77.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-148.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-108.sara.
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
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DLCround-PT-07b-ReachabilityCardinality-2024-05: EF 0 5 0 0 1 0 0 0
DLCround-PT-07b-ReachabilityCardinality-2024-13: AG 0 4 1 0 1 0 0 0
DLCround-PT-07b-ReachabilityCardinality-2024-14: EF 0 3 2 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
82 EF FNDP 3/587 0/5 DLCround-PT-07b-ReachabilityCardinality-2024-14 194545 t fired, 1 attempts, .
90 EF STEQ 3/704 0/5 DLCround-PT-07b-ReachabilityCardinality-2024-14 sara is running.
121 EF FNDP 42/673 0/5 DLCround-PT-07b-ReachabilityCardinality-2024-02 231308902 t fired, 115654452 attempts, .
137 EF EXCL 42/890 1/32 DLCround-PT-07b-ReachabilityCardinality-2024-13 139041 m, 2350 m/sec, 259626 t fired, .
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# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-ReachabilityCardinality-2024-00: EF true findpath
DLCround-PT-07b-ReachabilityCardinality-2024-01: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-2024-03: EF true tandem / insertion
DLCround-PT-07b-ReachabilityCardinality-2024-04: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-2024-06: AG false tandem / relaxed
DLCround-PT-07b-ReachabilityCardinality-2024-07: AG true state equation
DLCround-PT-07b-ReachabilityCardinality-2024-08: EF true findpath
DLCround-PT-07b-ReachabilityCardinality-2024-09: AG false tandem / insertion
DLCround-PT-07b-ReachabilityCardinality-2024-10: EF true findpath
DLCround-PT-07b-ReachabilityCardinality-2024-11: EF true tandem / relaxed
DLCround-PT-07b-ReachabilityCardinality-2024-12: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-2024-15: AG false tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-ReachabilityCardinality-2024-02: AG 0 4 1 0 1 0 0 0
DLCround-PT-07b-ReachabilityCardinality-2024-05: EF 0 5 0 0 1 0 0 0
DLCround-PT-07b-ReachabilityCardinality-2024-13: AG 0 4 1 0 1 0 0 0
DLCround-PT-07b-ReachabilityCardinality-2024-14: EF 0 3 2 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
82 EF FNDP 8/584 0/5 DLCround-PT-07b-ReachabilityCardinality-2024-14 529797 t fired, 1 attempts, .
90 EF STEQ 8/701 0/5 DLCround-PT-07b-ReachabilityCardinality-2024-14 sara is running.
121 EF FNDP 47/670 0/5 DLCround-PT-07b-ReachabilityCardinality-2024-02 248572720 t fired, 124286361 attempts, .
137 EF EXCL 47/890 1/32 DLCround-PT-07b-ReachabilityCardinality-2024-13 148020 m, 1795 m/sec, 276946 t fired, .
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# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-ReachabilityCardinality-2024-00: EF true findpath
DLCround-PT-07b-ReachabilityCardinality-2024-01: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-2024-03: EF true tandem / insertion
DLCround-PT-07b-ReachabilityCardinality-2024-04: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-2024-06: AG false tandem / relaxed
DLCround-PT-07b-ReachabilityCardinality-2024-07: AG true state equation
DLCround-PT-07b-ReachabilityCardinality-2024-08: EF true findpath
DLCround-PT-07b-ReachabilityCardinality-2024-09: AG false tandem / insertion
DLCround-PT-07b-ReachabilityCardinality-2024-10: EF true findpath
DLCround-PT-07b-ReachabilityCardinality-2024-11: EF true tandem / relaxed
DLCround-PT-07b-ReachabilityCardinality-2024-12: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-2024-15: AG false tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-ReachabilityCardinality-2024-02: AG 0 4 1 0 1 0 0 0
DLCround-PT-07b-ReachabilityCardinality-2024-05: EF 0 5 0 0 1 0 0 0
DLCround-PT-07b-ReachabilityCardinality-2024-13: AG 0 4 1 0 1 0 0 0
DLCround-PT-07b-ReachabilityCardinality-2024-14: EF 0 3 2 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
82 EF FNDP 13/579 0/5 DLCround-PT-07b-ReachabilityCardinality-2024-14 812674 t fired, 1 attempts, .
90 EF STEQ 13/696 0/5 DLCround-PT-07b-ReachabilityCardinality-2024-14 sara is running.
121 EF FNDP 52/665 0/5 DLCround-PT-07b-ReachabilityCardinality-2024-02 263645402 t fired, 131822702 attempts, .
137 EF EXCL 52/890 1/32 DLCround-PT-07b-ReachabilityCardinality-2024-13 157125 m, 1821 m/sec, 294774 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-ReachabilityCardinality-2024-00: EF true findpath
DLCround-PT-07b-ReachabilityCardinality-2024-01: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-2024-03: EF true tandem / insertion
DLCround-PT-07b-ReachabilityCardinality-2024-04: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-2024-06: AG false tandem / relaxed
DLCround-PT-07b-ReachabilityCardinality-2024-07: AG true state equation
DLCround-PT-07b-ReachabilityCardinality-2024-08: EF true findpath
DLCround-PT-07b-ReachabilityCardinality-2024-09: AG false tandem / insertion
DLCround-PT-07b-ReachabilityCardinality-2024-10: EF true findpath
DLCround-PT-07b-ReachabilityCardinality-2024-11: EF true tandem / relaxed
DLCround-PT-07b-ReachabilityCardinality-2024-12: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-2024-15: AG false tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-ReachabilityCardinality-2024-02: AG 0 4 1 0 1 0 0 0
DLCround-PT-07b-ReachabilityCardinality-2024-05: EF 0 5 0 0 1 0 0 0
DLCround-PT-07b-ReachabilityCardinality-2024-13: AG 0 4 1 0 1 0 0 0
DLCround-PT-07b-ReachabilityCardinality-2024-14: EF 0 3 2 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
82 EF FNDP 18/574 0/5 DLCround-PT-07b-ReachabilityCardinality-2024-14 954438 t fired, 1 attempts, .
90 EF STEQ 18/691 0/5 DLCround-PT-07b-ReachabilityCardinality-2024-14 sara is running.
121 EF FNDP 57/660 0/5 DLCround-PT-07b-ReachabilityCardinality-2024-02 281119030 t fired, 140559515 attempts, .
137 EF EXCL 57/890 2/32 DLCround-PT-07b-ReachabilityCardinality-2024-13 165478 m, 1670 m/sec, 311109 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-ReachabilityCardinality-2024-00: EF true findpath
DLCround-PT-07b-ReachabilityCardinality-2024-01: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-2024-03: EF true tandem / insertion
DLCround-PT-07b-ReachabilityCardinality-2024-04: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-2024-06: AG false tandem / relaxed
DLCround-PT-07b-ReachabilityCardinality-2024-07: AG true state equation
DLCround-PT-07b-ReachabilityCardinality-2024-08: EF true findpath
DLCround-PT-07b-ReachabilityCardinality-2024-09: AG false tandem / insertion
DLCround-PT-07b-ReachabilityCardinality-2024-10: EF true findpath
DLCround-PT-07b-ReachabilityCardinality-2024-11: EF true tandem / relaxed
DLCround-PT-07b-ReachabilityCardinality-2024-12: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-2024-15: AG false tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-ReachabilityCardinality-2024-02: AG 0 4 1 0 1 0 0 0
DLCround-PT-07b-ReachabilityCardinality-2024-05: EF 0 5 0 0 1 0 0 0
DLCround-PT-07b-ReachabilityCardinality-2024-13: AG 0 4 1 0 1 0 0 0
DLCround-PT-07b-ReachabilityCardinality-2024-14: EF 0 3 2 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
82 EF FNDP 23/569 0/5 DLCround-PT-07b-ReachabilityCardinality-2024-14 1106430 t fired, 2 attempts, .
90 EF STEQ 23/686 0/5 DLCround-PT-07b-ReachabilityCardinality-2024-14 sara is running.
121 EF FNDP 62/655 0/5 DLCround-PT-07b-ReachabilityCardinality-2024-02 300096746 t fired, 150048374 attempts, .
137 EF EXCL 62/890 2/32 DLCround-PT-07b-ReachabilityCardinality-2024-13 174428 m, 1790 m/sec, 327901 t fired, .
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# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-ReachabilityCardinality-2024-00: EF true findpath
DLCround-PT-07b-ReachabilityCardinality-2024-01: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-2024-03: EF true tandem / insertion
DLCround-PT-07b-ReachabilityCardinality-2024-04: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-2024-06: AG false tandem / relaxed
DLCround-PT-07b-ReachabilityCardinality-2024-07: AG true state equation
DLCround-PT-07b-ReachabilityCardinality-2024-08: EF true findpath
DLCround-PT-07b-ReachabilityCardinality-2024-09: AG false tandem / insertion
DLCround-PT-07b-ReachabilityCardinality-2024-10: EF true findpath
DLCround-PT-07b-ReachabilityCardinality-2024-11: EF true tandem / relaxed
DLCround-PT-07b-ReachabilityCardinality-2024-12: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-2024-15: AG false tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-ReachabilityCardinality-2024-02: AG 0 4 1 0 1 0 0 0
DLCround-PT-07b-ReachabilityCardinality-2024-05: EF 0 5 0 0 1 0 0 0
DLCround-PT-07b-ReachabilityCardinality-2024-13: AG 0 4 1 0 1 0 0 0
DLCround-PT-07b-ReachabilityCardinality-2024-14: EF 0 3 2 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
82 EF FNDP 28/564 0/5 DLCround-PT-07b-ReachabilityCardinality-2024-14 1240286 t fired, 2 attempts, .
90 EF STEQ 28/681 0/5 DLCround-PT-07b-ReachabilityCardinality-2024-14 sara is running.
121 EF FNDP 67/650 0/5 DLCround-PT-07b-ReachabilityCardinality-2024-02 317132062 t fired, 158566032 attempts, .
137 EF EXCL 67/890 2/32 DLCround-PT-07b-ReachabilityCardinality-2024-13 184629 m, 2040 m/sec, 346973 t fired, .
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lola: FINISHED task # 90 (type EQUN) for DLCround-PT-07b-ReachabilityCardinality-2024-14
lola: result : false
lola: CANCELED task # 82 (type FNDP) for DLCround-PT-07b-ReachabilityCardinality-2024-14 (obsolete)
lola: LAUNCH task # 89 (type FNDP) for 15 DLCround-PT-07b-ReachabilityCardinality-2024-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 105 (type EQUN) for 15 DLCround-PT-07b-ReachabilityCardinality-2024-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 82 (type FNDP) for DLCround-PT-07b-ReachabilityCardinality-2024-14
lola: result : unknown
lola: fired transitions : 1328211
lola: tried executions : 3
lola: time used : 31.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 89 (type FNDP) for DLCround-PT-07b-ReachabilityCardinality-2024-05
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 105 (type EQUN) for DLCround-PT-07b-ReachabilityCardinality-2024-05 (obsolete)
lola: LAUNCH task # 134 (type EQUN) for 6 DLCround-PT-07b-ReachabilityCardinality-2024-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 141 (type SRCH) for 6 DLCround-PT-07b-ReachabilityCardinality-2024-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 141 (type SRCH) for DLCround-PT-07b-ReachabilityCardinality-2024-02
lola: result : false
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 121 (type FNDP) for DLCround-PT-07b-ReachabilityCardinality-2024-02 (obsolete)
lola: CANCELED task # 134 (type EQUN) for DLCround-PT-07b-ReachabilityCardinality-2024-02 (obsolete)
lola: LAUNCH task # 95 (type FNDP) for 39 DLCround-PT-07b-ReachabilityCardinality-2024-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 120 (type EQUN) for 39 DLCround-PT-07b-ReachabilityCardinality-2024-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 136 (type SRCH) for 39 DLCround-PT-07b-ReachabilityCardinality-2024-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 121 (type FNDP) for DLCround-PT-07b-ReachabilityCardinality-2024-02
lola: result : unknown
lola: fired transitions : 329901799
lola: tried executions : 164950901
lola: time used : 70.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 134 (type EQUN) for DLCround-PT-07b-ReachabilityCardinality-2024-02
lola: result : unknown
lola: FINISHED task # 95 (type FNDP) for DLCround-PT-07b-ReachabilityCardinality-2024-13
lola: result : true
lola: fired transitions : 9
lola: tried executions : 1
lola: time used : 1.000000
lola: memory pages used : 0
lola: FINISHED task # 136 (type SRCH) for DLCround-PT-07b-ReachabilityCardinality-2024-13
lola: result : true
lola: markings : 11
lola: fired transitions : 10
lola: time used : 1.000000
lola: memory pages used : 1
lola: CANCELED task # 120 (type EQUN) for DLCround-PT-07b-ReachabilityCardinality-2024-13 (obsolete)
lola: CANCELED task # 137 (type EXCL) for DLCround-PT-07b-ReachabilityCardinality-2024-13 (obsolete)
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-ReachabilityCardinality-2024-00: EF true findpath
DLCround-PT-07b-ReachabilityCardinality-2024-01: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-2024-02: AG true tandem / insertion
DLCround-PT-07b-ReachabilityCardinality-2024-03: EF true tandem / insertion
DLCround-PT-07b-ReachabilityCardinality-2024-04: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-2024-05: EF true findpath
DLCround-PT-07b-ReachabilityCardinality-2024-06: AG false tandem / relaxed
DLCround-PT-07b-ReachabilityCardinality-2024-07: AG true state equation
DLCround-PT-07b-ReachabilityCardinality-2024-08: EF true findpath
DLCround-PT-07b-ReachabilityCardinality-2024-09: AG false tandem / insertion
DLCround-PT-07b-ReachabilityCardinality-2024-10: EF true findpath
DLCround-PT-07b-ReachabilityCardinality-2024-11: EF true tandem / relaxed
DLCround-PT-07b-ReachabilityCardinality-2024-12: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-2024-13: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-2024-14: EF false state equation
DLCround-PT-07b-ReachabilityCardinality-2024-15: AG false tandem / relaxed
Time elapsed: 110 secs. Pages in use: 3
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-07b"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="gold2023"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool gold2023"
echo " Input is DLCround-PT-07b, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r131-smll-171624288400119"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-07b.tgz
mv DLCround-PT-07b execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;