About the Execution of ITS-Tools for DNAwalker-PT-07track28RR
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
520.560 | 103357.00 | 119077.00 | 367.60 | F | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r123-smll-171624284100262.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.................
=====================================================================
Generated by BenchKit 2-5568
Executing tool itstools
Input is DNAwalker-PT-07track28RR, examination is QuasiLiveness
Time confinement is 1800 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r123-smll-171624284100262
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 592K
-rw-r--r-- 1 mcc users 6.2K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 66K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.0K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 64K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 3.3K Apr 22 14:39 LTLCardinality.txt
-rw-r--r-- 1 mcc users 22K Apr 22 14:39 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K May 19 07:16 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 19 18:12 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Apr 13 14:07 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 151K Apr 13 14:07 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.2K Apr 13 14:06 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 76K Apr 13 14:06 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 22 14:39 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Apr 22 14:39 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 12 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 108K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
FORMULA_NAME QuasiLiveness
=== Now, execution of the tool begins
BK_START 1716325212303
Invoking MCC driver with
BK_TOOL=itstools
BK_EXAMINATION=QuasiLiveness
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=1800
BK_INPUT=DNAwalker-PT-07track28RR
BK_MEMORY_CONFINEMENT=16384
Not applying reductions.
Model is PT
QuasiLiveness PT
Running Version 202405141337
[2024-05-21 21:00:13] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, QuasiLiveness, -its, -ltsmin, -greatspnpath, /home/mcc/BenchKit/bin//../itstools/bin//..//greatspn/, -order, META, -manyOrder, -smt, -timeout, 1800]
[2024-05-21 21:00:13] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2024-05-21 21:00:13] [INFO ] Load time of PNML (sax parser for PT used): 73 ms
[2024-05-21 21:00:13] [INFO ] Transformed 34 places.
[2024-05-21 21:00:13] [INFO ] Transformed 250 transitions.
[2024-05-21 21:00:13] [INFO ] Parsed PT model containing 34 places and 250 transitions and 728 arcs in 165 ms.
Starting structural reductions in LIVENESS mode, iteration 0 : 34/34 places, 250/250 transitions.
Applied a total of 0 rules in 8 ms. Remains 34 /34 variables (removed 0) and now considering 250/250 (removed 0) transitions.
Running 234 sub problems to find dead transitions.
[2024-05-21 21:00:13] [INFO ] Flow matrix only has 247 transitions (discarded 3 similar events)
// Phase 1: matrix 247 rows 34 cols
[2024-05-21 21:00:13] [INFO ] Computed 0 invariants in 12 ms
[2024-05-21 21:00:13] [INFO ] State equation strengthened by 54 read => feed constraints.
At refinement iteration 0 (INCLUDED_ONLY) 0/28 variables, 0/0 constraints. Problems are: Problem set: 0 solved, 234 unsolved
At refinement iteration 1 (OVERLAPS) 240/268 variables, 28/28 constraints. Problems are: Problem set: 0 solved, 234 unsolved
At refinement iteration 2 (INCLUDED_ONLY) 0/268 variables, 53/81 constraints. Problems are: Problem set: 0 solved, 234 unsolved
At refinement iteration 3 (INCLUDED_ONLY) 0/268 variables, 0/81 constraints. Problems are: Problem set: 0 solved, 234 unsolved
At refinement iteration 4 (OVERLAPS) 12/280 variables, 6/87 constraints. Problems are: Problem set: 0 solved, 234 unsolved
At refinement iteration 5 (INCLUDED_ONLY) 0/280 variables, 0/87 constraints. Problems are: Problem set: 0 solved, 234 unsolved
At refinement iteration 6 (OVERLAPS) 1/281 variables, 1/88 constraints. Problems are: Problem set: 0 solved, 234 unsolved
At refinement iteration 7 (INCLUDED_ONLY) 0/281 variables, 0/88 constraints. Problems are: Problem set: 0 solved, 234 unsolved
At refinement iteration 8 (OVERLAPS) 0/281 variables, 0/88 constraints. Problems are: Problem set: 0 solved, 234 unsolved
No progress, stopping.
After SMT solving in domain Real declared 281/281 variables, and 88 constraints, problems are : Problem set: 0 solved, 234 unsolved in 10997 ms.
Refiners :[State Equation: 34/34 constraints, ReadFeed: 54/54 constraints, PredecessorRefiner: 234/234 constraints, Known Traps: 0/0 constraints]
Escalating to Integer solving :Problem set: 0 solved, 234 unsolved
At refinement iteration 0 (INCLUDED_ONLY) 0/28 variables, 0/0 constraints. Problems are: Problem set: 0 solved, 234 unsolved
At refinement iteration 1 (OVERLAPS) 240/268 variables, 28/28 constraints. Problems are: Problem set: 0 solved, 234 unsolved
At refinement iteration 2 (INCLUDED_ONLY) 0/268 variables, 53/81 constraints. Problems are: Problem set: 0 solved, 234 unsolved
At refinement iteration 3 (INCLUDED_ONLY) 0/268 variables, 234/315 constraints. Problems are: Problem set: 0 solved, 234 unsolved
At refinement iteration 4 (INCLUDED_ONLY) 0/268 variables, 0/315 constraints. Problems are: Problem set: 0 solved, 234 unsolved
At refinement iteration 5 (OVERLAPS) 12/280 variables, 6/321 constraints. Problems are: Problem set: 0 solved, 234 unsolved
Solver is answering 'unknown', stopping.
After SMT solving in domain Int declared 280/281 variables, and 321 constraints, problems are : Problem set: 0 solved, 234 unsolved in 20031 ms.
Refiners :[State Equation: 34/34 constraints, ReadFeed: 53/54 constraints, PredecessorRefiner: 234/234 constraints, Known Traps: 0/0 constraints]
After SMT, in 31302ms problems are : Problem set: 0 solved, 234 unsolved
Search for dead transitions found 0 dead transitions in 31323ms
[2024-05-21 21:00:45] [INFO ] Flow matrix only has 247 transitions (discarded 3 similar events)
[2024-05-21 21:00:45] [INFO ] Invariant cache hit.
[2024-05-21 21:00:45] [INFO ] Implicit Places using invariants in 65 ms returned []
[2024-05-21 21:00:45] [INFO ] Flow matrix only has 247 transitions (discarded 3 similar events)
[2024-05-21 21:00:45] [INFO ] Invariant cache hit.
[2024-05-21 21:00:45] [INFO ] State equation strengthened by 54 read => feed constraints.
[2024-05-21 21:00:45] [INFO ] Implicit Places using invariants and state equation in 273 ms returned []
Implicit Place search using SMT with State Equation took 345 ms to find 0 implicit places.
Running 234 sub problems to find dead transitions.
[2024-05-21 21:00:45] [INFO ] Flow matrix only has 247 transitions (discarded 3 similar events)
[2024-05-21 21:00:45] [INFO ] Invariant cache hit.
[2024-05-21 21:00:45] [INFO ] State equation strengthened by 54 read => feed constraints.
At refinement iteration 0 (INCLUDED_ONLY) 0/28 variables, 0/0 constraints. Problems are: Problem set: 0 solved, 234 unsolved
At refinement iteration 1 (OVERLAPS) 240/268 variables, 28/28 constraints. Problems are: Problem set: 0 solved, 234 unsolved
At refinement iteration 2 (INCLUDED_ONLY) 0/268 variables, 53/81 constraints. Problems are: Problem set: 0 solved, 234 unsolved
At refinement iteration 3 (INCLUDED_ONLY) 0/268 variables, 0/81 constraints. Problems are: Problem set: 0 solved, 234 unsolved
At refinement iteration 4 (OVERLAPS) 12/280 variables, 6/87 constraints. Problems are: Problem set: 0 solved, 234 unsolved
At refinement iteration 5 (INCLUDED_ONLY) 0/280 variables, 0/87 constraints. Problems are: Problem set: 0 solved, 234 unsolved
At refinement iteration 6 (OVERLAPS) 1/281 variables, 1/88 constraints. Problems are: Problem set: 0 solved, 234 unsolved
At refinement iteration 7 (INCLUDED_ONLY) 0/281 variables, 0/88 constraints. Problems are: Problem set: 0 solved, 234 unsolved
At refinement iteration 8 (OVERLAPS) 0/281 variables, 0/88 constraints. Problems are: Problem set: 0 solved, 234 unsolved
No progress, stopping.
After SMT solving in domain Real declared 281/281 variables, and 88 constraints, problems are : Problem set: 0 solved, 234 unsolved in 10028 ms.
Refiners :[State Equation: 34/34 constraints, ReadFeed: 54/54 constraints, PredecessorRefiner: 234/234 constraints, Known Traps: 0/0 constraints]
Escalating to Integer solving :Problem set: 0 solved, 234 unsolved
At refinement iteration 0 (INCLUDED_ONLY) 0/28 variables, 0/0 constraints. Problems are: Problem set: 0 solved, 234 unsolved
At refinement iteration 1 (OVERLAPS) 240/268 variables, 28/28 constraints. Problems are: Problem set: 0 solved, 234 unsolved
At refinement iteration 2 (INCLUDED_ONLY) 0/268 variables, 53/81 constraints. Problems are: Problem set: 0 solved, 234 unsolved
At refinement iteration 3 (INCLUDED_ONLY) 0/268 variables, 234/315 constraints. Problems are: Problem set: 0 solved, 234 unsolved
At refinement iteration 4 (INCLUDED_ONLY) 0/268 variables, 0/315 constraints. Problems are: Problem set: 0 solved, 234 unsolved
At refinement iteration 5 (OVERLAPS) 12/280 variables, 6/321 constraints. Problems are: Problem set: 0 solved, 234 unsolved
Solver is answering 'unknown', stopping.
After SMT solving in domain Int declared 280/281 variables, and 321 constraints, problems are : Problem set: 0 solved, 234 unsolved in 30022 ms.
Refiners :[State Equation: 34/34 constraints, ReadFeed: 53/54 constraints, PredecessorRefiner: 234/234 constraints, Known Traps: 0/0 constraints]
After SMT, in 40175ms problems are : Problem set: 0 solved, 234 unsolved
Search for dead transitions found 0 dead transitions in 40180ms
Finished structural reductions in LIVENESS mode , in 1 iterations and 71910 ms. Remains : 34/34 places, 250/250 transitions.
Discarding 6 transitions out of 250. Remains 244
Initial state reduction rules removed 10 formulas.
[2024-05-21 21:01:26] [INFO ] Flatten gal took : 78 ms
[2024-05-21 21:01:26] [INFO ] Flatten gal took : 43 ms
[2024-05-21 21:01:26] [INFO ] Time to serialize gal into /tmp/ReachabilityCardinality5729109750637386044.gal : 20 ms
[2024-05-21 21:01:26] [INFO ] Time to serialize properties into /tmp/ReachabilityCardinality4236176080789113774.prop : 3 ms
Invoking ITS tools like this :cd /home/mcc/execution;'/home/mcc/BenchKit/itstools/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.202405141337/bin/its-reach-linux64' '--gc-threshold' '2000000' '--quiet' '-i' '/tmp/ReachabilityCardinality5729109750637386044.gal' '-t' 'CGAL' '-reachable-file' '/tmp/ReachabilityCardinality4236176080789113774.prop' '--nowitness' '--gen-order' 'FOLLOW'
its-reach command run as :
/home/mcc/BenchKit/itstools/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.202405141337/bin/its-reach-linux64 --gc-threshold 2000000 --quiet ...328
Loading property file /tmp/ReachabilityCardinality4236176080789113774.prop.
Reachability property qltransition_32 is true.
Reachability property qltransition_31 is true.
Reachability property qltransition_30 is true.
Reachability property qltransition_29 is true.
Reachability property qltransition_26 is true.
Reachability property qltransition_25 is true.
Reachability property qltransition_23 is true.
Reachability property qltransition_22 is true.
Reachability property qltransition_19 is true.
Reachability property qltransition_18 is true.
SDD proceeding with computation,224 properties remain. new max is 2
SDD size :1 after 10
Reachability property qltransition_41 is true.
Reachability property qltransition_40 is true.
Reachability property qltransition_39 is true.
Reachability property qltransition_38 is true.
Reachability property qltransition_36 is true.
Reachability property qltransition_35 is true.
Reachability property qltransition_34 is true.
Reachability property qltransition_27 is true.
Reachability property qltransition_20 is true.
Reachability property qltransition_15 is true.
SDD proceeding with computation,214 properties remain. new max is 2
SDD size :10 after 39
Reachability property qltransition_95 is true.
Reachability property qltransition_94 is true.
Reachability property qltransition_93 is true.
Reachability property qltransition_92 is true.
Reachability property qltransition_91 is true.
Reachability property qltransition_89 is true.
Reachability property qltransition_88 is true.
Reachability property qltransition_87 is true.
Reachability property qltransition_86 is true.
Reachability property qltransition_52 is true.
Reachability property qltransition_51 is true.
Reachability property qltransition_50 is true.
Reachability property qltransition_49 is true.
Reachability property qltransition_48 is true.
Reachability property qltransition_47 is true.
Reachability property qltransition_45 is true.
Reachability property qltransition_44 is true.
Reachability property qltransition_43 is true.
SDD proceeding with computation,196 properties remain. new max is 2
SDD size :39 after 142
Reachability property qltransition_90 is true.
Reachability property qltransition_64 is true.
Reachability property qltransition_63 is true.
Reachability property qltransition_62 is true.
Reachability property qltransition_61 is true.
Reachability property qltransition_60 is true.
Reachability property qltransition_59 is true.
Reachability property qltransition_58 is true.
Reachability property qltransition_57 is true.
Reachability property qltransition_56 is true.
Reachability property qltransition_55 is true.
Reachability property qltransition_54 is true.
Reachability property qltransition_53 is true.
Reachability property qltransition_46 is true.
Reachability property qltransition_37 is true.
Reachability property qltransition_28 is true.
Reachability property qltransition_21 is true.
SDD proceeding with computation,179 properties remain. new max is 2
SDD size :142 after 391
Reachability property qltransition_75 is true.
Reachability property qltransition_74 is true.
Reachability property qltransition_72 is true.
Reachability property qltransition_71 is true.
Reachability property qltransition_70 is true.
Reachability property qltransition_69 is true.
Reachability property qltransition_68 is true.
Reachability property qltransition_67 is true.
Reachability property qltransition_66 is true.
Reachability property qltransition_65 is true.
SDD proceeding with computation,169 properties remain. new max is 2
SDD size :391 after 800
SDD proceeding with computation,169 properties remain. new max is 4
SDD size :800 after 819
SDD proceeding with computation,169 properties remain. new max is 8
SDD size :819 after 836
SDD proceeding with computation,169 properties remain. new max is 16
SDD size :836 after 841
Reachability property qltransition_84 is true.
Reachability property qltransition_83 is true.
Reachability property qltransition_80 is true.
Reachability property qltransition_79 is true.
Reachability property qltransition_78 is true.
Reachability property qltransition_77 is true.
Reachability property qltransition_76 is true.
SDD proceeding with computation,162 properties remain. new max is 16
SDD size :841 after 1357
Reachability property qltransition_138 is true.
Reachability property qltransition_137 is true.
Reachability property qltransition_136 is true.
Reachability property qltransition_135 is true.
Reachability property qltransition_132 is true.
Reachability property qltransition_131 is true.
Reachability property qltransition_130 is true.
Reachability property qltransition_129 is true.
Reachability property qltransition_128 is true.
Reachability property qltransition_105 is true.
Reachability property qltransition_104 is true.
Reachability property qltransition_103 is true.
Reachability property qltransition_102 is true.
Reachability property qltransition_101 is true.
Reachability property qltransition_100 is true.
Reachability property qltransition_99 is true.
Reachability property qltransition_98 is true.
Reachability property qltransition_97 is true.
Reachability property qltransition_96 is true.
SDD proceeding with computation,143 properties remain. new max is 16
SDD size :1357 after 5055
SDD proceeding with computation,143 properties remain. new max is 32
SDD size :5055 after 5737
Reachability property qltransition_148 is true.
Reachability property qltransition_147 is true.
Reachability property qltransition_146 is true.
Reachability property qltransition_145 is true.
Reachability property qltransition_142 is true.
Reachability property qltransition_141 is true.
Reachability property qltransition_140 is true.
Reachability property qltransition_139 is true.
SDD proceeding with computation,135 properties remain. new max is 32
SDD size :5737 after 11566
Reachability property qltransition_118 is true.
Reachability property qltransition_115 is true.
Reachability property qltransition_114 is true.
Reachability property qltransition_113 is true.
Reachability property qltransition_112 is true.
Reachability property qltransition_111 is true.
Reachability property qltransition_110 is true.
Reachability property qltransition_109 is true.
Reachability property qltransition_108 is true.
SDD proceeding with computation,126 properties remain. new max is 32
SDD size :11566 after 17183
SDD proceeding with computation,126 properties remain. new max is 64
SDD size :17183 after 18498
Reachability property qltransition_175 is true.
Reachability property qltransition_174 is true.
Reachability property qltransition_173 is true.
Reachability property qltransition_172 is true.
Reachability property qltransition_170 is true.
Reachability property qltransition_169 is true.
Reachability property qltransition_168 is true.
Reachability property qltransition_167 is true.
Reachability property qltransition_166 is true.
Reachability property qltransition_165 is true.
Reachability property qltransition_157 is true.
Reachability property qltransition_156 is true.
Reachability property qltransition_155 is true.
Reachability property qltransition_154 is true.
Reachability property qltransition_152 is true.
Reachability property qltransition_151 is true.
Reachability property qltransition_150 is true.
Reachability property qltransition_149 is true.
Reachability property qltransition_143 is true.
Reachability property qltransition_133 is true.
Reachability property qltransition_81 is true.
Reachability property qltransition_73 is true.
SDD proceeding with computation,104 properties remain. new max is 64
SDD size :18498 after 153252
Reachability property qltransition_247 is true.
Reachability property qltransition_246 is true.
Reachability property qltransition_186 is true.
Reachability property qltransition_184 is true.
Reachability property qltransition_183 is true.
Reachability property qltransition_182 is true.
Reachability property qltransition_181 is true.
Reachability property qltransition_180 is true.
Reachability property qltransition_179 is true.
Reachability property qltransition_178 is true.
Reachability property qltransition_177 is true.
Reachability property qltransition_176 is true.
Reachability property qltransition_171 is true.
Reachability property qltransition_164 is true.
Reachability property qltransition_163 is true.
Reachability property qltransition_162 is true.
Reachability property qltransition_161 is true.
Reachability property qltransition_160 is true.
Reachability property qltransition_159 is true.
Reachability property qltransition_158 is true.
Reachability property qltransition_153 is true.
Reachability property qltransition_144 is true.
Reachability property qltransition_134 is true.
Reachability property qltransition_127 is true.
Reachability property qltransition_126 is true.
Reachability property qltransition_123 is true.
Reachability property qltransition_122 is true.
Reachability property qltransition_121 is true.
Reachability property qltransition_120 is true.
Reachability property qltransition_119 is true.
Reachability property qltransition_82 is true.
SDD proceeding with computation,73 properties remain. new max is 64
SDD size :153252 after 1.70432e+06
SDD proceeding with computation,73 properties remain. new max is 128
SDD size :1.70432e+06 after 1.76467e+06
SDD proceeding with computation,73 properties remain. new max is 256
SDD size :1.76467e+06 after 1.83665e+06
RANDOM walk for 40000 steps (2551 resets) in 2790 ms. (14 steps per ms) remains 5/234 properties
Reachability property qltransition_207 is true.
Reachability property qltransition_206 is true.
Reachability property qltransition_205 is true.
Reachability property qltransition_204 is true.
Reachability property qltransition_201 is true.
Reachability property qltransition_200 is true.
Reachability property qltransition_199 is true.
Reachability property qltransition_198 is true.
Reachability property qltransition_197 is true.
Reachability property qltransition_196 is true.
Reachability property qltransition_195 is true.
Reachability property qltransition_194 is true.
Reachability property qltransition_191 is true.
Reachability property qltransition_190 is true.
Reachability property qltransition_189 is true.
Reachability property qltransition_188 is true.
Reachability property qltransition_187 is true.
SDD proceeding with computation,56 properties remain. new max is 256
SDD size :1.83665e+06 after 5.69371e+06
BEST_FIRST walk for 40004 steps (283 resets) in 145 ms. (274 steps per ms) remains 5/5 properties
SDD proceeding with computation,56 properties remain. new max is 512
SDD size :5.69371e+06 after 7.74348e+06
BEST_FIRST walk for 40004 steps (277 resets) in 155 ms. (256 steps per ms) remains 5/5 properties
Reachability property qltransition_248 is true.
Reachability property qltransition_238 is true.
Reachability property qltransition_237 is true.
Reachability property qltransition_236 is true.
Reachability property qltransition_234 is true.
Reachability property qltransition_233 is true.
Reachability property qltransition_232 is true.
Reachability property qltransition_231 is true.
Reachability property qltransition_230 is true.
Reachability property qltransition_218 is true.
Reachability property qltransition_217 is true.
Reachability property qltransition_216 is true.
Reachability property qltransition_215 is true.
Reachability property qltransition_213 is true.
Reachability property qltransition_212 is true.
Reachability property qltransition_211 is true.
Reachability property qltransition_210 is true.
Reachability property qltransition_209 is true.
Reachability property qltransition_208 is true.
Reachability property qltransition_202 is true.
Reachability property qltransition_192 is true.
Reachability property qltransition_124 is true.
Reachability property qltransition_116 is true.
Reachability property qltransition_106 is true.
SDD proceeding with computation,32 properties remain. new max is 512
SDD size :7.74348e+06 after 4.99818e+07
BEST_FIRST walk for 40004 steps (275 resets) in 156 ms. (254 steps per ms) remains 5/5 properties
BEST_FIRST walk for 40004 steps (260 resets) in 108 ms. (367 steps per ms) remains 5/5 properties
BEST_FIRST walk for 40003 steps (272 resets) in 80 ms. (493 steps per ms) remains 5/5 properties
[2024-05-21 21:01:26] [INFO ] Flow matrix only has 247 transitions (discarded 3 similar events)
[2024-05-21 21:01:26] [INFO ] Invariant cache hit.
[2024-05-21 21:01:26] [INFO ] State equation strengthened by 54 read => feed constraints.
Reachability property qltransition_245 is true.
Reachability property qltransition_244 is true.
Reachability property qltransition_243 is true.
Reachability property qltransition_242 is true.
Reachability property qltransition_241 is true.
Reachability property qltransition_240 is true.
Reachability property qltransition_239 is true.
Reachability property qltransition_235 is true.
Reachability property qltransition_227 is true.
Reachability property qltransition_226 is true.
Reachability property qltransition_225 is true.
Reachability property qltransition_224 is true.
Reachability property qltransition_223 is true.
Reachability property qltransition_222 is true.
Reachability property qltransition_221 is true.
Reachability property qltransition_220 is true.
Reachability property qltransition_219 is true.
Reachability property qltransition_214 is true.
Reachability property qltransition_203 is true.
Reachability property qltransition_193 is true.
Reachability property qltransition_185 is true.
Reachability property qltransition_125 is true.
Reachability property qltransition_117 is true.
Reachability property qltransition_107 is true.
SDD proceeding with computation,8 properties remain. new max is 512
SDD size :4.99818e+07 after 2.87187e+08
Reachability property qltransition_228 is true.
SDD proceeding with computation,7 properties remain. new max is 512
SDD size :2.87187e+08 after 3.06417e+08
At refinement iteration 0 (INCLUDED_ONLY) 0/6 variables, 0/0 constraints. Problems are: Problem set: 0 solved, 5 unsolved
At refinement iteration 1 (OVERLAPS) 75/81 variables, 6/6 constraints. Problems are: Problem set: 0 solved, 5 unsolved
Reachability property qltransition_229 is true.
At refinement iteration 2 (INCLUDED_ONLY) 0/81 variables, 11/17 constraints. Problems are: Problem set: 0 solved, 5 unsolved
SDD proceeding with computation,6 properties remain. new max is 512
SDD size :3.06417e+08 after 3.58359e+08
At refinement iteration 3 (INCLUDED_ONLY) 0/81 variables, 0/17 constraints. Problems are: Problem set: 0 solved, 5 unsolved
At refinement iteration 4 (OVERLAPS) 109/190 variables, 9/26 constraints. Problems are: Problem set: 0 solved, 5 unsolved
At refinement iteration 5 (INCLUDED_ONLY) 0/190 variables, 12/38 constraints. Problems are: Problem set: 0 solved, 5 unsolved
All remaining problems are real, not stopping.
At refinement iteration 6 (INCLUDED_ONLY) 0/190 variables, 0/38 constraints. Problems are: Problem set: 0 solved, 5 unsolved
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
petri\_inst\_inst,4.32885e+08,0.385522,17076,2,1987,194,52830,12,0,426,56174,0
Total reachable state count : 432884827
Verifying 234 reachability properties.
Reachability property qltransition_15 is true.
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
qltransition\_15,1,0.386465,17076,2,35,194,52830,13,0,430,56174,0
Reachability property qltransition_17 does not hold.
FORMULA QuasiLiveness FALSE TECHNIQUES RANDOM_WALK DECISION_DIAGRAMS COLLATERAL_PROCESSING TOPOLOGICAL INITIAL_STATE
At refinement iteration 7 (OVERLAPS) 82/272 variables, 15/53 constraints. Problems are: Problem set: 0 solved, 5 unsolved
At refinement iteration 8 (INCLUDED_ONLY) 0/272 variables, 30/83 constraints. Problems are: Problem set: 0 solved, 5 unsolved
ITS tools runner thread asked to quit. Dying gracefully.
At refinement iteration 9 (INCLUDED_ONLY) 0/272 variables, 0/83 constraints. Problems are: Problem set: 0 solved, 5 unsolved
At refinement iteration 10 (OVERLAPS) 8/280 variables, 4/87 constraints. Problems are: Problem set: 0 solved, 5 unsolved
At refinement iteration 11 (INCLUDED_ONLY) 0/280 variables, 0/87 constraints. Problems are: Problem set: 0 solved, 5 unsolved
At refinement iteration 12 (OVERLAPS) 1/281 variables, 1/88 constraints. Problems are: Problem set: 0 solved, 5 unsolved
At refinement iteration 13 (INCLUDED_ONLY) 0/281 variables, 0/88 constraints. Problems are: Problem set: 0 solved, 5 unsolved
At refinement iteration 14 (OVERLAPS) 0/281 variables, 0/88 constraints. Problems are: Problem set: 0 solved, 5 unsolved
No progress, stopping.
After SMT solving in domain Real declared 281/281 variables, and 88 constraints, problems are : Problem set: 0 solved, 5 unsolved in 226 ms.
Refiners :[State Equation: 34/34 constraints, ReadFeed: 54/54 constraints, PredecessorRefiner: 5/5 constraints, Known Traps: 0/0 constraints]
Escalating to Integer solving :Problem set: 0 solved, 5 unsolved
At refinement iteration 0 (INCLUDED_ONLY) 0/6 variables, 0/0 constraints. Problems are: Problem set: 0 solved, 5 unsolved
At refinement iteration 1 (OVERLAPS) 75/81 variables, 6/6 constraints. Problems are: Problem set: 0 solved, 5 unsolved
At refinement iteration 2 (INCLUDED_ONLY) 0/81 variables, 11/17 constraints. Problems are: Problem set: 0 solved, 5 unsolved
At refinement iteration 3 (INCLUDED_ONLY) 0/81 variables, 0/17 constraints. Problems are: Problem set: 0 solved, 5 unsolved
At refinement iteration 4 (OVERLAPS) 109/190 variables, 9/26 constraints. Problems are: Problem set: 0 solved, 5 unsolved
At refinement iteration 5 (INCLUDED_ONLY) 0/190 variables, 12/38 constraints. Problems are: Problem set: 0 solved, 5 unsolved
At refinement iteration 6 (INCLUDED_ONLY) 0/190 variables, 5/43 constraints. Problems are: Problem set: 0 solved, 5 unsolved
At refinement iteration 7 (INCLUDED_ONLY) 0/190 variables, 0/43 constraints. Problems are: Problem set: 0 solved, 5 unsolved
At refinement iteration 8 (OVERLAPS) 82/272 variables, 15/58 constraints. Problems are: Problem set: 0 solved, 5 unsolved
At refinement iteration 9 (INCLUDED_ONLY) 0/272 variables, 30/88 constraints. Problems are: Problem set: 0 solved, 5 unsolved
At refinement iteration 10 (INCLUDED_ONLY) 0/272 variables, 0/88 constraints. Problems are: Problem set: 0 solved, 5 unsolved
Solver is answering 'unknown', stopping.
After SMT solving in domain Int declared 280/281 variables, and 92 constraints, problems are : Problem set: 0 solved, 5 unsolved in 5007 ms.
Refiners :[State Equation: 34/34 constraints, ReadFeed: 53/54 constraints, PredecessorRefiner: 5/5 constraints, Known Traps: 0/0 constraints]
After SMT, in 5248ms problems are : Problem set: 0 solved, 5 unsolved
Skipping Parikh replay, no witness traces provided.
Support contains 6 out of 34 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 34/34 places, 250/250 transitions.
Graph (complete) has 240 edges and 34 vertex of which 30 are kept as prefixes of interest. Removing 4 places using SCC suffix rule.1 ms
Discarding 4 places :
Also discarding 4 output transitions
Drop transitions (Output transitions of discarded places.) removed 4 transitions
Drop transitions (Empty/Sink Transition effects.) removed 30 transitions
Reduce isomorphic transitions removed 30 transitions.
Iterating post reduction 0 with 30 rules applied. Total rules applied 31 place count 30 transition count 216
Reduce places removed 5 places and 5 transitions.
Iterating global reduction 1 with 5 rules applied. Total rules applied 36 place count 25 transition count 211
Applied a total of 36 rules in 27 ms. Remains 25 /34 variables (removed 9) and now considering 211/250 (removed 39) transitions.
Running 206 sub problems to find dead transitions.
// Phase 1: matrix 211 rows 25 cols
[2024-05-21 21:01:31] [INFO ] Computed 0 invariants in 6 ms
[2024-05-21 21:01:31] [INFO ] State equation strengthened by 11 read => feed constraints.
At refinement iteration 0 (INCLUDED_ONLY) 0/24 variables, 0/0 constraints. Problems are: Problem set: 0 solved, 206 unsolved
At refinement iteration 1 (OVERLAPS) 211/235 variables, 24/24 constraints. Problems are: Problem set: 0 solved, 206 unsolved
At refinement iteration 2 (INCLUDED_ONLY) 0/235 variables, 11/35 constraints. Problems are: Problem set: 0 solved, 206 unsolved
At refinement iteration 3 (INCLUDED_ONLY) 0/235 variables, 0/35 constraints. Problems are: Problem set: 0 solved, 206 unsolved
At refinement iteration 4 (OVERLAPS) 1/236 variables, 1/36 constraints. Problems are: Problem set: 0 solved, 206 unsolved
At refinement iteration 5 (INCLUDED_ONLY) 0/236 variables, 0/36 constraints. Problems are: Problem set: 0 solved, 206 unsolved
At refinement iteration 6 (OVERLAPS) 0/236 variables, 0/36 constraints. Problems are: Problem set: 0 solved, 206 unsolved
No progress, stopping.
After SMT solving in domain Real declared 236/236 variables, and 36 constraints, problems are : Problem set: 0 solved, 206 unsolved in 3566 ms.
Refiners :[State Equation: 25/25 constraints, ReadFeed: 11/11 constraints, PredecessorRefiner: 206/206 constraints, Known Traps: 0/0 constraints]
Escalating to Integer solving :Problem set: 0 solved, 206 unsolved
At refinement iteration 0 (INCLUDED_ONLY) 0/24 variables, 0/0 constraints. Problems are: Problem set: 0 solved, 206 unsolved
At refinement iteration 1 (OVERLAPS) 211/235 variables, 24/24 constraints. Problems are: Problem set: 0 solved, 206 unsolved
At refinement iteration 2 (INCLUDED_ONLY) 0/235 variables, 11/35 constraints. Problems are: Problem set: 0 solved, 206 unsolved
At refinement iteration 3 (INCLUDED_ONLY) 0/235 variables, 206/241 constraints. Problems are: Problem set: 0 solved, 206 unsolved
At refinement iteration 4 (INCLUDED_ONLY) 0/235 variables, 0/241 constraints. Problems are: Problem set: 0 solved, 206 unsolved
At refinement iteration 5 (OVERLAPS) 1/236 variables, 1/242 constraints. Problems are: Problem set: 0 solved, 206 unsolved
Solver is answering 'unknown', stopping.
After SMT solving in domain Int declared 236/236 variables, and 242 constraints, problems are : Problem set: 0 solved, 206 unsolved in 20014 ms.
Refiners :[State Equation: 25/25 constraints, ReadFeed: 11/11 constraints, PredecessorRefiner: 206/206 constraints, Known Traps: 0/0 constraints]
After SMT, in 23694ms problems are : Problem set: 0 solved, 206 unsolved
Search for dead transitions found 0 dead transitions in 23696ms
Finished structural reductions in REACHABILITY mode , in 1 iterations and 23723 ms. Remains : 25/34 places, 211/250 transitions.
Total runtime 102141 ms.
BK_STOP 1716325315660
--------------------
content from stderr:
+ export BINDIR=/home/mcc/BenchKit/bin//../itstools/bin//../
+ BINDIR=/home/mcc/BenchKit/bin//../itstools/bin//../
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ [[ QuasiLiveness = StateSpace ]]
+ /home/mcc/BenchKit/bin//../itstools/bin//..//runeclipse.sh /home/mcc/execution QuasiLiveness -its -ltsmin -greatspnpath /home/mcc/BenchKit/bin//../itstools/bin//..//greatspn/ -order META -manyOrder -smt -timeout 1800
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../itstools/bin//..//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202405141337.jar
+ VERSION=202405141337
+ echo 'Running Version 202405141337'
+ /home/mcc/BenchKit/bin//../itstools/bin//..//itstools/its-tools -pnfolder /home/mcc/execution -examination QuasiLiveness -its -ltsmin -greatspnpath /home/mcc/BenchKit/bin//../itstools/bin//..//greatspn/ -order META -manyOrder -smt -timeout 1800
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DNAwalker-PT-07track28RR"
export BK_EXAMINATION="QuasiLiveness"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="1800"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool itstools"
echo " Input is DNAwalker-PT-07track28RR, examination is QuasiLiveness"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r123-smll-171624284100262"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DNAwalker-PT-07track28RR.tgz
mv DNAwalker-PT-07track28RR execution
cd execution
if [ "QuasiLiveness" = "ReachabilityDeadlock" ] || [ "QuasiLiveness" = "UpperBounds" ] || [ "QuasiLiveness" = "QuasiLiveness" ] || [ "QuasiLiveness" = "StableMarking" ] || [ "QuasiLiveness" = "Liveness" ] || [ "QuasiLiveness" = "OneSafe" ] || [ "QuasiLiveness" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "QuasiLiveness" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "QuasiLiveness" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "QuasiLiveness.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property QuasiLiveness.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "QuasiLiveness.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "QuasiLiveness" = "ReachabilityDeadlock" ] || [ "QuasiLiveness" = "QuasiLiveness" ] || [ "QuasiLiveness" = "StableMarking" ] || [ "QuasiLiveness" = "Liveness" ] || [ "QuasiLiveness" = "OneSafe" ] ; then
echo "FORMULA_NAME QuasiLiveness"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;