fond
Model Checking Contest 2024
14th edition, Geneva, Switzerland, June 25, 2024
Execution of r115-smll-171624276900356
Last Updated
July 7, 2024

About the Execution of LoLA for DLCshifumi-PT-6a

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
16209.443 570120.00 799792.00 2148.70 ?????????F?????T normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r115-smll-171624276900356.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is DLCshifumi-PT-6a, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r115-smll-171624276900356
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 7.3M
-rw-r--r-- 1 mcc users 6.9K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 74K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.6K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 47K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.1K Apr 22 14:38 LTLCardinality.txt
-rw-r--r-- 1 mcc users 29K Apr 22 14:38 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Apr 22 14:38 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Apr 22 14:38 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Apr 14 13:31 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 118K Apr 14 13:31 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.9K Apr 14 01:33 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 54K Apr 14 01:33 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 22 14:38 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Apr 22 14:38 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 3 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 6.9M May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCshifumi-PT-6a-LTLFireability-00
FORMULA_NAME DLCshifumi-PT-6a-LTLFireability-01
FORMULA_NAME DLCshifumi-PT-6a-LTLFireability-02
FORMULA_NAME DLCshifumi-PT-6a-LTLFireability-03
FORMULA_NAME DLCshifumi-PT-6a-LTLFireability-04
FORMULA_NAME DLCshifumi-PT-6a-LTLFireability-05
FORMULA_NAME DLCshifumi-PT-6a-LTLFireability-06
FORMULA_NAME DLCshifumi-PT-6a-LTLFireability-07
FORMULA_NAME DLCshifumi-PT-6a-LTLFireability-08
FORMULA_NAME DLCshifumi-PT-6a-LTLFireability-09
FORMULA_NAME DLCshifumi-PT-6a-LTLFireability-10
FORMULA_NAME DLCshifumi-PT-6a-LTLFireability-11
FORMULA_NAME DLCshifumi-PT-6a-LTLFireability-12
FORMULA_NAME DLCshifumi-PT-6a-LTLFireability-13
FORMULA_NAME DLCshifumi-PT-6a-LTLFireability-14
FORMULA_NAME DLCshifumi-PT-6a-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1717148198290

FORMULA DLCshifumi-PT-6a-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCshifumi-PT-6a-LTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1717148768410

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains place/transition net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading formula.
[lola][I] Using XML format (--xmlformula)
[lola][I] reading XML formula
[lola][I] reading formula from LTLFireability.xml
[lola][I] Rule S: 0 transitions removed,0 places removed
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCshifumi-PT-6a-LTLFireability-00: CONJ 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-04: CONJ 0 0 0 0 0 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-13: CONJ 0 0 0 0 0 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-15: F 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 6 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I] NOTDEADLOCKFREE
[lola][I] NOTDEADLOCKFREE
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCshifumi-PT-6a-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-02: CONJ 0 0 0 0 2 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-04: CONJ 0 0 0 0 2 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-13: CONJ 0 0 0 0 0 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-15: F 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 11 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I] NOTDEADLOCKFREE
[lola][I] LAUNCH task # 72 (type SKEL/SRCH) for 49 DLCshifumi-PT-6a-LTLFireability-11
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 72 (type SKEL/SRCH) for DLCshifumi-PT-6a-LTLFireability-11
[lola][I] result : false
[lola][I] markings : 17
[lola][I] fired transitions : 47
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] NOTDEADLOCKFREE
[lola][I] LAUNCH task # 73 (type SKEL/SRCH) for 62 DLCshifumi-PT-6a-LTLFireability-14
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 73 (type SKEL/SRCH) for DLCshifumi-PT-6a-LTLFireability-14
[lola][I] result : false
[lola][I] markings : 5
[lola][I] fired transitions : 5
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCshifumi-PT-6a-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-02: CONJ 0 0 0 0 2 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-04: CONJ 0 0 0 0 3 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-13: CONJ 0 0 0 0 2 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-14: CONJ 0 0 0 0 2 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-15: F 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 16 secs. Pages in use: 1
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCshifumi-PT-6a-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-02: CONJ 0 0 0 0 2 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-04: CONJ 0 0 0 0 3 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-13: CONJ 0 0 0 0 2 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-14: CONJ 0 0 0 0 2 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-15: F 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 21 secs. Pages in use: 1
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCshifumi-PT-6a-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-02: CONJ 0 0 0 0 2 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-04: CONJ 0 0 0 0 3 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-13: CONJ 0 0 0 0 2 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-14: CONJ 0 0 0 0 2 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-15: F 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 26 secs. Pages in use: 1
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCshifumi-PT-6a-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-02: CONJ 0 0 0 0 2 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-04: CONJ 0 0 0 0 3 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-13: CONJ 0 0 0 0 2 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-14: CONJ 0 0 0 0 2 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-15: F 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 31 secs. Pages in use: 1
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCshifumi-PT-6a-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-02: CONJ 0 0 0 0 2 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
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[lola][.] DLCshifumi-PT-6a-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-13: CONJ 0 0 0 0 2 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-14: CONJ 0 0 0 0 2 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-15: F 0 0 0 0 1 0 0 0
[lola][.]
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[lola][.] DLCshifumi-PT-6a-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-02: CONJ 0 0 0 0 2 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-04: CONJ 0 0 0 0 3 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-13: CONJ 0 0 0 0 2 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-14: CONJ 0 0 0 0 2 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-15: F 0 0 0 0 1 0 0 0
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[lola][I] LAUNCH task # 44 (type EXCL) for 43 DLCshifumi-PT-6a-LTLFireability-09
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[lola][I] FINISHED task # 44 (type EXCL) for DLCshifumi-PT-6a-LTLFireability-09
[lola][I] result : false
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[lola][I] LAUNCH task # 75 (type EXCL) for 69 DLCshifumi-PT-6a-LTLFireability-15
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[lola][I] LAUNCH task # 78 (type EQUN) for 69 DLCshifumi-PT-6a-LTLFireability-15
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[lola][.] DLCshifumi-PT-6a-LTLFireability-09: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCshifumi-PT-6a-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-02: CONJ 0 0 0 0 2 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-04: CONJ 0 0 0 0 3 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-13: CONJ 0 0 0 0 2 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-14: CONJ 0 0 0 0 2 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-15: F 0 0 2 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 75 EG EXCL 1/166 0/2000 DLCshifumi-PT-6a-LTLFireability-15 --
[lola][.] 78 EF STEQ 1/3500 0/5 DLCshifumi-PT-6a-LTLFireability-15 sara not yet started (preprocessing).
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[lola][I] FINISHED task # 75 (type EXCL) for DLCshifumi-PT-6a-LTLFireability-15
[lola][I] result : false
[lola][I] markings : 1
[lola][I] time used : 2
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 78 (type EQUN) for DLCshifumi-PT-6a-LTLFireability-15 (obsolete)
[lola][I] LAUNCH task # 80 (type EXCL) for 55 DLCshifumi-PT-6a-LTLFireability-13
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[lola][I] LAUNCH task # 83 (type EQUN) for 55 DLCshifumi-PT-6a-LTLFireability-13
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[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 80 (type EXCL) for DLCshifumi-PT-6a-LTLFireability-13
[lola][I] result : true
[lola][I] markings : 2
[lola][I] fired transitions : 2
[lola][I] time used : 3
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 83 (type EQUN) for DLCshifumi-PT-6a-LTLFireability-13 (obsolete)
[lola][I] LAUNCH task # 50 (type EXCL) for 49 DLCshifumi-PT-6a-LTLFireability-11
[lola][I] time limit : 194 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 50 (type EXCL) for DLCshifumi-PT-6a-LTLFireability-11
[lola][I] result : false
[lola][I] markings : 15
[lola][I] fired transitions : 2026
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCshifumi-PT-6a-LTLFireability-09: LTL false LTL model checker
[lola][.] DLCshifumi-PT-6a-LTLFireability-11: LTL false LTL model checker
[lola][.] DLCshifumi-PT-6a-LTLFireability-13: CONJ false state space / EG
[lola][.] DLCshifumi-PT-6a-LTLFireability-15: F true state space / EG
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCshifumi-PT-6a-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-02: CONJ 0 0 0 0 2 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-04: CONJ 0 0 0 0 3 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-14: CONJ 0 0 0 0 2 0 0 0
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[lola][I] LAUNCH task # 47 (type EXCL) for 46 DLCshifumi-PT-6a-LTLFireability-10
[lola][I] time limit : 205 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 47 (type EXCL) for DLCshifumi-PT-6a-LTLFireability-10
[lola][I] result : false
[lola][I] markings : 12
[lola][I] fired transitions : 1036
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 15 (type EXCL) for 10 DLCshifumi-PT-6a-LTLFireability-02
[lola][I] time limit : 218 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 15 (type EXCL) for DLCshifumi-PT-6a-LTLFireability-02
[lola][I] result : false
[lola][I] markings : 2
[lola][I] fired transitions : 2
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 27 (type EXCL) for 20 DLCshifumi-PT-6a-LTLFireability-04
[lola][I] time limit : 249 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 27 (type EXCL) for DLCshifumi-PT-6a-LTLFireability-04
[lola][I] result : false
[lola][I] markings : 2
[lola][I] fired transitions : 2
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] FINISHED task # 83 (type EQUN) for DLCshifumi-PT-6a-LTLFireability-13
[lola][I] result : true
[lola][I] FINISHED task # 78 (type EQUN) for DLCshifumi-PT-6a-LTLFireability-15
[lola][I] result : true
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCshifumi-PT-6a-LTLFireability-02: CONJ false LTL model checker
[lola][.] DLCshifumi-PT-6a-LTLFireability-04: CONJ false LTL model checker
[lola][.] DLCshifumi-PT-6a-LTLFireability-09: LTL false LTL model checker
[lola][.] DLCshifumi-PT-6a-LTLFireability-10: LTL false LTL model checker
[lola][.] DLCshifumi-PT-6a-LTLFireability-11: LTL false LTL model checker
[lola][.] DLCshifumi-PT-6a-LTLFireability-13: CONJ false state space / EG
[lola][.] DLCshifumi-PT-6a-LTLFireability-15: F true state space / EG
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCshifumi-PT-6a-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-14: CONJ 0 0 0 0 2 0 0 0
[lola][.]
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[lola][.] DLCshifumi-PT-6a-LTLFireability-02: CONJ false LTL model checker
[lola][.] DLCshifumi-PT-6a-LTLFireability-04: CONJ false LTL model checker
[lola][.] DLCshifumi-PT-6a-LTLFireability-09: LTL false LTL model checker
[lola][.] DLCshifumi-PT-6a-LTLFireability-10: LTL false LTL model checker
[lola][.] DLCshifumi-PT-6a-LTLFireability-11: LTL false LTL model checker
[lola][.] DLCshifumi-PT-6a-LTLFireability-13: CONJ false state space / EG
[lola][.] DLCshifumi-PT-6a-LTLFireability-15: F true state space / EG
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCshifumi-PT-6a-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-14: CONJ 0 0 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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[lola][.] DLCshifumi-PT-6a-LTLFireability-02: CONJ false LTL model checker
[lola][.] DLCshifumi-PT-6a-LTLFireability-04: CONJ false LTL model checker
[lola][.] DLCshifumi-PT-6a-LTLFireability-09: LTL false LTL model checker
[lola][.] DLCshifumi-PT-6a-LTLFireability-10: LTL false LTL model checker
[lola][.] DLCshifumi-PT-6a-LTLFireability-11: LTL false LTL model checker
[lola][.] DLCshifumi-PT-6a-LTLFireability-13: CONJ false state space / EG
[lola][.] DLCshifumi-PT-6a-LTLFireability-15: F true state space / EG
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCshifumi-PT-6a-LTLFireability-00: CONJ 0 0 0 0 2 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-14: CONJ 0 0 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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[lola][I] LAUNCH task # 3 (type EXCL) for 0 DLCshifumi-PT-6a-LTLFireability-00
[lola][I] time limit : 316 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 3 (type EXCL) for DLCshifumi-PT-6a-LTLFireability-00
[lola][I] result : false
[lola][I] markings : 3
[lola][I] fired transitions : 3
[lola][I] time used : 0
[lola][I] memory pages used : 1
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[lola][.] DLCshifumi-PT-6a-LTLFireability-00: CONJ false LTL model checker
[lola][.] DLCshifumi-PT-6a-LTLFireability-02: CONJ false LTL model checker
[lola][.] DLCshifumi-PT-6a-LTLFireability-04: CONJ false LTL model checker
[lola][.] DLCshifumi-PT-6a-LTLFireability-09: LTL false LTL model checker
[lola][.] DLCshifumi-PT-6a-LTLFireability-10: LTL false LTL model checker
[lola][.] DLCshifumi-PT-6a-LTLFireability-11: LTL false LTL model checker
[lola][.] DLCshifumi-PT-6a-LTLFireability-13: CONJ false state space / EG
[lola][.] DLCshifumi-PT-6a-LTLFireability-15: F true state space / EG
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCshifumi-PT-6a-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] DLCshifumi-PT-6a-LTLFireability-14: CONJ 0 0 0 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
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[lola][I] LAUNCH task # 53 (type EXCL) for 52 DLCshifumi-PT-6a-LTLFireability-12
[lola][I] time limit : 385 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 53 (type EXCL) for DLCshifumi-PT-6a-LTLFireability-12
[lola][I] result : false
[lola][I] markings : 4
[lola][I] fired transitions : 4
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 38 (type EXCL) for 37 DLCshifumi-PT-6a-LTLFireability-07
[lola][I] time limit : 434 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 38 (type EXCL) for DLCshifumi-PT-6a-LTLFireability-07
[lola][I] result : false
[lola][I] markings : 24
[lola][I] fired transitions : 73
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 32 (type EXCL) for 31 DLCshifumi-PT-6a-LTLFireability-05
[lola][I] time limit : 495 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 32 (type EXCL) for DLCshifumi-PT-6a-LTLFireability-05
[lola][I] result : false
[lola][I] markings : 2
[lola][I] fired transitions : 2
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 67 (type EXCL) for 62 DLCshifumi-PT-6a-LTLFireability-14
[lola][I] time limit : 578 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 67 (type EXCL) for DLCshifumi-PT-6a-LTLFireability-14
[lola][I] result : false
[lola][I] markings : 3
[lola][I] fired transitions : 3
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 8 (type EXCL) for 7 DLCshifumi-PT-6a-LTLFireability-01
[lola][I] time limit : 867 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 8 (type EXCL) for DLCshifumi-PT-6a-LTLFireability-01
[lola][I] result : true
[lola][I] markings : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 18 (type EXCL) for 17 DLCshifumi-PT-6a-LTLFireability-03
[lola][I] time limit : 1156 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 18 (type EXCL) for DLCshifumi-PT-6a-LTLFireability-03
[lola][I] result : false
[lola][I] markings : 24
[lola][I] fired transitions : 688
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 41 (type EXCL) for 40 DLCshifumi-PT-6a-LTLFireability-08
[lola][I] time limit : 1735 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 41 (type EXCL) for DLCshifumi-PT-6a-LTLFireability-08
[lola][I] result : true
[lola][I] markings : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 35 (type EXCL) for 34 DLCshifumi-PT-6a-LTLFireability-06
[lola][I] time limit : 3470 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCshifumi-PT-6a-LTLFireability-00: CONJ false LTL model checker
[lola][.] DLCshifumi-PT-6a-LTLFireability-01: LTL true LTL model checker
[lola][.] DLCshifumi-PT-6a-LTLFireability-02: CONJ false LTL model checker
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[lola][.] DLCshifumi-PT-6a-LTLFireability-08: LTL true LTL model checker
[lola][.] DLCshifumi-PT-6a-LTLFireability-09: LTL false LTL model checker
[lola][.] DLCshifumi-PT-6a-LTLFireability-10: LTL false LTL model checker
[lola][.] DLCshifumi-PT-6a-LTLFireability-11: LTL false LTL model checker
[lola][.] DLCshifumi-PT-6a-LTLFireability-12: LTL false LTL model checker
[lola][.] DLCshifumi-PT-6a-LTLFireability-13: CONJ false state space / EG
[lola][.] DLCshifumi-PT-6a-LTLFireability-14: CONJ false LTL model checker
[lola][.] DLCshifumi-PT-6a-LTLFireability-15: F true state space / EG
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCshifumi-PT-6a-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 425/3470 13/2000 DLCshifumi-PT-6a-LTLFireability-06 1201904 m, 80 m/sec, 77546466 t fired, .
[lola][.]
[lola][.] Time elapsed: 558 secs. Pages in use: 13
[lola][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 405 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCshifumi-PT-6a"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is DLCshifumi-PT-6a, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r115-smll-171624276900356"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCshifumi-PT-6a.tgz
mv DLCshifumi-PT-6a execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;