MCC'2024- Execution of r115-smll-171624276800324

About the Execution of LoLA for DLCshifumi-PT-4a

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
16207.735	426989.00	444706.00	1904.80	[undef]	Cannot compute

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r115-smll-171624276800324.qcow2',
Waiting for the VM to be ready (probing ssh)
........................................................
==================================
Generated by BenchKit 2-5568
Executing tool lola
Input is DLCshifumi-PT-4a, examination is LTLFireabi
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r115-smll-171624276800324
========================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 2.4M
-rw-r--r-- 1 mcc users 7.7K May 14 13:22 CTLCardinality.
-rw-r--r-- 1 mcc users 86K May 14 13:22 CTLCardinality.
-rw-r--r-- 1 mcc users 5.1K May 14 13:22 CTLFireability.
-rw-r--r-- 1 mcc users 45K May 14 13:22 CTLFireability.
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericProperti
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericProperti
-rw-r--r-- 1 mcc users 3.9K Apr 22 14:38 LTLCardinality.
-rw-r--r-- 1 mcc users 27K Apr 22 14:38 LTLCardinality.
-rw-r--r-- 1 mcc users 2.4K Apr 22 14:38 LTLFireability.
-rw-r--r-- 1 mcc users 18K Apr 22 14:38 LTLFireability.
-rw-r--r-- 1 mcc users 8.9K Apr 13 09:21 ReachabilityCar
-rw-r--r-- 1 mcc users 91K Apr 13 09:21 ReachabilityCar
-rw-r--r-- 1 mcc users 8.9K Apr 13 08:38 ReachabilityFir
-rw-r--r-- 1 mcc users 77K Apr 13 08:38 ReachabilityFir
-rw-r--r-- 1 mcc users 1.6K Apr 22 14:38 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Apr 22 14:38 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 3 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 1.9M May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from
FORMULA_NAME DLCshifumi-PT-4a-LTLFireability-00
FORMULA_NAME DLCshifumi-PT-4a-LTLFireability-01
FORMULA_NAME DLCshifumi-PT-4a-LTLFireability-02
FORMULA_NAME DLCshifumi-PT-4a-LTLFireability-03
FORMULA_NAME DLCshifumi-PT-4a-LTLFireability-04
FORMULA_NAME DLCshifumi-PT-4a-LTLFireability-05
FORMULA_NAME DLCshifumi-PT-4a-LTLFireability-06
FORMULA_NAME DLCshifumi-PT-4a-LTLFireability-07
FORMULA_NAME DLCshifumi-PT-4a-LTLFireability-08
FORMULA_NAME DLCshifumi-PT-4a-LTLFireability-09
FORMULA_NAME DLCshifumi-PT-4a-LTLFireability-10
FORMULA_NAME DLCshifumi-PT-4a-LTLFireability-11
FORMULA_NAME DLCshifumi-PT-4a-LTLFireability-12
FORMULA_NAME DLCshifumi-PT-4a-LTLFireability-13
FORMULA_NAME DLCshifumi-PT-4a-LTLFireability-14
FORMULA_NAME DLCshifumi-PT-4a-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1717133572380

BK_STOP 1717133999369

--------------------
content from stderr:

[[35mlola[0m][I] LoLA will run for 3600 seconds
[[35mlola[0m][W] [1m[33munknown unit in memory
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlne
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition
[[35mlola[0m][I] closed [1m[34mnet[0m file
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlfor
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] Rule S: 0 transitions removed,0
[[35mlola[0m][I] LAUNCH task # 3 (type CNST)
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 3 (type CNST)
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 16 (type CNST)
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 16 (type CNST)
[[35mlola[0m][I] result : false
[*** LOG ERROR #0001 ***] [2024-05-31 05:32:53]
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 32 (type EXCL)
[[35mlola[0m][I] time limit : 189 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 32 (type EXCL)
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-00:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-07:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-01:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-02:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-04:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-05:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-06:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-08:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-09:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-10:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-11:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-12:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-13:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-14:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 6 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible:
[[35mlola[0m][I] LAUNCH task # 69 (type EXCL)
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 69 (type EXCL)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 54 (type EXCL)
[[35mlola[0m][I] time limit : 224 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 54 (type EXCL)
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 71 (type EXCL)
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 71 (type EXCL)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 61 (type EXCL)
[[35mlola[0m][I] time limit : 256 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 61 (type EXCL)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 41 (type EXCL)
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 41 (type EXCL)
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 74 (type EXCL)
[[35mlola[0m][I] time limit : 326 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 74 (type EXCL)
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 64 (type EXCL)
[[35mlola[0m][I] time limit : 359 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 64 (type EXCL)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 24 (type EXCL)
[[35mlola[0m][I] time limit : 399 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 24 (type EXCL)
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 11 (type EXCL)
[[35mlola[0m][I] time limit : 448 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 11 (type EXCL)
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 44 (type EXCL)
[[35mlola[0m][I] time limit : 513 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-00:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-05:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-11:
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-4a-LTLFireability-13:
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-4a-LTLFireability-14:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-01:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-04:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-06:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-09:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-10:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 44 LTL EXCL 2/513
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 11 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-00:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-05:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-11:
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-4a-LTLFireability-13:
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-4a-LTLFireability-14:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-01:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-04:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-06:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-09:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-10:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 44 LTL EXCL 7/513
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 16 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-00:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-05:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-11:
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-4a-LTLFireability-13:
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-4a-LTLFireability-14:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-01:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-04:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-06:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-09:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-10:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 44 LTL EXCL 12/513
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 21 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-00:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-05:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-11:
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-4a-LTLFireability-13:
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-4a-LTLFireability-14:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-01:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-04:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-06:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-09:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-10:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 44 LTL EXCL 17/513
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 26 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-00:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-05:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-11:
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-4a-LTLFireability-13:
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-4a-LTLFireability-14:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-01:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-04:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-06:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-09:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-10:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 44 LTL EXCL 22/513
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 31 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-00:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-05:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-11:
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-4a-LTLFireability-13:
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-4a-LTLFireability-14:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-01:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-04:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-06:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-09:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-10:
[[35mlola[0m][.] DLCshifumi-PT-4a-LTLFireability-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 44 LTL EXCL 27/513
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 36 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-4a-LTLFireability-00:
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=================================== lity ============= txt xml txt xml esDefinition.xml esVerdict.xml txt xml txt xml dinality.txt dinality.xml eability.txt eability.xml (invocation template) text file) at most ([1m[36m--timelimit[0m) specification: using default[0m [4m[34mmodel.pnml[0m t[0m) net [4m[34mmodel.pnml[0m mula[0m) from [4m[34mLTLFireability.xml[0m places removed for 0 DLCshifumi-PT-4a-LTLFireability-00 for DLCshifumi-PT-4a-LTLFireability-00 for 13 DLCshifumi-PT-4a-LTLFireability-03 for DLCshifumi-PT-4a-LTLFireability-03 [status_logger] string pointer is null for 29 DLCshifumi-PT-4a-LTLFireability-07 for DLCshifumi-PT-4a-LTLFireability-07 2 2 0 1 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CONJ false preprocessing[0m CONJ false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 16 for 66 DLCshifumi-PT-4a-LTLFireability-14 for DLCshifumi-PT-4a-LTLFireability-14 1 0 1 for 53 DLCshifumi-PT-4a-LTLFireability-11 for DLCshifumi-PT-4a-LTLFireability-11 11 119 0 1 for 66 DLCshifumi-PT-4a-LTLFireability-14 for DLCshifumi-PT-4a-LTLFireability-14 2 1 0 1 for 56 DLCshifumi-PT-4a-LTLFireability-12 for DLCshifumi-PT-4a-LTLFireability-12 2 1 0 1 for 36 DLCshifumi-PT-4a-LTLFireability-08 for DLCshifumi-PT-4a-LTLFireability-08 3 3 0 1 for 73 DLCshifumi-PT-4a-LTLFireability-15 for DLCshifumi-PT-4a-LTLFireability-15 21 21 0 1 for 63 DLCshifumi-PT-4a-LTLFireability-13 for DLCshifumi-PT-4a-LTLFireability-13 2 1 0 1 for 23 DLCshifumi-PT-4a-LTLFireability-05 for DLCshifumi-PT-4a-LTLFireability-05 37 42 0 1 for 10 DLCshifumi-PT-4a-LTLFireability-02 for DLCshifumi-PT-4a-LTLFireability-02 23 23 0 1 for 43 DLCshifumi-PT-4a-LTLFireability-09 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCshifumi-PT-4a-LTLFireability-09 51393 m, 10278 m/sec, 566963 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 2/2000 DLCshifumi-PT-4a-LTLFireability-09 187107 m, 27142 m/sec, 2020349 t fired, . Pages in use: 2 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 3/2000 DLCshifumi-PT-4a-LTLFireability-09 332767 m, 29132 m/sec, 3595764 t fired, . Pages in use: 3 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 4/2000 DLCshifumi-PT-4a-LTLFireability-09 476357 m, 28718 m/sec, 5143588 t fired, . Pages in use: 4 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 5/2000 DLCshifumi-PT-4a-LTLFireability-09 619429 m, 28614 m/sec, 6696324 t fired, . Pages in use: 5 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 7/2000 DLCshifumi-PT-4a-LTLFireability-09 762615 m, 28637 m/sec, 8249667 t fired, . Pages in use: 7 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 8/2000 DLCshifumi-PT-4a-LTLFireability-09 904911 m, 28459 m/sec, 9820041 t fired, . Pages in use: 8 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 9/2000 DLCshifumi-PT-4a-LTLFireability-09 1046561 m, 28330 m/sec, 11387729 t fired, . Pages in use: 9 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 10/2000 DLCshifumi-PT-4a-LTLFireability-09 1186379 m, 27963 m/sec, 12968847 t fired, . Pages in use: 10 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 11/2000 DLCshifumi-PT-4a-LTLFireability-09 1328472 m, 28418 m/sec, 14515740 t fired, . Pages in use: 11 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 12/2000 DLCshifumi-PT-4a-LTLFireability-09 1469823 m, 28270 m/sec, 16037603 t fired, . Pages in use: 12 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 13/2000 DLCshifumi-PT-4a-LTLFireability-09 1611540 m, 28343 m/sec, 17566100 t fired, . Pages in use: 13 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 15/2000 DLCshifumi-PT-4a-LTLFireability-09 1751447 m, 27981 m/sec, 19101376 t fired, . Pages in use: 15 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 16/2000 DLCshifumi-PT-4a-LTLFireability-09 1891005 m, 27911 m/sec, 20656709 t fired, . Pages in use: 16 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 17/2000 DLCshifumi-PT-4a-LTLFireability-09 2028645 m, 27528 m/sec, 22200678 t fired, . Pages in use: 17 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 18/2000 DLCshifumi-PT-4a-LTLFireability-09 2169051 m, 28081 m/sec, 23736666 t fired, . Pages in use: 18 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 19/2000 DLCshifumi-PT-4a-LTLFireability-09 2309253 m, 28040 m/sec, 25280826 t fired, . Pages in use: 19 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 20/2000 DLCshifumi-PT-4a-LTLFireability-09 2448037 m, 27756 m/sec, 26831428 t fired, . Pages in use: 20 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 21/2000 DLCshifumi-PT-4a-LTLFireability-09 2589493 m, 28291 m/sec, 28359802 t fired, . Pages in use: 21 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 22/2000 DLCshifumi-PT-4a-LTLFireability-09 2729851 m, 28071 m/sec, 29874324 t fired, . Pages in use: 22 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 23/2000 DLCshifumi-PT-4a-LTLFireability-09 2867955 m, 27620 m/sec, 31409507 t fired, . Pages in use: 23 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 25/2000 DLCshifumi-PT-4a-LTLFireability-09 3009381 m, 28285 m/sec, 32939321 t fired, . Pages in use: 25 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 26/2000 DLCshifumi-PT-4a-LTLFireability-09 3148437 m, 27811 m/sec, 34482356 t fired, . Pages in use: 26 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 27/2000 DLCshifumi-PT-4a-LTLFireability-09 3288487 m, 28010 m/sec, 36009405 t fired, . Pages in use: 27 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 28/2000 DLCshifumi-PT-4a-LTLFireability-09 3426737 m, 27650 m/sec, 37567139 t fired, . Pages in use: 28 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 29/2000 DLCshifumi-PT-4a-LTLFireability-09 3564670 m, 27586 m/sec, 39099476 t fired, . Pages in use: 29 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 30/2000 DLCshifumi-PT-4a-LTLFireability-09 3703395 m, 27745 m/sec, 40639784 t fired, . Pages in use: 30 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 31/2000 DLCshifumi-PT-4a-LTLFireability-09 3842137 m, 27748 m/sec, 42143196 t fired, . Pages in use: 31 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 32/2000 DLCshifumi-PT-4a-LTLFireability-09 3981631 m, 27898 m/sec, 43641661 t fired, . Pages in use: 32 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 33/2000 DLCshifumi-PT-4a-LTLFireability-09 4119734 m, 27620 m/sec, 45147114 t fired, . Pages in use: 33 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 35/2000 DLCshifumi-PT-4a-LTLFireability-09 4256839 m, 27421 m/sec, 46674593 t fired, . Pages in use: 35 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 36/2000 DLCshifumi-PT-4a-LTLFireability-09 4392173 m, 27066 m/sec, 48203271 t fired, . Pages in use: 36 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 37/2000 DLCshifumi-PT-4a-LTLFireability-09 4529117 m, 27388 m/sec, 49721365 t fired, . Pages in use: 37 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 38/2000 DLCshifumi-PT-4a-LTLFireability-09 4666739 m, 27524 m/sec, 51233782 t fired, . Pages in use: 38 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 39/2000 DLCshifumi-PT-4a-LTLFireability-09 4804345 m, 27521 m/sec, 52756061 t fired, . Pages in use: 39 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 40/2000 DLCshifumi-PT-4a-LTLFireability-09 4942425 m, 27616 m/sec, 54267877 t fired, . Pages in use: 40 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 41/2000 DLCshifumi-PT-4a-LTLFireability-09 5081541 m, 27823 m/sec, 55759639 t fired, . Pages in use: 41 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 42/2000 DLCshifumi-PT-4a-LTLFireability-09 5221099 m, 27911 m/sec, 57283392 t fired, . Pages in use: 42 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 43/2000 DLCshifumi-PT-4a-LTLFireability-09 5358839 m, 27548 m/sec, 58816416 t fired, . Pages in use: 43 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 44/2000 DLCshifumi-PT-4a-LTLFireability-09 5496153 m, 27462 m/sec, 60338958 t fired, . Pages in use: 44 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 45/2000 DLCshifumi-PT-4a-LTLFireability-09 5631646 m, 27098 m/sec, 61871204 t fired, . Pages in use: 45 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 46/2000 DLCshifumi-PT-4a-LTLFireability-09 5767655 m, 27201 m/sec, 63401808 t fired, . Pages in use: 46 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 48/2000 DLCshifumi-PT-4a-LTLFireability-09 5909639 m, 28396 m/sec, 64940675 t fired, . Pages in use: 48 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 49/2000 DLCshifumi-PT-4a-LTLFireability-09 6051229 m, 28318 m/sec, 66472479 t fired, . Pages in use: 49 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 50/2000 DLCshifumi-PT-4a-LTLFireability-09 6189366 m, 27627 m/sec, 68018828 t fired, . Pages in use: 50 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 51/2000 DLCshifumi-PT-4a-LTLFireability-09 6324709 m, 27068 m/sec, 69551767 t fired, . Pages in use: 51 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 52/2000 DLCshifumi-PT-4a-LTLFireability-09 6460135 m, 27085 m/sec, 71078604 t fired, . Pages in use: 52 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 53/2000 DLCshifumi-PT-4a-LTLFireability-09 6588969 m, 25766 m/sec, 72552979 t fired, . Pages in use: 53 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 54/2000 DLCshifumi-PT-4a-LTLFireability-09 6723934 m, 26993 m/sec, 74090742 t fired, . Pages in use: 54 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 55/2000 DLCshifumi-PT-4a-LTLFireability-09 6859985 m, 27210 m/sec, 75610101 t fired, . Pages in use: 55 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 56/2000 DLCshifumi-PT-4a-LTLFireability-09 6995749 m, 27152 m/sec, 77114762 t fired, . Pages in use: 56 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 57/2000 DLCshifumi-PT-4a-LTLFireability-09 7129387 m, 26727 m/sec, 78629328 t fired, . Pages in use: 57 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 58/2000 DLCshifumi-PT-4a-LTLFireability-09 7263039 m, 26730 m/sec, 80154476 t fired, . Pages in use: 58 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 59/2000 DLCshifumi-PT-4a-LTLFireability-09 7396267 m, 26645 m/sec, 81684857 t fired, . Pages in use: 59 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 60/2000 DLCshifumi-PT-4a-LTLFireability-09 7529865 m, 26719 m/sec, 83221087 t fired, . Pages in use: 60 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 61/2000 DLCshifumi-PT-4a-LTLFireability-09 7664233 m, 26873 m/sec, 84751174 t fired, . Pages in use: 61 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 62/2000 DLCshifumi-PT-4a-LTLFireability-09 7796319 m, 26417 m/sec, 86286710 t fired, . Pages in use: 62 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 64/2000 DLCshifumi-PT-4a-LTLFireability-09 7928715 m, 26479 m/sec, 87807935 t fired, . Pages in use: 64 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 65/2000 DLCshifumi-PT-4a-LTLFireability-09 8066551 m, 27567 m/sec, 89309097 t fired, . Pages in use: 65 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 66/2000 DLCshifumi-PT-4a-LTLFireability-09 8204901 m, 27670 m/sec, 90799731 t fired, . Pages in use: 66 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 67/2000 DLCshifumi-PT-4a-LTLFireability-09 8339108 m, 26841 m/sec, 92317366 t fired, . Pages in use: 67 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 68/2000 DLCshifumi-PT-4a-LTLFireability-09 8470717 m, 26321 m/sec, 93845844 t fired, . Pages in use: 68 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 69/2000 DLCshifumi-PT-4a-LTLFireability-09 8605316 m, 26919 m/sec, 95343560 t fired, . Pages in use: 69 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 70/2000 DLCshifumi-PT-4a-LTLFireability-09 8742069 m, 27350 m/sec, 96816232 t fired, . Pages in use: 70 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 71/2000 DLCshifumi-PT-4a-LTLFireability-09 8875369 m, 26660 m/sec, 98320947 t fired, . Pages in use: 71 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 72/2000 DLCshifumi-PT-4a-LTLFireability-09 9011055 m, 27137 m/sec, 99830568 t fired, . Pages in use: 72 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 73/2000 DLCshifumi-PT-4a-LTLFireability-09 9144347 m, 26658 m/sec, 101344614 t fired, . Pages in use: 73 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 74/2000 DLCshifumi-PT-4a-LTLFireability-09 9275941 m, 26318 m/sec, 102853475 t fired, . Pages in use: 74 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 75/2000 DLCshifumi-PT-4a-LTLFireability-09 9408035 m, 26418 m/sec, 104366054 t fired, . Pages in use: 75 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 76/2000 DLCshifumi-PT-4a-LTLFireability-09 9543089 m, 27010 m/sec, 105852190 t fired, . Pages in use: 76 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 77/2000 DLCshifumi-PT-4a-LTLFireability-09 9674327 m, 26247 m/sec, 107380622 t fired, . Pages in use: 77 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 78/2000 DLCshifumi-PT-4a-LTLFireability-09 9808659 m, 26866 m/sec, 108934372 t fired, . Pages in use: 78 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 79/2000 DLCshifumi-PT-4a-LTLFireability-09 9939743 m, 26216 m/sec, 110444900 t fired, . Pages in use: 79 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 80/2000 DLCshifumi-PT-4a-LTLFireability-09 10070767 m, 26204 m/sec, 111861709 t fired, . Pages in use: 80 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 82/2000 DLCshifumi-PT-4a-LTLFireability-09 10208649 m, 27576 m/sec, 113346543 t fired, . Pages in use: 82 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 83/2000 DLCshifumi-PT-4a-LTLFireability-09 10345187 m, 27307 m/sec, 114837407 t fired, . Pages in use: 83 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 84/2000 DLCshifumi-PT-4a-LTLFireability-09 10481837 m, 27330 m/sec, 116338022 t fired, . Pages in use: 84 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 85/2000 DLCshifumi-PT-4a-LTLFireability-09 10616919 m, 27016 m/sec, 117828020 t fired, . Pages in use: 85 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 86/2000 DLCshifumi-PT-4a-LTLFireability-09 10754805 m, 27577 m/sec, 119324375 t fired, . Pages in use: 86 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 87/2000 DLCshifumi-PT-4a-LTLFireability-09 10887007 m, 26440 m/sec, 120756719 t fired, . Pages in use: 87 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 88/2000 DLCshifumi-PT-4a-LTLFireability-09 11023211 m, 27240 m/sec, 122232667 t fired, . Pages in use: 88 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 89/2000 DLCshifumi-PT-4a-LTLFireability-09 11157943 m, 26946 m/sec, 123720055 t fired, . Pages in use: 89 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 90/2000 DLCshifumi-PT-4a-LTLFireability-09 11294147 m, 27240 m/sec, 125239792 t fired, . Pages in use: 90 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m CONJ true CONJ[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 91/2000 DLCshifumi-PT-4a-LTLFireability-09 11426644 m, 26499 m/sec, 126713886 t fired, . Pages in use: 91 16 $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCshifumi-PT-4a"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is DLCshifumi-PT-4a, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r115-smll-171624276800324"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCshifumi-PT-4a.tgz
mv DLCshifumi-PT-4a execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;