About the Execution of LoLA for DLCshifumi-PT-2a
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16208.527 | 1004472.00 | 1162986.00 | 4559.50 | ?????????????F?? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r115-smll-171624276700290.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is DLCshifumi-PT-2a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r115-smll-171624276700290
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 672K
-rw-r--r-- 1 mcc users 5.9K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 61K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.0K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 46K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.0K Apr 22 14:38 LTLCardinality.txt
-rw-r--r-- 1 mcc users 29K Apr 22 14:38 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Apr 22 14:38 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 22 14:38 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Apr 13 06:58 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 138K Apr 13 06:58 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.0K Apr 13 06:42 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 68K Apr 13 06:42 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 22 14:38 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Apr 22 14:38 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 3 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 213K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCshifumi-PT-2a-CTLFireability-2024-00
FORMULA_NAME DLCshifumi-PT-2a-CTLFireability-2024-01
FORMULA_NAME DLCshifumi-PT-2a-CTLFireability-2024-02
FORMULA_NAME DLCshifumi-PT-2a-CTLFireability-2024-03
FORMULA_NAME DLCshifumi-PT-2a-CTLFireability-2024-04
FORMULA_NAME DLCshifumi-PT-2a-CTLFireability-2024-05
FORMULA_NAME DLCshifumi-PT-2a-CTLFireability-2024-06
FORMULA_NAME DLCshifumi-PT-2a-CTLFireability-2024-07
FORMULA_NAME DLCshifumi-PT-2a-CTLFireability-2024-08
FORMULA_NAME DLCshifumi-PT-2a-CTLFireability-2024-09
FORMULA_NAME DLCshifumi-PT-2a-CTLFireability-2024-10
FORMULA_NAME DLCshifumi-PT-2a-CTLFireability-2024-11
FORMULA_NAME DLCshifumi-PT-2a-CTLFireability-2023-12
FORMULA_NAME DLCshifumi-PT-2a-CTLFireability-2023-13
FORMULA_NAME DLCshifumi-PT-2a-CTLFireability-2023-14
FORMULA_NAME DLCshifumi-PT-2a-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717115343219
FORMULA DLCshifumi-PT-2a-CTLFireability-2023-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717116347691
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 17 (type EXCL) for 16 DLCshifumi-PT-2a-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 163 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 60 (type EQUN) for 19 DLCshifumi-PT-2a-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 62 (type EQUN) for 19 DLCshifumi-PT-2a-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 62 (type EQUN) for DLCshifumi-PT-2a-CTLFireability-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 60 (type EQUN) for DLCshifumi-PT-2a-CTLFireability-2024-05
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 64 (type FNDP) for 47 DLCshifumi-PT-2a-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 65 (type EQUN) for 47 DLCshifumi-PT-2a-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 64 (type FNDP) for DLCshifumi-PT-2a-CTLFireability-2023-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 65 (type EQUN) for DLCshifumi-PT-2a-CTLFireability-2023-13 (obsolete)
[[35mlola[0m][I] FINISHED task # 65 (type EQUN) for DLCshifumi-PT-2a-CTLFireability-2023-13
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 4/211 1/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 177573 m, 35514 m/sec, 4385220 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 9/211 2/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 371013 m, 38688 m/sec, 9666102 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 14/211 3/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 570054 m, 39808 m/sec, 14908548 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 19/211 4/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 762446 m, 38478 m/sec, 20177694 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 24/211 5/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 948711 m, 37253 m/sec, 25403879 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 29/211 5/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 1135017 m, 37261 m/sec, 30600520 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 34/211 6/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 1318624 m, 36721 m/sec, 35797344 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 39/211 7/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 1488030 m, 33881 m/sec, 40769039 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 44/211 8/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 1660815 m, 34557 m/sec, 45951138 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 49/211 8/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 1832900 m, 34417 m/sec, 51097431 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 54/211 9/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 2001443 m, 33708 m/sec, 56235263 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 59/211 10/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 2172905 m, 34292 m/sec, 61360506 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 64/211 10/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 2353124 m, 36043 m/sec, 66456739 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 69/211 11/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 2515951 m, 32565 m/sec, 71591213 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 74/211 12/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 2696837 m, 36177 m/sec, 76641706 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 79/211 13/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 2867747 m, 34182 m/sec, 81700769 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 84/211 13/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 3049144 m, 36279 m/sec, 86816471 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 89/211 14/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 3230321 m, 36235 m/sec, 91856335 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 94/211 15/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 3401475 m, 34230 m/sec, 96928693 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 99/211 16/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 3584848 m, 36674 m/sec, 101972138 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 104/211 16/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 3766003 m, 36231 m/sec, 107022889 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 109/211 17/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 3950524 m, 36904 m/sec, 112072424 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 17
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 114/211 18/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 4136896 m, 37274 m/sec, 117122589 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 119/211 19/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 4310629 m, 34746 m/sec, 122161823 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 19
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 124/211 19/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 4480393 m, 33952 m/sec, 127173196 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 19
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 129/211 20/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 4653781 m, 34677 m/sec, 132188740 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 20
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 134/211 21/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 4823830 m, 34009 m/sec, 137215026 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 139/211 22/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 4991730 m, 33580 m/sec, 142262580 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 140 secs. Pages in use: 22
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 144/211 22/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 5157765 m, 33207 m/sec, 147286649 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 145 secs. Pages in use: 22
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 149/211 23/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 5320280 m, 32503 m/sec, 152313336 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 154/211 24/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 5485142 m, 32972 m/sec, 157289810 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 155 secs. Pages in use: 24
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 159/211 24/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 5650873 m, 33146 m/sec, 162277565 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 160 secs. Pages in use: 24
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 164/211 25/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 5817736 m, 33372 m/sec, 167276516 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 165 secs. Pages in use: 25
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 169/211 26/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 5979207 m, 32294 m/sec, 172283650 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 170 secs. Pages in use: 26
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 174/211 26/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 6143134 m, 32785 m/sec, 177295667 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 175 secs. Pages in use: 26
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 179/211 27/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 6308954 m, 33164 m/sec, 182325353 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 180 secs. Pages in use: 27
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 184/211 28/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 6466337 m, 31476 m/sec, 187315009 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 185 secs. Pages in use: 28
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 189/211 28/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 6632353 m, 33203 m/sec, 192313213 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 190 secs. Pages in use: 28
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 194/211 29/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 6802833 m, 34096 m/sec, 197280018 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 195 secs. Pages in use: 29
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 199/211 30/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 6961929 m, 31819 m/sec, 202289606 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 200 secs. Pages in use: 30
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 204/211 31/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 7129713 m, 33556 m/sec, 207295651 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 205 secs. Pages in use: 31
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 209/211 31/2000 DLCshifumi-PT-2a-CTLFireability-2024-04 7290162 m, 32089 m/sec, 212254062 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 210 secs. Pages in use: 31
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 17 (type EXCL) for DLCshifumi-PT-2a-CTLFireability-2024-04 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 215 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 51 (type EXCL) for 50 DLCshifumi-PT-2a-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 17 (type EXCL) for 16 DLCshifumi-PT-2a-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 3385 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 51 (type EXCL) for DLCshifumi-PT-2a-CTLFireability-2023-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 12
[[35mlola[0m][I] fired transitions : 162
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 5/211 1/5 DLCshifumi-PT-2a-CTLFireability-2024-04 206801 m, -1416672 m/sec, 5142821 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 220 secs. Pages in use: 34
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 10/211 2/5 DLCshifumi-PT-2a-CTLFireability-2024-04 385865 m, 35812 m/sec, 10080347 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 225 secs. Pages in use: 34
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 15/211 3/5 DLCshifumi-PT-2a-CTLFireability-2024-04 578897 m, 38606 m/sec, 15210905 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 230 secs. Pages in use: 35
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 20/211 4/5 DLCshifumi-PT-2a-CTLFireability-2024-04 760494 m, 36319 m/sec, 20119492 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 235 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 25/211 4/5 DLCshifumi-PT-2a-CTLFireability-2024-04 922146 m, 32330 m/sec, 24634468 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 240 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 30/211 5/5 DLCshifumi-PT-2a-CTLFireability-2024-04 1104882 m, 36547 m/sec, 29812095 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 245 secs. Pages in use: 37
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 17 (type EXCL) for DLCshifumi-PT-2a-CTLFireability-2024-04 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 250 secs. Pages in use: 37
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 42 (type EXCL) for 41 DLCshifumi-PT-2a-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 223 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 42 (type EXCL) for DLCshifumi-PT-2a-CTLFireability-2024-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 47
[[35mlola[0m][I] fired transitions : 436
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 39 (type EXCL) for 38 DLCshifumi-PT-2a-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 5/239 2/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 397426 m, 79485 m/sec, 5259994 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 255 secs. Pages in use: 37
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 10/239 4/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 805313 m, 81577 m/sec, 10452681 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 260 secs. Pages in use: 37
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 15/239 6/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 1200007 m, 78938 m/sec, 15641499 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 265 secs. Pages in use: 38
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 20/239 7/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 1613887 m, 82776 m/sec, 20728655 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 270 secs. Pages in use: 39
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 25/239 9/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 1982623 m, 73747 m/sec, 25518088 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 275 secs. Pages in use: 41
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 30/239 11/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 2388518 m, 81179 m/sec, 30628525 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 280 secs. Pages in use: 43
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 35/239 12/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 2777989 m, 77894 m/sec, 35647351 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 285 secs. Pages in use: 44
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 40/239 14/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 3192018 m, 82805 m/sec, 40727711 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 290 secs. Pages in use: 46
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 45/239 16/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 3607459 m, 83088 m/sec, 45795331 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 295 secs. Pages in use: 48
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 50/239 17/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 4025738 m, 83655 m/sec, 50914534 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 300 secs. Pages in use: 49
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 55/239 19/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 4424626 m, 79777 m/sec, 55851409 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 305 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 60/239 21/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 4803307 m, 75736 m/sec, 60792767 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 310 secs. Pages in use: 53
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 65/239 22/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 5183326 m, 76003 m/sec, 65600158 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 315 secs. Pages in use: 54
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 70/239 24/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 5569088 m, 77152 m/sec, 70525897 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 320 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 75/239 26/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 5934202 m, 73022 m/sec, 75244484 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 325 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 80/239 26/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 6058949 m, 24949 m/sec, 79723460 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 330 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 85/239 27/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 6205962 m, 29402 m/sec, 85418907 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 335 secs. Pages in use: 59
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 90/239 27/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 6370402 m, 32888 m/sec, 91057878 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 340 secs. Pages in use: 59
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 95/239 28/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 6532393 m, 32398 m/sec, 96654140 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 345 secs. Pages in use: 60
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 100/239 29/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 6686542 m, 30829 m/sec, 102244896 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 350 secs. Pages in use: 61
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 105/239 29/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 6843944 m, 31480 m/sec, 107789606 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 355 secs. Pages in use: 61
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 110/239 30/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 6999965 m, 31204 m/sec, 113285582 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 360 secs. Pages in use: 62
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 115/239 31/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 7141651 m, 28337 m/sec, 118813078 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 365 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 120/239 31/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 7287141 m, 29098 m/sec, 124340612 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 370 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 125/239 32/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 7427086 m, 27989 m/sec, 129832643 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 375 secs. Pages in use: 64
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 130/239 32/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 7570893 m, 28761 m/sec, 135333619 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 380 secs. Pages in use: 64
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 135/239 33/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 7716993 m, 29220 m/sec, 140710666 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 385 secs. Pages in use: 65
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 140/239 34/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 7852819 m, 27165 m/sec, 146063870 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 390 secs. Pages in use: 66
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 145/239 34/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 8001515 m, 29739 m/sec, 151341344 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 395 secs. Pages in use: 66
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 150/239 35/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 8145403 m, 28777 m/sec, 156742390 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 400 secs. Pages in use: 67
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 155/239 36/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 8307458 m, 32411 m/sec, 162194536 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 405 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 160/239 36/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 8466137 m, 31735 m/sec, 167641899 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 410 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 165/239 37/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 8620618 m, 30896 m/sec, 173073389 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 415 secs. Pages in use: 69
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 170/239 38/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 8785863 m, 33049 m/sec, 178454744 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 420 secs. Pages in use: 70
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 175/239 38/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 8952851 m, 33397 m/sec, 183899158 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 425 secs. Pages in use: 70
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 180/239 39/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 9131078 m, 35645 m/sec, 189282190 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 430 secs. Pages in use: 71
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 185/239 40/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 9289161 m, 31616 m/sec, 194700049 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 435 secs. Pages in use: 72
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 190/239 40/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 9449193 m, 32006 m/sec, 200041907 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 440 secs. Pages in use: 72
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 195/239 41/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 9599013 m, 29964 m/sec, 205391889 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 445 secs. Pages in use: 73
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 200/239 42/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 9752018 m, 30601 m/sec, 210794680 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 450 secs. Pages in use: 74
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 205/239 42/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 9903620 m, 30320 m/sec, 216219096 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 455 secs. Pages in use: 74
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 210/239 43/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 10055153 m, 30306 m/sec, 221608402 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 460 secs. Pages in use: 75
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 215/239 43/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 10193754 m, 27720 m/sec, 227042146 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 465 secs. Pages in use: 75
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 220/239 44/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 10334930 m, 28235 m/sec, 232424600 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 470 secs. Pages in use: 76
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 225/239 45/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 10481601 m, 29334 m/sec, 237768175 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 475 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 230/239 45/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 10631552 m, 29990 m/sec, 243138250 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 480 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 235/239 46/2000 DLCshifumi-PT-2a-CTLFireability-2024-10 10775908 m, 28871 m/sec, 248489696 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 485 secs. Pages in use: 78
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 39 (type EXCL) for DLCshifumi-PT-2a-CTLFireability-2024-10 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 490 secs. Pages in use: 79
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 36 (type EXCL) for 35 DLCshifumi-PT-2a-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 39 (type EXCL) for 38 DLCshifumi-PT-2a-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 3110 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 5/239 1/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 170722 m, 34144 m/sec, 5439990 t fired, .
[[35mlola[0m][.] 39 CTL EXCL 5/3110 2/5 DLCshifumi-PT-2a-CTLFireability-2024-10 418186 m, -2071544 m/sec, 5529070 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 495 secs. Pages in use: 82
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 10/239 2/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 347636 m, 35382 m/sec, 11403941 t fired, .
[[35mlola[0m][.] 39 CTL EXCL 10/222 4/5 DLCshifumi-PT-2a-CTLFireability-2024-10 832870 m, 82936 m/sec, 10827828 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 500 secs. Pages in use: 85
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 39 (type EXCL) for DLCshifumi-PT-2a-CTLFireability-2024-10 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 15/239 3/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 523364 m, 35145 m/sec, 17319853 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 505 secs. Pages in use: 87
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 20/239 3/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 691859 m, 33699 m/sec, 23173257 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 510 secs. Pages in use: 87
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 25/239 4/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 858265 m, 33281 m/sec, 29015843 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 515 secs. Pages in use: 87
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 30/239 5/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 1022446 m, 32836 m/sec, 34782980 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 520 secs. Pages in use: 87
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 35/239 6/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 1181357 m, 31782 m/sec, 40547187 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 525 secs. Pages in use: 87
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 40/239 6/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 1339269 m, 31582 m/sec, 46282378 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 530 secs. Pages in use: 87
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 45/239 7/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 1494855 m, 31117 m/sec, 52019004 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 535 secs. Pages in use: 87
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 50/239 7/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 1650913 m, 31211 m/sec, 57688837 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 540 secs. Pages in use: 87
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 55/239 8/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 1808866 m, 31590 m/sec, 63410502 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 545 secs. Pages in use: 87
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 60/239 9/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 1971168 m, 32460 m/sec, 69127979 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 550 secs. Pages in use: 88
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 65/239 9/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 2125801 m, 30926 m/sec, 74832449 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 555 secs. Pages in use: 88
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 70/239 10/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 2288222 m, 32484 m/sec, 80512220 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 560 secs. Pages in use: 89
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 75/239 11/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 2443787 m, 31113 m/sec, 86173150 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 565 secs. Pages in use: 90
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 80/239 11/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 2603322 m, 31907 m/sec, 91880115 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 570 secs. Pages in use: 90
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 85/239 12/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 2765819 m, 32499 m/sec, 97588455 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 575 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 90/239 13/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 2921343 m, 31104 m/sec, 103248106 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 580 secs. Pages in use: 92
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 95/239 13/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 3078908 m, 31513 m/sec, 108881637 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 585 secs. Pages in use: 92
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 100/239 14/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 3241477 m, 32513 m/sec, 114593101 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 590 secs. Pages in use: 93
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 105/239 15/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 3402053 m, 32115 m/sec, 120281051 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 595 secs. Pages in use: 94
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 110/239 16/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 3559550 m, 31499 m/sec, 125962060 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 600 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 115/239 16/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 3713057 m, 30701 m/sec, 131603974 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 605 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 120/239 17/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 3867161 m, 30820 m/sec, 137235405 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 610 secs. Pages in use: 96
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 125/239 17/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 4017094 m, 29986 m/sec, 142840329 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 615 secs. Pages in use: 96
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 130/239 18/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 4171122 m, 30805 m/sec, 148482003 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 620 secs. Pages in use: 97
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 135/239 19/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 4321622 m, 30100 m/sec, 154077354 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 625 secs. Pages in use: 98
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 140/239 19/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 4470228 m, 29721 m/sec, 159686113 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 630 secs. Pages in use: 98
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 145/239 20/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 4621654 m, 30285 m/sec, 165250043 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 635 secs. Pages in use: 99
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 150/239 21/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 4772573 m, 30183 m/sec, 170847507 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 640 secs. Pages in use: 100
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 155/239 21/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 4922610 m, 30007 m/sec, 176445287 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 645 secs. Pages in use: 100
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 160/239 22/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 5071225 m, 29723 m/sec, 182035295 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 650 secs. Pages in use: 101
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 165/239 22/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 5220194 m, 29793 m/sec, 187619906 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 655 secs. Pages in use: 101
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 170/239 23/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 5363608 m, 28682 m/sec, 193133909 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 660 secs. Pages in use: 102
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 175/239 24/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 5513336 m, 29945 m/sec, 198715469 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 665 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 180/239 24/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 5666143 m, 30561 m/sec, 204303788 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 670 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 185/239 25/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 5811433 m, 29058 m/sec, 209892636 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 675 secs. Pages in use: 104
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 190/239 26/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 5960235 m, 29760 m/sec, 215440655 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 680 secs. Pages in use: 105
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 195/239 26/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 6107297 m, 29412 m/sec, 220991784 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 685 secs. Pages in use: 105
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 200/239 27/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 6254980 m, 29536 m/sec, 226550019 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 690 secs. Pages in use: 106
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 205/239 27/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 6403749 m, 29753 m/sec, 232115145 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 695 secs. Pages in use: 106
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 210/239 28/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 6552296 m, 29709 m/sec, 237692065 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 700 secs. Pages in use: 107
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 215/239 29/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 6696595 m, 28859 m/sec, 243200788 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 705 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 220/239 29/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 6842536 m, 29188 m/sec, 248766974 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 710 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 225/239 30/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 6989954 m, 29483 m/sec, 254262896 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 715 secs. Pages in use: 109
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 230/239 31/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 7134500 m, 28909 m/sec, 259772738 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 720 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 235/239 31/2000 DLCshifumi-PT-2a-CTLFireability-2024-09 7275484 m, 28196 m/sec, 265224336 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 725 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 36 (type EXCL) for DLCshifumi-PT-2a-CTLFireability-2024-09 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 730 secs. Pages in use: 111
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 30 (type EXCL) for 29 DLCshifumi-PT-2a-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 36 (type EXCL) for 35 DLCshifumi-PT-2a-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 2870 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 5/239 2/2000 DLCshifumi-PT-2a-CTLFireability-2024-07 410384 m, 82076 m/sec, 5419852 t fired, .
[[35mlola[0m][.] 36 CTL EXCL 5/2870 1/5 DLCshifumi-PT-2a-CTLFireability-2024-09 187819 m, -1417533 m/sec, 6008584 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 735 secs. Pages in use: 115
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 10/239 4/2000 DLCshifumi-PT-2a-CTLFireability-2024-07 805625 m, 79048 m/sec, 10487253 t fired, .
[[35mlola[0m][.] 36 CTL EXCL 10/220 2/5 DLCshifumi-PT-2a-CTLFireability-2024-09 363390 m, 35114 m/sec, 11954651 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 740 secs. Pages in use: 119
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 15/239 6/2000 DLCshifumi-PT-2a-CTLFireability-2024-07 1201510 m, 79177 m/sec, 15508654 t fired, .
[[35mlola[0m][.] 36 CTL EXCL 15/220 3/5 DLCshifumi-PT-2a-CTLFireability-2024-09 539460 m, 35214 m/sec, 17855398 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 745 secs. Pages in use: 122
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 20/239 7/2000 DLCshifumi-PT-2a-CTLFireability-2024-07 1578858 m, 75469 m/sec, 20463777 t fired, .
[[35mlola[0m][.] 36 CTL EXCL 20/220 4/5 DLCshifumi-PT-2a-CTLFireability-2024-09 708226 m, 33753 m/sec, 23746223 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 750 secs. Pages in use: 125
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 25/239 9/2000 DLCshifumi-PT-2a-CTLFireability-2024-07 1973904 m, 79009 m/sec, 25535068 t fired, .
[[35mlola[0m][.] 36 CTL EXCL 25/220 4/5 DLCshifumi-PT-2a-CTLFireability-2024-09 875264 m, 33407 m/sec, 29621087 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 755 secs. Pages in use: 127
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 30/239 10/2000 DLCshifumi-PT-2a-CTLFireability-2024-07 2348486 m, 74916 m/sec, 30244497 t fired, .
[[35mlola[0m][.] 36 CTL EXCL 30/220 5/5 DLCshifumi-PT-2a-CTLFireability-2024-09 1039295 m, 32806 m/sec, 35401993 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 760 secs. Pages in use: 130
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 36 (type EXCL) for DLCshifumi-PT-2a-CTLFireability-2024-09 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 35/239 12/2000 DLCshifumi-PT-2a-CTLFireability-2024-07 2721478 m, 74598 m/sec, 34910514 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 765 secs. Pages in use: 133
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 40/239 14/2000 DLCshifumi-PT-2a-CTLFireability-2024-07 3108704 m, 77445 m/sec, 39566192 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 770 secs. Pages in use: 133
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 45/239 15/2000 DLCshifumi-PT-2a-CTLFireability-2024-07 3515644 m, 81388 m/sec, 44714325 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 775 secs. Pages in use: 133
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 50/239 17/2000 DLCshifumi-PT-2a-CTLFireability-2024-07 3913755 m, 79622 m/sec, 49694636 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 780 secs. Pages in use: 134
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 55/239 19/2000 DLCshifumi-PT-2a-CTLFireability-2024-07 4313590 m, 79967 m/sec, 54605222 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 785 secs. Pages in use: 137
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 60/239 20/2000 DLCshifumi-PT-2a-CTLFireability-2024-07 4697308 m, 76743 m/sec, 59552593 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 790 secs. Pages in use: 139
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 65/239 22/2000 DLCshifumi-PT-2a-CTLFireability-2024-07 5083151 m, 77168 m/sec, 64415488 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 795 secs. Pages in use: 141
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 70/239 24/2000 DLCshifumi-PT-2a-CTLFireability-2024-07 5458893 m, 75148 m/sec, 69269114 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 800 secs. Pages in use: 144
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 75/239 25/2000 DLCshifumi-PT-2a-CTLFireability-2024-07 5831845 m, 74590 m/sec, 74046720 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 805 secs. Pages in use: 146
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 80/239 27/2000 DLCshifumi-PT-2a-CTLFireability-2024-07 6203266 m, 74284 m/sec, 78839868 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 810 secs. Pages in use: 148
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 85/239 28/2000 DLCshifumi-PT-2a-CTLFireability-2024-07 6575901 m, 74527 m/sec, 83713484 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 815 secs. Pages in use: 150
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 90/239 30/2000 DLCshifumi-PT-2a-CTLFireability-2024-07 6948663 m, 74552 m/sec, 88524411 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 820 secs. Pages in use: 152
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 95/239 31/2000 DLCshifumi-PT-2a-CTLFireability-2024-07 7332480 m, 76763 m/sec, 93428434 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 825 secs. Pages in use: 154
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 100/239 33/2000 DLCshifumi-PT-2a-CTLFireability-2024-07 7701623 m, 73828 m/sec, 98255350 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 830 secs. Pages in use: 157
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 105/239 35/2000 DLCshifumi-PT-2a-CTLFireability-2024-07 8103364 m, 80348 m/sec, 103138134 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 835 secs. Pages in use: 159
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 110/239 36/2000 DLCshifumi-PT-2a-CTLFireability-2024-07 8484113 m, 76149 m/sec, 107934834 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 840 secs. Pages in use: 161
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 115/239 38/2000 DLCshifumi-PT-2a-CTLFireability-2024-07 8878614 m, 78900 m/sec, 112944702 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 845 secs. Pages in use: 164
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 120/239 40/2000 DLCshifumi-PT-2a-CTLFireability-2024-07 9257889 m, 75855 m/sec, 117749402 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 850 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 125/239 41/2000 DLCshifumi-PT-2a-CTLFireability-2024-07 9662397 m, 80901 m/sec, 122593905 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 855 secs. Pages in use: 168
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 130/239 43/2000 DLCshifumi-PT-2a-CTLFireability-2024-07 10032091 m, 73938 m/sec, 127330829 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 860 secs. Pages in use: 170
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 135/239 44/2000 DLCshifumi-PT-2a-CTLFireability-2024-07 10411704 m, 75922 m/sec, 132142311 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 865 secs. Pages in use: 172
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 140/239 46/2000 DLCshifumi-PT-2a-CTLFireability-2024-07 10801364 m, 77932 m/sec, 136897705 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 870 secs. Pages in use: 175
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 145/239 48/2000 DLCshifumi-PT-2a-CTLFireability-2024-07 11188432 m, 77413 m/sec, 141646830 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 875 secs. Pages in use: 177
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 150/239 49/2000 DLCshifumi-PT-2a-CTLFireability-2024-07 11583050 m, 78923 m/sec, 146418208 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 880 secs. Pages in use: 179
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 155/239 51/2000 DLCshifumi-PT-2a-CTLFireability-2024-07 11955858 m, 74561 m/sec, 151140174 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 885 secs. Pages in use: 181
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 160/239 53/2000 DLCshifumi-PT-2a-CTLFireability-2024-07 12336829 m, 76194 m/sec, 155853278 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 890 secs. Pages in use: 184
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 165/239 54/2000 DLCshifumi-PT-2a-CTLFireability-2024-07 12719101 m, 76454 m/sec, 160552138 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 895 secs. Pages in use: 186
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 170/239 56/2000 DLCshifumi-PT-2a-CTLFireability-2024-07 13130678 m, 82315 m/sec, 165312952 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 900 secs. Pages in use: 188
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 175/239 58/2000 DLCshifumi-PT-2a-CTLFireability-2024-07 13519946 m, 77853 m/sec, 170022108 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 905 secs. Pages in use: 191
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 180/239 59/2000 DLCshifumi-PT-2a-CTLFireability-2024-07 13898203 m, 75651 m/sec, 174756290 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 910 secs. Pages in use: 192
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 185/239 61/2000 DLCshifumi-PT-2a-CTLFireability-2024-07 14254160 m, 71191 m/sec, 179145823 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 915 secs. Pages in use: 195
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 247/239 61/2000 DLCshifumi-PT-2a-CTLFireability-2024-07 14392170 m, 27602 m/sec, 180780496 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 981 secs. Pages in use: 195
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 30 (type EXCL) for DLCshifumi-PT-2a-CTLFireability-2024-07 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCshifumi-PT-2a-CTLFireability-2023-13: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCshifumi-PT-2a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-05: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-07: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCshifumi-PT-2a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 989 secs. Pages in use: 195
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 25 (type EXCL) for 22 DLCshifumi-PT-2a-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 237 sec
[[35mlola[0m][I] memory limit: 2000 pages
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 409 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCshifumi-PT-2a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is DLCshifumi-PT-2a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r115-smll-171624276700290"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DLCshifumi-PT-2a.tgz
mv DLCshifumi-PT-2a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;