About the Execution of LoLA for DLCround-PT-12b
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
15375.348 | 3600000.00 | 1506586.00 | 10844.00 | ?FFFF????F?F?F?? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r115-smll-171624276700267.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is DLCround-PT-12b, examination is LTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r115-smll-171624276700267
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 2.3M
-rw-r--r-- 1 mcc users 6.6K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 68K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.1K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 56K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.3K Apr 22 14:38 LTLCardinality.txt
-rw-r--r-- 1 mcc users 22K Apr 22 14:38 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K May 19 07:16 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K May 19 18:11 LTLFireability.xml
-rw-r--r-- 1 mcc users 7.5K Apr 13 12:12 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 70K Apr 13 12:12 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.5K Apr 13 12:12 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 82K Apr 13 12:12 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 22 14:38 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Apr 22 14:38 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 4 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 1.9M May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-12b-LTLCardinality-00
FORMULA_NAME DLCround-PT-12b-LTLCardinality-01
FORMULA_NAME DLCround-PT-12b-LTLCardinality-02
FORMULA_NAME DLCround-PT-12b-LTLCardinality-03
FORMULA_NAME DLCround-PT-12b-LTLCardinality-04
FORMULA_NAME DLCround-PT-12b-LTLCardinality-05
FORMULA_NAME DLCround-PT-12b-LTLCardinality-06
FORMULA_NAME DLCround-PT-12b-LTLCardinality-07
FORMULA_NAME DLCround-PT-12b-LTLCardinality-08
FORMULA_NAME DLCround-PT-12b-LTLCardinality-09
FORMULA_NAME DLCround-PT-12b-LTLCardinality-10
FORMULA_NAME DLCround-PT-12b-LTLCardinality-11
FORMULA_NAME DLCround-PT-12b-LTLCardinality-12
FORMULA_NAME DLCround-PT-12b-LTLCardinality-13
FORMULA_NAME DLCround-PT-12b-LTLCardinality-14
FORMULA_NAME DLCround-PT-12b-LTLCardinality-15
=== Now, execution of the tool begins
BK_START 1717102383526
FORMULA DLCround-PT-12b-LTLCardinality-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-12b-LTLCardinality-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-12b-LTLCardinality-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-12b-LTLCardinality-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-12b-LTLCardinality-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-12b-LTLCardinality-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-12b-LTLCardinality-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLCardinality.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-01: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-03: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-04: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-09: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-11: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-14: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 292 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 4 (type CNST) for 3 DLCround-PT-12b-LTLCardinality-01
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 4 (type CNST) for DLCround-PT-12b-LTLCardinality-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 10 (type CNST) for 9 DLCround-PT-12b-LTLCardinality-03
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 38 (type CNST) for 37 DLCround-PT-12b-LTLCardinality-11
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 10 (type CNST) for DLCround-PT-12b-LTLCardinality-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 38 (type CNST) for DLCround-PT-12b-LTLCardinality-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-04: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-09: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-14: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 297 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 DLCround-PT-12b-LTLCardinality-02
[[35mlola[0m][I] time limit : 235 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 15 (type CNST) for 12 DLCround-PT-12b-LTLCardinality-04
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 53 (type FNDP) for 31 DLCround-PT-12b-LTLCardinality-09
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 54 (type EQUN) for 31 DLCround-PT-12b-LTLCardinality-09
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 15 (type CNST) for DLCround-PT-12b-LTLCardinality-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 7 (type EXCL) for DLCround-PT-12b-LTLCardinality-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 262
[[35mlola[0m][I] fired transitions : 263
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 55 (type EXCL) for 31 DLCround-PT-12b-LTLCardinality-09
[[35mlola[0m][I] time limit : 300 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 53 (type FNDP) for DLCround-PT-12b-LTLCardinality-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 54 (type EQUN) for DLCround-PT-12b-LTLCardinality-09 (obsolete)
[[35mlola[0m][W] CANCELED task # 55 (type EXCL) for DLCround-PT-12b-LTLCardinality-09 (obsolete)
[[35mlola[0m][I] LAUNCH task # 44 (type EXCL) for 43 DLCround-PT-12b-LTLCardinality-13
[[35mlola[0m][I] time limit : 330 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 44 (type EXCL) for DLCround-PT-12b-LTLCardinality-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 165
[[35mlola[0m][I] fired transitions : 166
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] FINISHED task # 55 (type EXCL) for DLCround-PT-12b-LTLCardinality-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] FINISHED task # 54 (type EQUN) for DLCround-PT-12b-LTLCardinality-09
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-14: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 302 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[*** LOG ERROR #0001 ***] [2024-05-30 20:58:08] [status_logger] string pointer is null
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-14: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 307 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 47 (type EXCL) for 46 DLCround-PT-12b-LTLCardinality-14
[[35mlola[0m][I] time limit : 365 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 47 (type EXCL) for DLCround-PT-12b-LTLCardinality-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 135
[[35mlola[0m][I] fired transitions : 135
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 29 (type EXCL) for 28 DLCround-PT-12b-LTLCardinality-08
[[35mlola[0m][I] time limit : 411 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 29 (type EXCL) for DLCround-PT-12b-LTLCardinality-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 23 (type EXCL) for 22 DLCround-PT-12b-LTLCardinality-06
[[35mlola[0m][I] time limit : 469 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 23 (type EXCL) for DLCround-PT-12b-LTLCardinality-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 135
[[35mlola[0m][I] fired transitions : 135
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 312 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 20 (type EXCL) for 19 DLCround-PT-12b-LTLCardinality-05
[[35mlola[0m][I] time limit : 548 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 20 (type EXCL) for DLCround-PT-12b-LTLCardinality-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 26 (type EXCL) for 25 DLCround-PT-12b-LTLCardinality-07
[[35mlola[0m][I] time limit : 657 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 5/657 2/2000 DLCround-PT-12b-LTLCardinality-07 159532 m, 31906 m/sec, 169596 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 317 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 10/657 4/2000 DLCround-PT-12b-LTLCardinality-07 360580 m, 40209 m/sec, 384083 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 322 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 15/657 6/2000 DLCround-PT-12b-LTLCardinality-07 556801 m, 39244 m/sec, 600102 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 327 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 26 (type EXCL) for DLCround-PT-12b-LTLCardinality-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 690072
[[35mlola[0m][I] fired transitions : 748450
[[35mlola[0m][I] time used : 18
[[35mlola[0m][I] memory pages used : 7
[[35mlola[0m][I] LAUNCH task # 50 (type EXCL) for 49 DLCround-PT-12b-LTLCardinality-15
[[35mlola[0m][I] time limit : 817 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 50 (type EXCL) for DLCround-PT-12b-LTLCardinality-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 135
[[35mlola[0m][I] fired transitions : 135
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 41 (type EXCL) for 40 DLCround-PT-12b-LTLCardinality-12
[[35mlola[0m][I] time limit : 1090 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 2/1090 1/2000 DLCround-PT-12b-LTLCardinality-12 55889 m, 11177 m/sec, 59244 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 332 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 7/1090 3/2000 DLCround-PT-12b-LTLCardinality-12 248609 m, 38544 m/sec, 264749 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 337 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 12/1090 5/2000 DLCround-PT-12b-LTLCardinality-12 447659 m, 39810 m/sec, 479547 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 342 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 17/1090 7/2000 DLCround-PT-12b-LTLCardinality-12 643740 m, 39216 m/sec, 695402 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 347 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 22/1090 9/2000 DLCround-PT-12b-LTLCardinality-12 838758 m, 39003 m/sec, 912272 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 352 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 27/1090 11/2000 DLCround-PT-12b-LTLCardinality-12 1030598 m, 38368 m/sec, 1128892 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 357 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 32/1090 12/2000 DLCround-PT-12b-LTLCardinality-12 1213306 m, 36541 m/sec, 1326418 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 362 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 37/1090 14/2000 DLCround-PT-12b-LTLCardinality-12 1397486 m, 36836 m/sec, 1535616 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 367 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 42/1090 16/2000 DLCround-PT-12b-LTLCardinality-12 1574355 m, 35373 m/sec, 1750327 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 372 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 47/1090 18/2000 DLCround-PT-12b-LTLCardinality-12 1748495 m, 34828 m/sec, 1950329 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 377 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 52/1090 19/2000 DLCround-PT-12b-LTLCardinality-12 1927355 m, 35772 m/sec, 2158161 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 382 secs. Pages in use: 19
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 57/1090 21/2000 DLCround-PT-12b-LTLCardinality-12 2105045 m, 35538 m/sec, 2367778 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 387 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 62/1090 23/2000 DLCround-PT-12b-LTLCardinality-12 2280929 m, 35176 m/sec, 2576117 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 392 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 67/1090 24/2000 DLCround-PT-12b-LTLCardinality-12 2455232 m, 34860 m/sec, 2788913 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 397 secs. Pages in use: 24
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 72/1090 26/2000 DLCround-PT-12b-LTLCardinality-12 2623706 m, 33694 m/sec, 2990316 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 402 secs. Pages in use: 26
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 77/1090 27/2000 DLCround-PT-12b-LTLCardinality-12 2801730 m, 35604 m/sec, 3199857 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 407 secs. Pages in use: 27
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 82/1090 29/2000 DLCround-PT-12b-LTLCardinality-12 2975053 m, 34664 m/sec, 3411310 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 412 secs. Pages in use: 29
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 87/1090 31/2000 DLCround-PT-12b-LTLCardinality-12 3154994 m, 35988 m/sec, 3618610 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 417 secs. Pages in use: 31
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 92/1090 32/2000 DLCround-PT-12b-LTLCardinality-12 3328389 m, 34679 m/sec, 3830145 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 422 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 97/1090 34/2000 DLCround-PT-12b-LTLCardinality-12 3504991 m, 35320 m/sec, 4038984 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 427 secs. Pages in use: 34
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 102/1090 36/2000 DLCround-PT-12b-LTLCardinality-12 3677174 m, 34436 m/sec, 4250173 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 432 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 107/1090 37/2000 DLCround-PT-12b-LTLCardinality-12 3850420 m, 34649 m/sec, 4461859 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 437 secs. Pages in use: 37
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 112/1090 39/2000 DLCround-PT-12b-LTLCardinality-12 4032283 m, 36372 m/sec, 4674415 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 442 secs. Pages in use: 39
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 117/1090 41/2000 DLCround-PT-12b-LTLCardinality-12 4209526 m, 35448 m/sec, 4888191 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 447 secs. Pages in use: 41
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 122/1090 42/2000 DLCround-PT-12b-LTLCardinality-12 4379226 m, 33940 m/sec, 5103448 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 452 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 127/1090 44/2000 DLCround-PT-12b-LTLCardinality-12 4547342 m, 33623 m/sec, 5306662 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 457 secs. Pages in use: 44
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 132/1090 46/2000 DLCround-PT-12b-LTLCardinality-12 4724466 m, 35424 m/sec, 5521637 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 462 secs. Pages in use: 46
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 137/1090 47/2000 DLCround-PT-12b-LTLCardinality-12 4906275 m, 36361 m/sec, 5733662 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 467 secs. Pages in use: 47
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 142/1090 49/2000 DLCround-PT-12b-LTLCardinality-12 5087329 m, 36210 m/sec, 5945988 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 472 secs. Pages in use: 49
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 147/1090 51/2000 DLCround-PT-12b-LTLCardinality-12 5268654 m, 36265 m/sec, 6156669 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 477 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 152/1090 52/2000 DLCround-PT-12b-LTLCardinality-12 5443477 m, 34964 m/sec, 6371568 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 482 secs. Pages in use: 52
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 157/1090 54/2000 DLCround-PT-12b-LTLCardinality-12 5619537 m, 35212 m/sec, 6586998 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 487 secs. Pages in use: 54
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 162/1090 56/2000 DLCround-PT-12b-LTLCardinality-12 5800239 m, 36140 m/sec, 6799927 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 492 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 167/1090 57/2000 DLCround-PT-12b-LTLCardinality-12 5977382 m, 35428 m/sec, 7013705 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 497 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 172/1090 59/2000 DLCround-PT-12b-LTLCardinality-12 6149196 m, 34362 m/sec, 7231203 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 502 secs. Pages in use: 59
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 177/1090 61/2000 DLCround-PT-12b-LTLCardinality-12 6318651 m, 33891 m/sec, 7435919 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 507 secs. Pages in use: 61
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 182/1090 62/2000 DLCround-PT-12b-LTLCardinality-12 6495172 m, 35304 m/sec, 7650233 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 512 secs. Pages in use: 62
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 187/1090 64/2000 DLCround-PT-12b-LTLCardinality-12 6675723 m, 36110 m/sec, 7860927 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 517 secs. Pages in use: 64
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 192/1090 66/2000 DLCround-PT-12b-LTLCardinality-12 6856657 m, 36186 m/sec, 8071874 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 522 secs. Pages in use: 66
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 197/1090 67/2000 DLCround-PT-12b-LTLCardinality-12 7036707 m, 36010 m/sec, 8282430 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 527 secs. Pages in use: 67
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 202/1090 69/2000 DLCround-PT-12b-LTLCardinality-12 7211740 m, 35006 m/sec, 8496895 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 532 secs. Pages in use: 69
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 207/1090 71/2000 DLCround-PT-12b-LTLCardinality-12 7387913 m, 35234 m/sec, 8710616 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 537 secs. Pages in use: 71
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 212/1090 72/2000 DLCround-PT-12b-LTLCardinality-12 7566347 m, 35686 m/sec, 8923192 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 542 secs. Pages in use: 72
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 217/1090 74/2000 DLCround-PT-12b-LTLCardinality-12 7742474 m, 35225 m/sec, 9136339 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 547 secs. Pages in use: 74
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 222/1090 76/2000 DLCround-PT-12b-LTLCardinality-12 7913547 m, 34214 m/sec, 9353066 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 552 secs. Pages in use: 76
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 227/1090 77/2000 DLCround-PT-12b-LTLCardinality-12 8090665 m, 35423 m/sec, 9565955 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 557 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 232/1090 79/2000 DLCround-PT-12b-LTLCardinality-12 8266874 m, 35241 m/sec, 9780164 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 562 secs. Pages in use: 79
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 237/1090 81/2000 DLCround-PT-12b-LTLCardinality-12 8447543 m, 36133 m/sec, 9990704 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 567 secs. Pages in use: 81
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 242/1090 82/2000 DLCround-PT-12b-LTLCardinality-12 8627049 m, 35901 m/sec, 10199934 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 572 secs. Pages in use: 82
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 247/1090 84/2000 DLCround-PT-12b-LTLCardinality-12 8805398 m, 35669 m/sec, 10408890 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 577 secs. Pages in use: 84
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 252/1090 86/2000 DLCround-PT-12b-LTLCardinality-12 8979964 m, 34913 m/sec, 10622280 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 582 secs. Pages in use: 86
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 257/1090 87/2000 DLCround-PT-12b-LTLCardinality-12 9156833 m, 35373 m/sec, 10835349 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 587 secs. Pages in use: 87
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 262/1090 89/2000 DLCround-PT-12b-LTLCardinality-12 9334106 m, 35454 m/sec, 11048489 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 592 secs. Pages in use: 89
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 267/1090 91/2000 DLCround-PT-12b-LTLCardinality-12 9509211 m, 35021 m/sec, 11260741 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 597 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 272/1090 92/2000 DLCround-PT-12b-LTLCardinality-12 9679251 m, 34008 m/sec, 11475956 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 602 secs. Pages in use: 92
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 277/1090 94/2000 DLCround-PT-12b-LTLCardinality-12 9855382 m, 35226 m/sec, 11688123 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 607 secs. Pages in use: 94
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 282/1090 96/2000 DLCround-PT-12b-LTLCardinality-12 10032460 m, 35415 m/sec, 11901351 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 612 secs. Pages in use: 96
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 287/1090 97/2000 DLCround-PT-12b-LTLCardinality-12 10211010 m, 35710 m/sec, 12111637 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 617 secs. Pages in use: 97
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 292/1090 99/2000 DLCround-PT-12b-LTLCardinality-12 10391807 m, 36159 m/sec, 12319730 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 622 secs. Pages in use: 99
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 297/1090 101/2000 DLCround-PT-12b-LTLCardinality-12 10568793 m, 35397 m/sec, 12529678 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 627 secs. Pages in use: 101
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 302/1090 102/2000 DLCround-PT-12b-LTLCardinality-12 10743717 m, 34984 m/sec, 12741399 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 632 secs. Pages in use: 102
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 307/1090 104/2000 DLCround-PT-12b-LTLCardinality-12 10917937 m, 34844 m/sec, 12953279 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 637 secs. Pages in use: 104
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 312/1090 105/2000 DLCround-PT-12b-LTLCardinality-12 11091376 m, 34687 m/sec, 13161051 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 642 secs. Pages in use: 105
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 317/1090 107/2000 DLCround-PT-12b-LTLCardinality-12 11262509 m, 34226 m/sec, 13368508 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 647 secs. Pages in use: 107
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 322/1090 109/2000 DLCround-PT-12b-LTLCardinality-12 11430189 m, 33536 m/sec, 13580044 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 652 secs. Pages in use: 109
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 327/1090 110/2000 DLCround-PT-12b-LTLCardinality-12 11604264 m, 34815 m/sec, 13788592 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 657 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 332/1090 112/2000 DLCround-PT-12b-LTLCardinality-12 11775895 m, 34326 m/sec, 13998480 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 662 secs. Pages in use: 112
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 337/1090 113/2000 DLCround-PT-12b-LTLCardinality-12 11947169 m, 34254 m/sec, 14200960 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 667 secs. Pages in use: 113
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 342/1090 115/2000 DLCround-PT-12b-LTLCardinality-12 12114432 m, 33452 m/sec, 14394003 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 672 secs. Pages in use: 115
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 347/1090 116/2000 DLCround-PT-12b-LTLCardinality-12 12270797 m, 31273 m/sec, 14577047 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 677 secs. Pages in use: 116
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 352/1090 118/2000 DLCround-PT-12b-LTLCardinality-12 12440285 m, 33897 m/sec, 14778088 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 682 secs. Pages in use: 118
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 357/1090 120/2000 DLCround-PT-12b-LTLCardinality-12 12610030 m, 33949 m/sec, 14985728 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 687 secs. Pages in use: 120
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 362/1090 121/2000 DLCround-PT-12b-LTLCardinality-12 12778322 m, 33658 m/sec, 15191600 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 692 secs. Pages in use: 121
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 367/1090 123/2000 DLCround-PT-12b-LTLCardinality-12 12948493 m, 34034 m/sec, 15395713 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 697 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 372/1090 124/2000 DLCround-PT-12b-LTLCardinality-12 13112415 m, 32784 m/sec, 15606123 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 702 secs. Pages in use: 124
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 377/1090 126/2000 DLCround-PT-12b-LTLCardinality-12 13285605 m, 34638 m/sec, 15811382 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 707 secs. Pages in use: 126
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 382/1090 128/2000 DLCround-PT-12b-LTLCardinality-12 13457862 m, 34451 m/sec, 16020053 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 712 secs. Pages in use: 128
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 387/1090 129/2000 DLCround-PT-12b-LTLCardinality-12 13633628 m, 35153 m/sec, 16228612 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 717 secs. Pages in use: 129
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 392/1090 131/2000 DLCround-PT-12b-LTLCardinality-12 13805516 m, 34377 m/sec, 16429587 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 722 secs. Pages in use: 131
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 397/1090 132/2000 DLCround-PT-12b-LTLCardinality-12 13972776 m, 33452 m/sec, 16623758 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 727 secs. Pages in use: 132
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 402/1090 134/2000 DLCround-PT-12b-LTLCardinality-12 14136893 m, 32823 m/sec, 16819686 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 732 secs. Pages in use: 134
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 407/1090 135/2000 DLCround-PT-12b-LTLCardinality-12 14299270 m, 32475 m/sec, 17018017 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 737 secs. Pages in use: 135
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 412/1090 137/2000 DLCround-PT-12b-LTLCardinality-12 14463416 m, 32829 m/sec, 17214772 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 742 secs. Pages in use: 137
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 417/1090 139/2000 DLCround-PT-12b-LTLCardinality-12 14638364 m, 34989 m/sec, 17424195 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 747 secs. Pages in use: 139
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 422/1090 140/2000 DLCround-PT-12b-LTLCardinality-12 14810952 m, 34517 m/sec, 17634402 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 752 secs. Pages in use: 140
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 427/1090 142/2000 DLCround-PT-12b-LTLCardinality-12 14978602 m, 33530 m/sec, 17846583 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 757 secs. Pages in use: 142
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 432/1090 143/2000 DLCround-PT-12b-LTLCardinality-12 15153637 m, 35007 m/sec, 18054559 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 762 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 437/1090 145/2000 DLCround-PT-12b-LTLCardinality-12 15326750 m, 34622 m/sec, 18267199 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 767 secs. Pages in use: 145
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 442/1090 147/2000 DLCround-PT-12b-LTLCardinality-12 15502489 m, 35147 m/sec, 18473250 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 772 secs. Pages in use: 147
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 447/1090 148/2000 DLCround-PT-12b-LTLCardinality-12 15678815 m, 35265 m/sec, 18677727 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 777 secs. Pages in use: 148
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 452/1090 150/2000 DLCround-PT-12b-LTLCardinality-12 15852928 m, 34822 m/sec, 18882109 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 782 secs. Pages in use: 150
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 457/1090 152/2000 DLCround-PT-12b-LTLCardinality-12 16023742 m, 34162 m/sec, 19087843 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 787 secs. Pages in use: 152
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 462/1090 153/2000 DLCround-PT-12b-LTLCardinality-12 16195303 m, 34312 m/sec, 19295418 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 792 secs. Pages in use: 153
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 467/1090 155/2000 DLCround-PT-12b-LTLCardinality-12 16368132 m, 34565 m/sec, 19504084 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 797 secs. Pages in use: 155
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 472/1090 156/2000 DLCround-PT-12b-LTLCardinality-12 16538836 m, 34140 m/sec, 19711454 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 802 secs. Pages in use: 156
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 477/1090 158/2000 DLCround-PT-12b-LTLCardinality-12 16705464 m, 33325 m/sec, 19921346 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 807 secs. Pages in use: 158
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 482/1090 160/2000 DLCround-PT-12b-LTLCardinality-12 16877539 m, 34415 m/sec, 20127737 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 812 secs. Pages in use: 160
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 487/1090 161/2000 DLCround-PT-12b-LTLCardinality-12 17048091 m, 34110 m/sec, 20337143 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 817 secs. Pages in use: 161
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 492/1090 163/2000 DLCround-PT-12b-LTLCardinality-12 17224377 m, 35257 m/sec, 20541623 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 822 secs. Pages in use: 163
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 497/1090 164/2000 DLCround-PT-12b-LTLCardinality-12 17396537 m, 34432 m/sec, 20746374 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 827 secs. Pages in use: 164
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 502/1090 166/2000 DLCround-PT-12b-LTLCardinality-12 17569242 m, 34541 m/sec, 20947773 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 832 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 507/1090 168/2000 DLCround-PT-12b-LTLCardinality-12 17741554 m, 34462 m/sec, 21151370 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 837 secs. Pages in use: 168
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 512/1090 169/2000 DLCround-PT-12b-LTLCardinality-12 17910506 m, 33790 m/sec, 21357386 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 842 secs. Pages in use: 169
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 517/1090 171/2000 DLCround-PT-12b-LTLCardinality-12 18079707 m, 33840 m/sec, 21564754 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 847 secs. Pages in use: 171
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 522/1090 172/2000 DLCround-PT-12b-LTLCardinality-12 18251573 m, 34373 m/sec, 21770178 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 852 secs. Pages in use: 172
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 527/1090 174/2000 DLCround-PT-12b-LTLCardinality-12 18414323 m, 32550 m/sec, 21981022 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 857 secs. Pages in use: 174
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 532/1090 175/2000 DLCround-PT-12b-LTLCardinality-12 18587953 m, 34726 m/sec, 22185993 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 862 secs. Pages in use: 175
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 537/1090 177/2000 DLCround-PT-12b-LTLCardinality-12 18758741 m, 34157 m/sec, 22393431 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 867 secs. Pages in use: 177
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 542/1090 179/2000 DLCround-PT-12b-LTLCardinality-12 18933016 m, 34855 m/sec, 22600748 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 872 secs. Pages in use: 179
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 547/1090 180/2000 DLCround-PT-12b-LTLCardinality-12 19114360 m, 36268 m/sec, 22810831 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 877 secs. Pages in use: 180
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 552/1090 182/2000 DLCround-PT-12b-LTLCardinality-12 19295243 m, 36176 m/sec, 23024213 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 882 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 557/1090 184/2000 DLCround-PT-12b-LTLCardinality-12 19476128 m, 36177 m/sec, 23236265 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 887 secs. Pages in use: 184
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 562/1090 186/2000 DLCround-PT-12b-LTLCardinality-12 19657233 m, 36221 m/sec, 23450014 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 892 secs. Pages in use: 186
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 567/1090 187/2000 DLCround-PT-12b-LTLCardinality-12 19836299 m, 35813 m/sec, 23664142 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 897 secs. Pages in use: 187
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 572/1090 189/2000 DLCround-PT-12b-LTLCardinality-12 20010104 m, 34761 m/sec, 23879483 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 902 secs. Pages in use: 189
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 577/1090 191/2000 DLCround-PT-12b-LTLCardinality-12 20194061 m, 36791 m/sec, 24088551 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 907 secs. Pages in use: 191
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 582/1090 192/2000 DLCround-PT-12b-LTLCardinality-12 20370860 m, 35359 m/sec, 24299775 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 912 secs. Pages in use: 192
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 587/1090 194/2000 DLCround-PT-12b-LTLCardinality-12 20550881 m, 36004 m/sec, 24511776 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 917 secs. Pages in use: 194
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 592/1090 196/2000 DLCround-PT-12b-LTLCardinality-12 20731293 m, 36082 m/sec, 24724931 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 922 secs. Pages in use: 196
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 597/1090 198/2000 DLCround-PT-12b-LTLCardinality-12 20910274 m, 35796 m/sec, 24937010 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 927 secs. Pages in use: 198
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 602/1090 200/2000 DLCround-PT-12b-LTLCardinality-12 21078641 m, 33673 m/sec, 25136263 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 932 secs. Pages in use: 200
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 607/1090 202/2000 DLCround-PT-12b-LTLCardinality-12 21247611 m, 33794 m/sec, 25336334 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 937 secs. Pages in use: 202
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 612/1090 204/2000 DLCround-PT-12b-LTLCardinality-12 21422994 m, 35076 m/sec, 25544295 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 942 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 617/1090 206/2000 DLCround-PT-12b-LTLCardinality-12 21596173 m, 34635 m/sec, 25749381 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 947 secs. Pages in use: 206
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 622/1090 207/2000 DLCround-PT-12b-LTLCardinality-12 21769811 m, 34727 m/sec, 25954955 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 952 secs. Pages in use: 207
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 627/1090 209/2000 DLCround-PT-12b-LTLCardinality-12 21943323 m, 34702 m/sec, 26160259 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 957 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 632/1090 210/2000 DLCround-PT-12b-LTLCardinality-12 22116465 m, 34628 m/sec, 26365220 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 962 secs. Pages in use: 210
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 637/1090 212/2000 DLCround-PT-12b-LTLCardinality-12 22289125 m, 34532 m/sec, 26569622 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 967 secs. Pages in use: 212
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 642/1090 214/2000 DLCround-PT-12b-LTLCardinality-12 22463614 m, 34897 m/sec, 26775816 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 972 secs. Pages in use: 214
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 647/1090 216/2000 DLCround-PT-12b-LTLCardinality-12 22638777 m, 35032 m/sec, 26983046 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 977 secs. Pages in use: 216
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 652/1090 218/2000 DLCround-PT-12b-LTLCardinality-12 22813778 m, 35000 m/sec, 27189848 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 982 secs. Pages in use: 218
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 657/1090 219/2000 DLCround-PT-12b-LTLCardinality-12 22985656 m, 34375 m/sec, 27393885 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 987 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 662/1090 221/2000 DLCround-PT-12b-LTLCardinality-12 23158211 m, 34511 m/sec, 27598060 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 992 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 667/1090 223/2000 DLCround-PT-12b-LTLCardinality-12 23330948 m, 34547 m/sec, 27803573 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 997 secs. Pages in use: 223
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 672/1090 225/2000 DLCround-PT-12b-LTLCardinality-12 23504452 m, 34700 m/sec, 28009163 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1002 secs. Pages in use: 225
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 677/1090 226/2000 DLCround-PT-12b-LTLCardinality-12 23675789 m, 34267 m/sec, 28212548 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1007 secs. Pages in use: 226
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 682/1090 228/2000 DLCround-PT-12b-LTLCardinality-12 23846646 m, 34171 m/sec, 28414846 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1012 secs. Pages in use: 228
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 687/1090 229/2000 DLCround-PT-12b-LTLCardinality-12 24018159 m, 34302 m/sec, 28617795 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1017 secs. Pages in use: 229
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 692/1090 231/2000 DLCround-PT-12b-LTLCardinality-12 24191512 m, 34670 m/sec, 28822853 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1022 secs. Pages in use: 231
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 697/1090 232/2000 DLCround-PT-12b-LTLCardinality-12 24365481 m, 34793 m/sec, 29029595 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1027 secs. Pages in use: 232
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 702/1090 234/2000 DLCround-PT-12b-LTLCardinality-12 24543039 m, 35511 m/sec, 29239725 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1032 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 707/1090 237/2000 DLCround-PT-12b-LTLCardinality-12 24721788 m, 35749 m/sec, 29451637 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1037 secs. Pages in use: 237
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 712/1090 239/2000 DLCround-PT-12b-LTLCardinality-12 24900815 m, 35805 m/sec, 29663306 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1042 secs. Pages in use: 239
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 717/1090 241/2000 DLCround-PT-12b-LTLCardinality-12 25077741 m, 35385 m/sec, 29873379 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1047 secs. Pages in use: 241
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 722/1090 243/2000 DLCround-PT-12b-LTLCardinality-12 25255251 m, 35502 m/sec, 30084118 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1052 secs. Pages in use: 243
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 727/1090 245/2000 DLCround-PT-12b-LTLCardinality-12 25434527 m, 35855 m/sec, 30295955 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1057 secs. Pages in use: 245
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 732/1090 247/2000 DLCround-PT-12b-LTLCardinality-12 25610963 m, 35287 m/sec, 30504707 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1062 secs. Pages in use: 247
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 737/1090 249/2000 DLCround-PT-12b-LTLCardinality-12 25785642 m, 34935 m/sec, 30711862 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1067 secs. Pages in use: 249
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 742/1090 251/2000 DLCround-PT-12b-LTLCardinality-12 25962436 m, 35358 m/sec, 30921011 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1072 secs. Pages in use: 251
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 747/1090 253/2000 DLCround-PT-12b-LTLCardinality-12 26138490 m, 35210 m/sec, 31129360 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1077 secs. Pages in use: 253
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 752/1090 255/2000 DLCround-PT-12b-LTLCardinality-12 26314851 m, 35272 m/sec, 31338469 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1082 secs. Pages in use: 255
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 757/1090 257/2000 DLCround-PT-12b-LTLCardinality-12 26491424 m, 35314 m/sec, 31547388 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1087 secs. Pages in use: 257
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 762/1090 259/2000 DLCround-PT-12b-LTLCardinality-12 26667248 m, 35164 m/sec, 31755762 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1092 secs. Pages in use: 259
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 767/1090 261/2000 DLCround-PT-12b-LTLCardinality-12 26842002 m, 34950 m/sec, 31963561 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1097 secs. Pages in use: 261
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 772/1090 263/2000 DLCround-PT-12b-LTLCardinality-12 27016703 m, 34940 m/sec, 32170983 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1102 secs. Pages in use: 263
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 777/1090 265/2000 DLCround-PT-12b-LTLCardinality-12 27193567 m, 35372 m/sec, 32380002 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1107 secs. Pages in use: 265
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 782/1090 267/2000 DLCround-PT-12b-LTLCardinality-12 27369792 m, 35245 m/sec, 32588576 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1112 secs. Pages in use: 267
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 787/1090 269/2000 DLCround-PT-12b-LTLCardinality-12 27545170 m, 35075 m/sec, 32796045 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1117 secs. Pages in use: 269
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 792/1090 270/2000 DLCround-PT-12b-LTLCardinality-12 27719659 m, 34897 m/sec, 33002996 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1122 secs. Pages in use: 270
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 797/1090 272/2000 DLCround-PT-12b-LTLCardinality-12 27894047 m, 34877 m/sec, 33209625 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1127 secs. Pages in use: 272
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 802/1090 274/2000 DLCround-PT-12b-LTLCardinality-12 28067796 m, 34749 m/sec, 33415890 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1132 secs. Pages in use: 274
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 807/1090 276/2000 DLCround-PT-12b-LTLCardinality-12 28242709 m, 34982 m/sec, 33622593 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1137 secs. Pages in use: 276
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 812/1090 277/2000 DLCround-PT-12b-LTLCardinality-12 28416979 m, 34854 m/sec, 33829220 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1142 secs. Pages in use: 277
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 817/1090 279/2000 DLCround-PT-12b-LTLCardinality-12 28590877 m, 34779 m/sec, 34034979 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1147 secs. Pages in use: 279
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 822/1090 281/2000 DLCround-PT-12b-LTLCardinality-12 28764385 m, 34701 m/sec, 34240358 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1152 secs. Pages in use: 281
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 827/1090 282/2000 DLCround-PT-12b-LTLCardinality-12 28938020 m, 34727 m/sec, 34445806 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1157 secs. Pages in use: 282
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 832/1090 284/2000 DLCround-PT-12b-LTLCardinality-12 29112256 m, 34847 m/sec, 34652256 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1162 secs. Pages in use: 284
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 837/1090 286/2000 DLCround-PT-12b-LTLCardinality-12 29286819 m, 34912 m/sec, 34858796 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1167 secs. Pages in use: 286
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 842/1090 288/2000 DLCround-PT-12b-LTLCardinality-12 29460130 m, 34662 m/sec, 35063991 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1172 secs. Pages in use: 288
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 847/1090 289/2000 DLCround-PT-12b-LTLCardinality-12 29632456 m, 34465 m/sec, 35268613 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1177 secs. Pages in use: 289
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 852/1090 291/2000 DLCround-PT-12b-LTLCardinality-12 29805512 m, 34611 m/sec, 35473711 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1182 secs. Pages in use: 291
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 857/1090 293/2000 DLCround-PT-12b-LTLCardinality-12 29979953 m, 34888 m/sec, 35679999 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1187 secs. Pages in use: 293
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 862/1090 295/2000 DLCround-PT-12b-LTLCardinality-12 30153408 m, 34691 m/sec, 35885635 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1192 secs. Pages in use: 295
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 867/1090 296/2000 DLCround-PT-12b-LTLCardinality-12 30330116 m, 35341 m/sec, 36094752 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1197 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 872/1090 298/2000 DLCround-PT-12b-LTLCardinality-12 30506881 m, 35353 m/sec, 36303563 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1202 secs. Pages in use: 298
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 877/1090 300/2000 DLCround-PT-12b-LTLCardinality-12 30681688 m, 34961 m/sec, 36512131 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1207 secs. Pages in use: 300
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 882/1090 302/2000 DLCround-PT-12b-LTLCardinality-12 30855947 m, 34851 m/sec, 36718481 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1212 secs. Pages in use: 302
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 887/1090 303/2000 DLCround-PT-12b-LTLCardinality-12 31029984 m, 34807 m/sec, 36924258 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1217 secs. Pages in use: 303
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 892/1090 305/2000 DLCround-PT-12b-LTLCardinality-12 31204216 m, 34846 m/sec, 37130162 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1222 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 897/1090 307/2000 DLCround-PT-12b-LTLCardinality-12 31380891 m, 35335 m/sec, 37339624 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1227 secs. Pages in use: 307
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 902/1090 309/2000 DLCround-PT-12b-LTLCardinality-12 31558845 m, 35590 m/sec, 37550096 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1232 secs. Pages in use: 309
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 907/1090 311/2000 DLCround-PT-12b-LTLCardinality-12 31734577 m, 35146 m/sec, 37757962 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1237 secs. Pages in use: 311
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 912/1090 313/2000 DLCround-PT-12b-LTLCardinality-12 31909594 m, 35003 m/sec, 37965170 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1242 secs. Pages in use: 313
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 917/1090 314/2000 DLCround-PT-12b-LTLCardinality-12 32085206 m, 35122 m/sec, 38173094 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1247 secs. Pages in use: 314
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 922/1090 316/2000 DLCround-PT-12b-LTLCardinality-12 32260237 m, 35006 m/sec, 38380214 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1252 secs. Pages in use: 316
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 927/1090 318/2000 DLCround-PT-12b-LTLCardinality-12 32435154 m, 34983 m/sec, 38588193 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1257 secs. Pages in use: 318
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 932/1090 319/2000 DLCround-PT-12b-LTLCardinality-12 32610345 m, 35038 m/sec, 38796134 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1262 secs. Pages in use: 319
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 937/1090 321/2000 DLCround-PT-12b-LTLCardinality-12 32784690 m, 34869 m/sec, 39002762 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1267 secs. Pages in use: 321
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 942/1090 323/2000 DLCround-PT-12b-LTLCardinality-12 32958775 m, 34817 m/sec, 39208853 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1272 secs. Pages in use: 323
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 947/1090 324/2000 DLCround-PT-12b-LTLCardinality-12 33133414 m, 34927 m/sec, 39415523 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1277 secs. Pages in use: 324
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 952/1090 326/2000 DLCround-PT-12b-LTLCardinality-12 33309329 m, 35183 m/sec, 39623701 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1282 secs. Pages in use: 326
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 957/1090 328/2000 DLCround-PT-12b-LTLCardinality-12 33488092 m, 35752 m/sec, 39834942 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1287 secs. Pages in use: 328
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 962/1090 330/2000 DLCround-PT-12b-LTLCardinality-12 33665320 m, 35445 m/sec, 40044715 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1292 secs. Pages in use: 330
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 967/1090 332/2000 DLCround-PT-12b-LTLCardinality-12 33843750 m, 35686 m/sec, 40255800 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1297 secs. Pages in use: 332
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 972/1090 334/2000 DLCround-PT-12b-LTLCardinality-12 34020955 m, 35441 m/sec, 40465590 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1302 secs. Pages in use: 334
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 977/1090 336/2000 DLCround-PT-12b-LTLCardinality-12 34197589 m, 35326 m/sec, 40674685 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1307 secs. Pages in use: 336
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 982/1090 338/2000 DLCround-PT-12b-LTLCardinality-12 34375291 m, 35540 m/sec, 40884735 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1312 secs. Pages in use: 338
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 987/1090 340/2000 DLCround-PT-12b-LTLCardinality-12 34553344 m, 35610 m/sec, 41095424 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1317 secs. Pages in use: 340
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 992/1090 342/2000 DLCround-PT-12b-LTLCardinality-12 34731562 m, 35643 m/sec, 41306064 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1322 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 997/1090 344/2000 DLCround-PT-12b-LTLCardinality-12 34909284 m, 35544 m/sec, 41516322 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1327 secs. Pages in use: 344
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 1002/1090 346/2000 DLCround-PT-12b-LTLCardinality-12 35086710 m, 35485 m/sec, 41726543 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1332 secs. Pages in use: 346
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 1007/1090 349/2000 DLCround-PT-12b-LTLCardinality-12 35262641 m, 35186 m/sec, 41935148 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1337 secs. Pages in use: 349
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 1012/1090 351/2000 DLCround-PT-12b-LTLCardinality-12 35438636 m, 35199 m/sec, 42143474 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1342 secs. Pages in use: 351
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 1017/1090 352/2000 DLCround-PT-12b-LTLCardinality-12 35615006 m, 35274 m/sec, 42352184 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1347 secs. Pages in use: 352
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 1022/1090 355/2000 DLCround-PT-12b-LTLCardinality-12 35791695 m, 35337 m/sec, 42561289 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1352 secs. Pages in use: 355
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 1027/1090 357/2000 DLCround-PT-12b-LTLCardinality-12 35967120 m, 35085 m/sec, 42768889 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1357 secs. Pages in use: 357
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 1032/1090 358/2000 DLCround-PT-12b-LTLCardinality-12 36141266 m, 34829 m/sec, 42975276 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1362 secs. Pages in use: 358
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 1037/1090 360/2000 DLCround-PT-12b-LTLCardinality-12 36317525 m, 35251 m/sec, 43184017 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1367 secs. Pages in use: 360
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 1042/1090 363/2000 DLCround-PT-12b-LTLCardinality-12 36493760 m, 35247 m/sec, 43392869 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1372 secs. Pages in use: 363
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 1047/1090 365/2000 DLCround-PT-12b-LTLCardinality-12 36670550 m, 35358 m/sec, 43602016 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1377 secs. Pages in use: 365
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 1052/1090 366/2000 DLCround-PT-12b-LTLCardinality-12 36846863 m, 35262 m/sec, 43810776 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1382 secs. Pages in use: 366
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 1057/1090 368/2000 DLCround-PT-12b-LTLCardinality-12 37021577 m, 34942 m/sec, 44017873 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1387 secs. Pages in use: 368
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 1062/1090 370/2000 DLCround-PT-12b-LTLCardinality-12 37196301 m, 34944 m/sec, 44225941 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1392 secs. Pages in use: 370
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 1067/1090 372/2000 DLCround-PT-12b-LTLCardinality-12 37370389 m, 34817 m/sec, 44431902 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1397 secs. Pages in use: 372
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 1072/1090 374/2000 DLCround-PT-12b-LTLCardinality-12 37543445 m, 34611 m/sec, 44637793 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1402 secs. Pages in use: 374
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 1077/1090 376/2000 DLCround-PT-12b-LTLCardinality-12 37718475 m, 35006 m/sec, 44845061 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1407 secs. Pages in use: 376
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 1082/1090 378/2000 DLCround-PT-12b-LTLCardinality-12 37896105 m, 35526 m/sec, 45055287 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1412 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 1087/1090 380/2000 DLCround-PT-12b-LTLCardinality-12 38073099 m, 35398 m/sec, 45264954 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1417 secs. Pages in use: 380
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 41 (type EXCL) for DLCround-PT-12b-LTLCardinality-12 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1422 secs. Pages in use: 382
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 35 (type EXCL) for 34 DLCround-PT-12b-LTLCardinality-10
[[35mlola[0m][I] time limit : 1089 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 41 (type EXCL) for 40 DLCround-PT-12b-LTLCardinality-12
[[35mlola[0m][I] time limit : 2178 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 35 (type EXCL) for DLCround-PT-12b-LTLCardinality-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 5/1089 2/5 DLCround-PT-12b-LTLCardinality-12 182332 m, -7578153 m/sec, 193862 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1427 secs. Pages in use: 384
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 LTL EXCL 10/1089 4/5 DLCround-PT-12b-LTLCardinality-12 380623 m, 39658 m/sec, 408420 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1432 secs. Pages in use: 386
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 41 (type EXCL) for DLCround-PT-12b-LTLCardinality-12 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-00: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1437 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 DLCround-PT-12b-LTLCardinality-00
[[35mlola[0m][I] time limit : 2163 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for DLCround-PT-12b-LTLCardinality-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 135
[[35mlola[0m][I] fired transitions : 135
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1442 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1447 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1452 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1457 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1462 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1467 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1472 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1477 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1482 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1487 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1492 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1497 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1502 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1507 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1512 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1517 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1522 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1527 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1532 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1537 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1542 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1547 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1552 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1557 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1562 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1567 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1572 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1577 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1582 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1587 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1592 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1597 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1602 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1607 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1612 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1617 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1622 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1627 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1632 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1637 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1642 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1647 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1652 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1657 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1662 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1667 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1672 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1677 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1682 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1687 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1692 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1697 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1702 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1707 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1712 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1717 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1722 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1727 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1732 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1737 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1742 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1747 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1752 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1757 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1762 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1767 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1772 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1777 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1782 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1787 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1792 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1797 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1802 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1807 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1812 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1817 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1822 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1827 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1832 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-00: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-09: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-LTLCardinality-12: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1837 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-12b"
export BK_EXAMINATION="LTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is DLCround-PT-12b, examination is LTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r115-smll-171624276700267"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-12b.tgz
mv DLCround-PT-12b execution
cd execution
if [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "UpperBounds" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] || [ "LTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;