About the Execution of LoLA for DLCround-PT-12b
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16207.228 | 1311235.00 | 1394369.00 | 6670.90 | ??F??TFT???T???? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r115-smll-171624276700266.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is DLCround-PT-12b, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r115-smll-171624276700266
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 2.3M
-rw-r--r-- 1 mcc users 6.6K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 68K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.1K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 56K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.3K Apr 22 14:38 LTLCardinality.txt
-rw-r--r-- 1 mcc users 22K Apr 22 14:38 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K May 19 07:16 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K May 19 18:11 LTLFireability.xml
-rw-r--r-- 1 mcc users 7.5K Apr 13 12:12 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 70K Apr 13 12:12 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.5K Apr 13 12:12 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 82K Apr 13 12:12 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 22 14:38 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Apr 22 14:38 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 4 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 1.9M May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-12b-CTLFireability-2024-00
FORMULA_NAME DLCround-PT-12b-CTLFireability-2024-01
FORMULA_NAME DLCround-PT-12b-CTLFireability-2024-02
FORMULA_NAME DLCround-PT-12b-CTLFireability-2024-03
FORMULA_NAME DLCround-PT-12b-CTLFireability-2024-04
FORMULA_NAME DLCround-PT-12b-CTLFireability-2024-05
FORMULA_NAME DLCround-PT-12b-CTLFireability-2024-06
FORMULA_NAME DLCround-PT-12b-CTLFireability-2024-07
FORMULA_NAME DLCround-PT-12b-CTLFireability-2024-08
FORMULA_NAME DLCround-PT-12b-CTLFireability-2024-09
FORMULA_NAME DLCround-PT-12b-CTLFireability-2024-10
FORMULA_NAME DLCround-PT-12b-CTLFireability-2024-11
FORMULA_NAME DLCround-PT-12b-CTLFireability-2023-12
FORMULA_NAME DLCround-PT-12b-CTLFireability-2023-13
FORMULA_NAME DLCround-PT-12b-CTLFireability-2023-14
FORMULA_NAME DLCround-PT-12b-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717101058450
FORMULA DLCround-PT-12b-CTLFireability-2024-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-12b-CTLFireability-2024-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-12b-CTLFireability-2024-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-12b-CTLFireability-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-12b-CTLFireability-2024-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717102369685
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-02: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-05: EFEG 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-06: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-07: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 86 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-02: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-05: EFEG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-06: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-07: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 91 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-02: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-05: EFEG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-06: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-07: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 96 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 57 (type EXCL) for 46 DLCround-PT-12b-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 152 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 60 (type EQUN) for 46 DLCround-PT-12b-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 57 (type EXCL) for DLCround-PT-12b-CTLFireability-2023-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 60 (type EQUN) for DLCround-PT-12b-CTLFireability-2023-14 (obsolete)
[[35mlola[0m][I] FINISHED task # 60 (type EQUN) for DLCround-PT-12b-CTLFireability-2023-14
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-02: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-05: EFEG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-06: CONJ 1 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-07: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 101 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 38 (type EXCL) for 37 DLCround-PT-12b-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 174 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-02: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-05: EFEG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-06: CONJ 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-07: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 0/183 0/2000 DLCround-PT-12b-CTLFireability-2024-11 --
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 106 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 68 (type EQUN) for 15 DLCround-PT-12b-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 70 (type EQUN) for 15 DLCround-PT-12b-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 38 (type EXCL) for DLCround-PT-12b-CTLFireability-2024-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 4
[[35mlola[0m][I] time used : 4
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 77 (type EXCL) for 18 DLCround-PT-12b-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 183 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 73 (type FNDP) for 18 DLCround-PT-12b-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 77 (type EXCL) for DLCround-PT-12b-CTLFireability-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 3
[[35mlola[0m][I] fired transitions : 2
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 73 (type FNDP) for DLCround-PT-12b-CTLFireability-2024-06 (obsolete)
[[35mlola[0m][I] LAUNCH task # 75 (type EXCL) for 25 DLCround-PT-12b-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 205 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 62 (type FNDP) for 6 DLCround-PT-12b-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 73 (type FNDP) for DLCround-PT-12b-CTLFireability-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] FINISHED task # 62 (type FNDP) for DLCround-PT-12b-CTLFireability-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] LAUNCH task # 65 (type FNDP) for 25 DLCround-PT-12b-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 65 (type FNDP) for DLCround-PT-12b-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 75 (type EXCL) for DLCround-PT-12b-CTLFireability-2024-07 (obsolete)
[[35mlola[0m][I] LAUNCH task # 63 (type EXCL) for 15 DLCround-PT-12b-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 232 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 63 (type EXCL) for DLCround-PT-12b-CTLFireability-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 261
[[35mlola[0m][I] fired transitions : 261
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 68 (type EQUN) for DLCround-PT-12b-CTLFireability-2024-05 (obsolete)
[[35mlola[0m][W] CANCELED task # 70 (type EQUN) for DLCround-PT-12b-CTLFireability-2024-05 (obsolete)
[[35mlola[0m][I] LAUNCH task # 54 (type EXCL) for 53 DLCround-PT-12b-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 249 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 68 (type EQUN) for DLCround-PT-12b-CTLFireability-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 70 (type EQUN) for DLCround-PT-12b-CTLFireability-2024-05
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 54 (type EXCL) for DLCround-PT-12b-CTLFireability-2023-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 29233
[[35mlola[0m][I] fired transitions : 87361
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 111 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 35 (type EXCL) for 34 DLCround-PT-12b-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 348 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 3/348 1/2000 DLCround-PT-12b-CTLFireability-2024-10 92894 m, 18578 m/sec, 96097 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 116 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 8/348 2/2000 DLCround-PT-12b-CTLFireability-2024-10 241992 m, 29819 m/sec, 250748 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 121 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 13/348 4/2000 DLCround-PT-12b-CTLFireability-2024-10 409005 m, 33402 m/sec, 423930 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 126 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 18/348 5/2000 DLCround-PT-12b-CTLFireability-2024-10 575614 m, 33321 m/sec, 596749 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 131 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 23/348 6/2000 DLCround-PT-12b-CTLFireability-2024-10 740445 m, 32966 m/sec, 770659 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 136 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 28/348 7/2000 DLCround-PT-12b-CTLFireability-2024-10 905079 m, 32926 m/sec, 944243 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 141 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 33/348 8/2000 DLCround-PT-12b-CTLFireability-2024-10 1068860 m, 32756 m/sec, 1117938 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 146 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 38/348 9/2000 DLCround-PT-12b-CTLFireability-2024-10 1232259 m, 32679 m/sec, 1291161 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 151 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 43/348 10/2000 DLCround-PT-12b-CTLFireability-2024-10 1394292 m, 32406 m/sec, 1464586 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 156 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 48/348 12/2000 DLCround-PT-12b-CTLFireability-2024-10 1557355 m, 32612 m/sec, 1636909 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 161 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 53/348 13/2000 DLCround-PT-12b-CTLFireability-2024-10 1718770 m, 32283 m/sec, 1809899 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 166 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 58/348 14/2000 DLCround-PT-12b-CTLFireability-2024-10 1879966 m, 32239 m/sec, 1983453 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 171 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 63/348 15/2000 DLCround-PT-12b-CTLFireability-2024-10 2044806 m, 32968 m/sec, 2154422 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 176 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 68/348 16/2000 DLCround-PT-12b-CTLFireability-2024-10 2207299 m, 32498 m/sec, 2323046 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 181 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 73/348 17/2000 DLCround-PT-12b-CTLFireability-2024-10 2363095 m, 31159 m/sec, 2493000 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 186 secs. Pages in use: 17
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 78/348 18/2000 DLCround-PT-12b-CTLFireability-2024-10 2518867 m, 31154 m/sec, 2661451 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 191 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 83/348 19/2000 DLCround-PT-12b-CTLFireability-2024-10 2671852 m, 30597 m/sec, 2832385 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 196 secs. Pages in use: 19
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 88/348 20/2000 DLCround-PT-12b-CTLFireability-2024-10 2823139 m, 30257 m/sec, 3004093 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 201 secs. Pages in use: 20
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 93/348 21/2000 DLCround-PT-12b-CTLFireability-2024-10 2976000 m, 30572 m/sec, 3172210 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 206 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 98/348 22/2000 DLCround-PT-12b-CTLFireability-2024-10 3129330 m, 30666 m/sec, 3339792 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 211 secs. Pages in use: 22
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 103/348 23/2000 DLCround-PT-12b-CTLFireability-2024-10 3281878 m, 30509 m/sec, 3506382 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 216 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 108/348 24/2000 DLCround-PT-12b-CTLFireability-2024-10 3436238 m, 30872 m/sec, 3674669 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 221 secs. Pages in use: 24
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 113/348 25/2000 DLCround-PT-12b-CTLFireability-2024-10 3589722 m, 30696 m/sec, 3842465 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 226 secs. Pages in use: 25
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 118/348 26/2000 DLCround-PT-12b-CTLFireability-2024-10 3741378 m, 30331 m/sec, 4010048 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 231 secs. Pages in use: 26
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 123/348 27/2000 DLCround-PT-12b-CTLFireability-2024-10 3892040 m, 30132 m/sec, 4178755 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 236 secs. Pages in use: 27
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 128/348 28/2000 DLCround-PT-12b-CTLFireability-2024-10 4044553 m, 30502 m/sec, 4348340 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 241 secs. Pages in use: 28
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 133/348 29/2000 DLCround-PT-12b-CTLFireability-2024-10 4194168 m, 29923 m/sec, 4519818 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 246 secs. Pages in use: 29
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 138/348 31/2000 DLCround-PT-12b-CTLFireability-2024-10 4346466 m, 30459 m/sec, 4687136 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 251 secs. Pages in use: 31
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 143/348 31/2000 DLCround-PT-12b-CTLFireability-2024-10 4493892 m, 29485 m/sec, 4854250 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 256 secs. Pages in use: 31
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 148/348 33/2000 DLCround-PT-12b-CTLFireability-2024-10 4645050 m, 30231 m/sec, 5016613 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 261 secs. Pages in use: 33
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 153/348 33/2000 DLCround-PT-12b-CTLFireability-2024-10 4789663 m, 28922 m/sec, 5179349 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 266 secs. Pages in use: 33
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 158/348 34/2000 DLCround-PT-12b-CTLFireability-2024-10 4936114 m, 29290 m/sec, 5341875 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 271 secs. Pages in use: 34
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 163/348 35/2000 DLCround-PT-12b-CTLFireability-2024-10 5083146 m, 29406 m/sec, 5503826 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 276 secs. Pages in use: 35
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 168/348 36/2000 DLCround-PT-12b-CTLFireability-2024-10 5228090 m, 28988 m/sec, 5666376 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 281 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 173/348 37/2000 DLCround-PT-12b-CTLFireability-2024-10 5379153 m, 30212 m/sec, 5830636 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 286 secs. Pages in use: 37
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 178/348 39/2000 DLCround-PT-12b-CTLFireability-2024-10 5528073 m, 29784 m/sec, 5996309 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 291 secs. Pages in use: 39
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 183/348 39/2000 DLCround-PT-12b-CTLFireability-2024-10 5676138 m, 29613 m/sec, 6163359 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 296 secs. Pages in use: 39
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 188/348 41/2000 DLCround-PT-12b-CTLFireability-2024-10 5824398 m, 29652 m/sec, 6330021 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 301 secs. Pages in use: 41
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 193/348 42/2000 DLCround-PT-12b-CTLFireability-2024-10 5975481 m, 30216 m/sec, 6493759 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 306 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 198/348 43/2000 DLCround-PT-12b-CTLFireability-2024-10 6123862 m, 29676 m/sec, 6659310 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 311 secs. Pages in use: 43
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 203/348 44/2000 DLCround-PT-12b-CTLFireability-2024-10 6272356 m, 29698 m/sec, 6822713 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 316 secs. Pages in use: 44
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 208/348 45/2000 DLCround-PT-12b-CTLFireability-2024-10 6415850 m, 28698 m/sec, 6991417 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 321 secs. Pages in use: 45
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 213/348 46/2000 DLCround-PT-12b-CTLFireability-2024-10 6567707 m, 30371 m/sec, 7155443 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 326 secs. Pages in use: 46
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 218/348 47/2000 DLCround-PT-12b-CTLFireability-2024-10 6707321 m, 27922 m/sec, 7316509 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 331 secs. Pages in use: 47
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 223/348 48/2000 DLCround-PT-12b-CTLFireability-2024-10 6856223 m, 29780 m/sec, 7480857 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 336 secs. Pages in use: 48
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 228/348 49/2000 DLCround-PT-12b-CTLFireability-2024-10 7005799 m, 29915 m/sec, 7645040 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 341 secs. Pages in use: 49
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 233/348 50/2000 DLCround-PT-12b-CTLFireability-2024-10 7151185 m, 29077 m/sec, 7810473 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 346 secs. Pages in use: 50
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 238/348 51/2000 DLCround-PT-12b-CTLFireability-2024-10 7298999 m, 29562 m/sec, 7976119 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 351 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 243/348 51/2000 DLCround-PT-12b-CTLFireability-2024-10 7440942 m, 28388 m/sec, 8147654 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 356 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 248/348 53/2000 DLCround-PT-12b-CTLFireability-2024-10 7590457 m, 29903 m/sec, 8311898 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 361 secs. Pages in use: 53
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 253/348 54/2000 DLCround-PT-12b-CTLFireability-2024-10 7739533 m, 29815 m/sec, 8476766 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 366 secs. Pages in use: 54
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 258/348 54/2000 DLCround-PT-12b-CTLFireability-2024-10 7887354 m, 29564 m/sec, 8641186 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 371 secs. Pages in use: 54
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 263/348 55/2000 DLCround-PT-12b-CTLFireability-2024-10 8032763 m, 29081 m/sec, 8808532 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 376 secs. Pages in use: 55
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 268/348 56/2000 DLCround-PT-12b-CTLFireability-2024-10 8181813 m, 29810 m/sec, 8974816 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 381 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 273/348 58/2000 DLCround-PT-12b-CTLFireability-2024-10 8330968 m, 29831 m/sec, 9137731 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 386 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 278/348 59/2000 DLCround-PT-12b-CTLFireability-2024-10 8479682 m, 29742 m/sec, 9302737 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 391 secs. Pages in use: 59
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 283/348 60/2000 DLCround-PT-12b-CTLFireability-2024-10 8628406 m, 29744 m/sec, 9466277 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 396 secs. Pages in use: 60
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 288/348 61/2000 DLCround-PT-12b-CTLFireability-2024-10 8777675 m, 29853 m/sec, 9627531 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 401 secs. Pages in use: 61
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 293/348 62/2000 DLCround-PT-12b-CTLFireability-2024-10 8925380 m, 29541 m/sec, 9791408 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 406 secs. Pages in use: 62
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 298/348 62/2000 DLCround-PT-12b-CTLFireability-2024-10 9073827 m, 29689 m/sec, 9954577 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 411 secs. Pages in use: 62
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 303/348 64/2000 DLCround-PT-12b-CTLFireability-2024-10 9222248 m, 29684 m/sec, 10118057 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 416 secs. Pages in use: 64
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 308/348 65/2000 DLCround-PT-12b-CTLFireability-2024-10 9370010 m, 29552 m/sec, 10281388 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 421 secs. Pages in use: 65
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 313/348 65/2000 DLCround-PT-12b-CTLFireability-2024-10 9514036 m, 28805 m/sec, 10448557 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 426 secs. Pages in use: 65
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 318/348 66/2000 DLCround-PT-12b-CTLFireability-2024-10 9663552 m, 29903 m/sec, 10612538 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 431 secs. Pages in use: 66
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 323/348 67/2000 DLCround-PT-12b-CTLFireability-2024-10 9808260 m, 28941 m/sec, 10780064 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 436 secs. Pages in use: 67
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 328/348 68/2000 DLCround-PT-12b-CTLFireability-2024-10 9956418 m, 29631 m/sec, 10943677 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 441 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 333/348 70/2000 DLCround-PT-12b-CTLFireability-2024-10 10105682 m, 29852 m/sec, 11106635 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 446 secs. Pages in use: 70
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 338/348 70/2000 DLCround-PT-12b-CTLFireability-2024-10 10251679 m, 29199 m/sec, 11270541 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 451 secs. Pages in use: 70
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 343/348 71/2000 DLCround-PT-12b-CTLFireability-2024-10 10398849 m, 29434 m/sec, 11435238 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 456 secs. Pages in use: 71
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 348/348 72/2000 DLCround-PT-12b-CTLFireability-2024-10 10538423 m, 27914 m/sec, 11605564 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 461 secs. Pages in use: 72
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 35 (type EXCL) for DLCround-PT-12b-CTLFireability-2024-10 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 466 secs. Pages in use: 73
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 51 (type EXCL) for 46 DLCround-PT-12b-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 348 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 35 (type EXCL) for 34 DLCround-PT-12b-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 3134 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 5/3134 1/5 DLCround-PT-12b-CTLFireability-2024-10 129367 m, -2081811 m/sec, 133837 t fired, .
[[35mlola[0m][.] 51 CTL EXCL 5/348 3/2000 DLCround-PT-12b-CTLFireability-2023-14 181081 m, 36216 m/sec, 197410 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 471 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 10/3134 3/5 DLCround-PT-12b-CTLFireability-2024-10 278286 m, 29783 m/sec, 288239 t fired, .
[[35mlola[0m][.] 51 CTL EXCL 10/313 6/2000 DLCround-PT-12b-CTLFireability-2023-14 372250 m, 38233 m/sec, 409907 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 476 secs. Pages in use: 82
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 15/3134 4/5 DLCround-PT-12b-CTLFireability-2024-10 435468 m, 31436 m/sec, 451514 t fired, .
[[35mlola[0m][.] 51 CTL EXCL 15/313 8/2000 DLCround-PT-12b-CTLFireability-2023-14 563720 m, 38294 m/sec, 621877 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 481 secs. Pages in use: 85
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 20/3134 5/5 DLCround-PT-12b-CTLFireability-2024-10 591952 m, 31296 m/sec, 613650 t fired, .
[[35mlola[0m][.] 51 CTL EXCL 20/313 10/2000 DLCround-PT-12b-CTLFireability-2023-14 754727 m, 38201 m/sec, 833534 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 486 secs. Pages in use: 88
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 35 (type EXCL) for DLCround-PT-12b-CTLFireability-2024-10 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 25/313 12/2000 DLCround-PT-12b-CTLFireability-2023-14 947620 m, 38578 m/sec, 1046759 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 491 secs. Pages in use: 90
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 30/348 15/2000 DLCround-PT-12b-CTLFireability-2023-14 1145622 m, 39600 m/sec, 1266360 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 496 secs. Pages in use: 90
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 35/348 17/2000 DLCround-PT-12b-CTLFireability-2023-14 1342219 m, 39319 m/sec, 1485242 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 501 secs. Pages in use: 90
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 40/348 19/2000 DLCround-PT-12b-CTLFireability-2023-14 1540081 m, 39572 m/sec, 1704541 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 506 secs. Pages in use: 92
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 45/348 22/2000 DLCround-PT-12b-CTLFireability-2023-14 1737183 m, 39420 m/sec, 1923664 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 511 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 50/348 24/2000 DLCround-PT-12b-CTLFireability-2023-14 1934099 m, 39383 m/sec, 2142324 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 516 secs. Pages in use: 97
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 55/348 26/2000 DLCround-PT-12b-CTLFireability-2023-14 2131144 m, 39409 m/sec, 2360075 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 521 secs. Pages in use: 99
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 60/348 28/2000 DLCround-PT-12b-CTLFireability-2023-14 2326067 m, 38984 m/sec, 2575942 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 526 secs. Pages in use: 101
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 65/348 30/2000 DLCround-PT-12b-CTLFireability-2023-14 2521909 m, 39168 m/sec, 2792844 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 531 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 70/348 32/2000 DLCround-PT-12b-CTLFireability-2023-14 2718217 m, 39261 m/sec, 3010431 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 536 secs. Pages in use: 105
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 75/348 34/2000 DLCround-PT-12b-CTLFireability-2023-14 2913388 m, 39034 m/sec, 3227129 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 541 secs. Pages in use: 107
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 80/348 36/2000 DLCround-PT-12b-CTLFireability-2023-14 3109104 m, 39143 m/sec, 3444772 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 546 secs. Pages in use: 109
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 85/348 38/2000 DLCround-PT-12b-CTLFireability-2023-14 3303159 m, 38811 m/sec, 3660068 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 551 secs. Pages in use: 111
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 90/348 40/2000 DLCround-PT-12b-CTLFireability-2023-14 3496549 m, 38678 m/sec, 3875483 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 556 secs. Pages in use: 113
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 95/348 42/2000 DLCround-PT-12b-CTLFireability-2023-14 3689807 m, 38651 m/sec, 4091451 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 561 secs. Pages in use: 115
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 100/348 44/2000 DLCround-PT-12b-CTLFireability-2023-14 3883719 m, 38782 m/sec, 4307877 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 566 secs. Pages in use: 117
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 105/348 45/2000 DLCround-PT-12b-CTLFireability-2023-14 4077809 m, 38818 m/sec, 4523056 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 571 secs. Pages in use: 118
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 110/348 47/2000 DLCround-PT-12b-CTLFireability-2023-14 4269572 m, 38352 m/sec, 4736006 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 576 secs. Pages in use: 120
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 115/348 49/2000 DLCround-PT-12b-CTLFireability-2023-14 4459830 m, 38051 m/sec, 4947544 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 581 secs. Pages in use: 122
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 120/348 50/2000 DLCround-PT-12b-CTLFireability-2023-14 4651889 m, 38411 m/sec, 5162008 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 586 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 125/348 52/2000 DLCround-PT-12b-CTLFireability-2023-14 4843781 m, 38378 m/sec, 5375372 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 591 secs. Pages in use: 125
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 130/348 54/2000 DLCround-PT-12b-CTLFireability-2023-14 5039578 m, 39159 m/sec, 5593072 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 596 secs. Pages in use: 127
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 135/348 56/2000 DLCround-PT-12b-CTLFireability-2023-14 5233135 m, 38711 m/sec, 5808189 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 601 secs. Pages in use: 129
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 140/348 57/2000 DLCround-PT-12b-CTLFireability-2023-14 5425126 m, 38398 m/sec, 6021183 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 606 secs. Pages in use: 130
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 145/348 58/2000 DLCround-PT-12b-CTLFireability-2023-14 5617443 m, 38463 m/sec, 6234212 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 611 secs. Pages in use: 131
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 150/348 60/2000 DLCround-PT-12b-CTLFireability-2023-14 5809054 m, 38322 m/sec, 6446648 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 616 secs. Pages in use: 133
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 155/348 62/2000 DLCround-PT-12b-CTLFireability-2023-14 6001788 m, 38546 m/sec, 6661293 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 621 secs. Pages in use: 135
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 160/348 64/2000 DLCround-PT-12b-CTLFireability-2023-14 6194741 m, 38590 m/sec, 6875883 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 626 secs. Pages in use: 137
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 165/348 65/2000 DLCround-PT-12b-CTLFireability-2023-14 6388170 m, 38685 m/sec, 7092247 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 631 secs. Pages in use: 138
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 170/348 67/2000 DLCround-PT-12b-CTLFireability-2023-14 6579570 m, 38280 m/sec, 7305339 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 636 secs. Pages in use: 140
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 175/348 69/2000 DLCround-PT-12b-CTLFireability-2023-14 6772773 m, 38640 m/sec, 7519660 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 641 secs. Pages in use: 142
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 180/348 70/2000 DLCround-PT-12b-CTLFireability-2023-14 6965625 m, 38570 m/sec, 7733560 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 646 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 185/348 72/2000 DLCround-PT-12b-CTLFireability-2023-14 7158091 m, 38493 m/sec, 7947088 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 651 secs. Pages in use: 145
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 190/348 74/2000 DLCround-PT-12b-CTLFireability-2023-14 7350848 m, 38551 m/sec, 8161840 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 656 secs. Pages in use: 147
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 195/348 75/2000 DLCround-PT-12b-CTLFireability-2023-14 7544597 m, 38749 m/sec, 8376821 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 661 secs. Pages in use: 148
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 200/348 77/2000 DLCround-PT-12b-CTLFireability-2023-14 7737131 m, 38506 m/sec, 8591402 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 666 secs. Pages in use: 150
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 205/348 79/2000 DLCround-PT-12b-CTLFireability-2023-14 7929418 m, 38457 m/sec, 8806833 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 671 secs. Pages in use: 152
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 210/348 81/2000 DLCround-PT-12b-CTLFireability-2023-14 8122520 m, 38620 m/sec, 9022025 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 676 secs. Pages in use: 154
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 215/348 83/2000 DLCround-PT-12b-CTLFireability-2023-14 8315790 m, 38654 m/sec, 9238132 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 681 secs. Pages in use: 156
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 220/348 84/2000 DLCround-PT-12b-CTLFireability-2023-14 8508177 m, 38477 m/sec, 9453307 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 686 secs. Pages in use: 157
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 225/348 86/2000 DLCround-PT-12b-CTLFireability-2023-14 8697827 m, 37930 m/sec, 9663593 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 691 secs. Pages in use: 159
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 230/348 87/2000 DLCround-PT-12b-CTLFireability-2023-14 8888560 m, 38146 m/sec, 9875849 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 696 secs. Pages in use: 160
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 235/348 89/2000 DLCround-PT-12b-CTLFireability-2023-14 9079475 m, 38183 m/sec, 10087614 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 701 secs. Pages in use: 162
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 240/348 90/2000 DLCround-PT-12b-CTLFireability-2023-14 9270664 m, 38237 m/sec, 10300658 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 706 secs. Pages in use: 163
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 245/348 92/2000 DLCround-PT-12b-CTLFireability-2023-14 9461042 m, 38075 m/sec, 10512404 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 711 secs. Pages in use: 165
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 250/348 93/2000 DLCround-PT-12b-CTLFireability-2023-14 9652254 m, 38242 m/sec, 10724584 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 716 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 255/348 95/2000 DLCround-PT-12b-CTLFireability-2023-14 9845418 m, 38632 m/sec, 10939518 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 721 secs. Pages in use: 168
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 260/348 97/2000 DLCround-PT-12b-CTLFireability-2023-14 10036668 m, 38250 m/sec, 11153285 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 726 secs. Pages in use: 170
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 265/348 98/2000 DLCround-PT-12b-CTLFireability-2023-14 10227651 m, 38196 m/sec, 11364939 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 731 secs. Pages in use: 171
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 270/348 100/2000 DLCround-PT-12b-CTLFireability-2023-14 10418167 m, 38103 m/sec, 11577275 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 736 secs. Pages in use: 173
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 275/348 101/2000 DLCround-PT-12b-CTLFireability-2023-14 10609143 m, 38195 m/sec, 11790172 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 741 secs. Pages in use: 174
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 280/348 103/2000 DLCround-PT-12b-CTLFireability-2023-14 10798773 m, 37926 m/sec, 12000169 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 746 secs. Pages in use: 176
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 285/348 105/2000 DLCround-PT-12b-CTLFireability-2023-14 10989683 m, 38182 m/sec, 12212367 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 751 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 290/348 107/2000 DLCround-PT-12b-CTLFireability-2023-14 11181354 m, 38334 m/sec, 12425240 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 756 secs. Pages in use: 180
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 295/348 109/2000 DLCround-PT-12b-CTLFireability-2023-14 11371159 m, 37961 m/sec, 12635780 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 761 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 300/348 111/2000 DLCround-PT-12b-CTLFireability-2023-14 11561716 m, 38111 m/sec, 12847792 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 766 secs. Pages in use: 184
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 305/348 112/2000 DLCround-PT-12b-CTLFireability-2023-14 11751935 m, 38043 m/sec, 13059412 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 771 secs. Pages in use: 185
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 310/348 114/2000 DLCround-PT-12b-CTLFireability-2023-14 11942144 m, 38041 m/sec, 13270355 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 776 secs. Pages in use: 187
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 315/348 116/2000 DLCround-PT-12b-CTLFireability-2023-14 12133316 m, 38234 m/sec, 13482123 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 781 secs. Pages in use: 189
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 320/348 117/2000 DLCround-PT-12b-CTLFireability-2023-14 12324300 m, 38196 m/sec, 13694284 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 786 secs. Pages in use: 190
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 325/348 119/2000 DLCround-PT-12b-CTLFireability-2023-14 12515860 m, 38312 m/sec, 13906216 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 791 secs. Pages in use: 192
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 330/348 121/2000 DLCround-PT-12b-CTLFireability-2023-14 12707747 m, 38377 m/sec, 14119793 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 796 secs. Pages in use: 194
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 335/348 123/2000 DLCround-PT-12b-CTLFireability-2023-14 12899448 m, 38340 m/sec, 14334279 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 801 secs. Pages in use: 196
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 340/348 124/2000 DLCround-PT-12b-CTLFireability-2023-14 13090129 m, 38136 m/sec, 14546378 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 806 secs. Pages in use: 197
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 345/348 126/2000 DLCround-PT-12b-CTLFireability-2023-14 13281411 m, 38256 m/sec, 14759122 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 811 secs. Pages in use: 199
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 51 (type EXCL) for DLCround-PT-12b-CTLFireability-2023-14 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 1 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 816 secs. Pages in use: 201
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 44 (type EXCL) for 43 DLCround-PT-12b-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 348 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 51 (type EXCL) for 46 DLCround-PT-12b-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 2784 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 44 (type EXCL) for DLCround-PT-12b-CTLFireability-2023-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1320
[[35mlola[0m][I] fired transitions : 1321
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 5/348 3/5 DLCround-PT-12b-CTLFireability-2023-14 185542 m, -2619173 m/sec, 202330 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 821 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 51 (type EXCL) for DLCround-PT-12b-CTLFireability-2023-14 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 826 secs. Pages in use: 206
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 41 (type EXCL) for 40 DLCround-PT-12b-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 396 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 5/396 1/2000 DLCround-PT-12b-CTLFireability-2023-12 84219 m, 16843 m/sec, 173592 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 831 secs. Pages in use: 206
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 10/396 2/2000 DLCround-PT-12b-CTLFireability-2023-12 181978 m, 19551 m/sec, 375465 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 836 secs. Pages in use: 206
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 15/396 3/2000 DLCround-PT-12b-CTLFireability-2023-12 284021 m, 20408 m/sec, 586372 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 841 secs. Pages in use: 206
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 20/396 4/2000 DLCround-PT-12b-CTLFireability-2023-12 385141 m, 20224 m/sec, 798356 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 846 secs. Pages in use: 206
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 25/396 4/2000 DLCround-PT-12b-CTLFireability-2023-12 485962 m, 20164 m/sec, 1009158 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 851 secs. Pages in use: 206
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 30/396 5/2000 DLCround-PT-12b-CTLFireability-2023-12 586069 m, 20021 m/sec, 1217446 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 856 secs. Pages in use: 206
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 35/396 6/2000 DLCround-PT-12b-CTLFireability-2023-12 684420 m, 19670 m/sec, 1426818 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 861 secs. Pages in use: 207
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 40/396 6/2000 DLCround-PT-12b-CTLFireability-2023-12 782609 m, 19637 m/sec, 1635004 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 866 secs. Pages in use: 207
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 45/396 7/2000 DLCround-PT-12b-CTLFireability-2023-12 881144 m, 19707 m/sec, 1841598 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 871 secs. Pages in use: 208
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 50/396 8/2000 DLCround-PT-12b-CTLFireability-2023-12 978935 m, 19558 m/sec, 2049159 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 876 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 55/396 9/2000 DLCround-PT-12b-CTLFireability-2023-12 1076307 m, 19474 m/sec, 2256710 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 881 secs. Pages in use: 210
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 60/396 9/2000 DLCround-PT-12b-CTLFireability-2023-12 1175757 m, 19890 m/sec, 2462070 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 886 secs. Pages in use: 210
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 65/396 10/2000 DLCround-PT-12b-CTLFireability-2023-12 1273188 m, 19486 m/sec, 2664851 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 891 secs. Pages in use: 211
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 70/396 11/2000 DLCround-PT-12b-CTLFireability-2023-12 1366964 m, 18755 m/sec, 2868381 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 896 secs. Pages in use: 212
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 75/396 11/2000 DLCround-PT-12b-CTLFireability-2023-12 1460334 m, 18674 m/sec, 3069241 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 901 secs. Pages in use: 212
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 80/396 12/2000 DLCround-PT-12b-CTLFireability-2023-12 1551927 m, 18318 m/sec, 3272972 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 906 secs. Pages in use: 213
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 85/396 13/2000 DLCround-PT-12b-CTLFireability-2023-12 1644105 m, 18435 m/sec, 3476009 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 911 secs. Pages in use: 214
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 90/396 13/2000 DLCround-PT-12b-CTLFireability-2023-12 1737522 m, 18683 m/sec, 3676203 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 916 secs. Pages in use: 214
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 95/396 14/2000 DLCround-PT-12b-CTLFireability-2023-12 1829698 m, 18435 m/sec, 3876347 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 921 secs. Pages in use: 215
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 100/396 15/2000 DLCround-PT-12b-CTLFireability-2023-12 1922481 m, 18556 m/sec, 4075314 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 926 secs. Pages in use: 216
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 105/396 15/2000 DLCround-PT-12b-CTLFireability-2023-12 2015191 m, 18542 m/sec, 4275131 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 931 secs. Pages in use: 216
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 110/396 16/2000 DLCround-PT-12b-CTLFireability-2023-12 2103589 m, 17679 m/sec, 4468598 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 936 secs. Pages in use: 217
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 115/396 17/2000 DLCround-PT-12b-CTLFireability-2023-12 2191343 m, 17550 m/sec, 4659243 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 941 secs. Pages in use: 218
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 120/396 17/2000 DLCround-PT-12b-CTLFireability-2023-12 2278958 m, 17523 m/sec, 4852991 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 946 secs. Pages in use: 218
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 125/396 18/2000 DLCround-PT-12b-CTLFireability-2023-12 2366328 m, 17474 m/sec, 5051290 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 951 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 130/396 19/2000 DLCround-PT-12b-CTLFireability-2023-12 2456809 m, 18096 m/sec, 5247388 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 956 secs. Pages in use: 220
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 135/396 19/2000 DLCround-PT-12b-CTLFireability-2023-12 2548943 m, 18426 m/sec, 5451121 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 961 secs. Pages in use: 220
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 140/396 20/2000 DLCround-PT-12b-CTLFireability-2023-12 2642151 m, 18641 m/sec, 5653604 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 966 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 145/396 20/2000 DLCround-PT-12b-CTLFireability-2023-12 2735392 m, 18648 m/sec, 5855454 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 971 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 150/396 21/2000 DLCround-PT-12b-CTLFireability-2023-12 2826820 m, 18285 m/sec, 6059040 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 976 secs. Pages in use: 222
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 155/396 22/2000 DLCround-PT-12b-CTLFireability-2023-12 2919692 m, 18574 m/sec, 6260363 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 981 secs. Pages in use: 223
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 160/396 22/2000 DLCround-PT-12b-CTLFireability-2023-12 3011327 m, 18327 m/sec, 6463405 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 986 secs. Pages in use: 223
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 165/396 23/2000 DLCround-PT-12b-CTLFireability-2023-12 3105606 m, 18855 m/sec, 6664077 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 991 secs. Pages in use: 224
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 170/396 24/2000 DLCround-PT-12b-CTLFireability-2023-12 3196471 m, 18173 m/sec, 6866848 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 996 secs. Pages in use: 225
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 175/396 24/2000 DLCround-PT-12b-CTLFireability-2023-12 3287477 m, 18201 m/sec, 7069323 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1001 secs. Pages in use: 225
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 180/396 25/2000 DLCround-PT-12b-CTLFireability-2023-12 3378896 m, 18283 m/sec, 7269963 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1006 secs. Pages in use: 226
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 185/396 26/2000 DLCround-PT-12b-CTLFireability-2023-12 3471745 m, 18569 m/sec, 7469828 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1011 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 190/396 26/2000 DLCround-PT-12b-CTLFireability-2023-12 3564035 m, 18458 m/sec, 7670587 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1016 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 195/396 27/2000 DLCround-PT-12b-CTLFireability-2023-12 3655461 m, 18285 m/sec, 7873262 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1021 secs. Pages in use: 228
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 200/396 28/2000 DLCround-PT-12b-CTLFireability-2023-12 3745996 m, 18107 m/sec, 8076332 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1026 secs. Pages in use: 229
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 205/396 28/2000 DLCround-PT-12b-CTLFireability-2023-12 3836785 m, 18157 m/sec, 8277441 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1031 secs. Pages in use: 229
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 210/396 29/2000 DLCround-PT-12b-CTLFireability-2023-12 3928133 m, 18269 m/sec, 8480574 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1036 secs. Pages in use: 230
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 215/396 30/2000 DLCround-PT-12b-CTLFireability-2023-12 4020640 m, 18501 m/sec, 8681789 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1041 secs. Pages in use: 231
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 220/396 30/2000 DLCround-PT-12b-CTLFireability-2023-12 4111246 m, 18121 m/sec, 8882549 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1046 secs. Pages in use: 231
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 225/396 31/2000 DLCround-PT-12b-CTLFireability-2023-12 4202761 m, 18303 m/sec, 9083714 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1051 secs. Pages in use: 232
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 230/396 32/2000 DLCround-PT-12b-CTLFireability-2023-12 4290645 m, 17576 m/sec, 9290700 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1056 secs. Pages in use: 233
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 235/396 32/2000 DLCround-PT-12b-CTLFireability-2023-12 4383680 m, 18607 m/sec, 9491871 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1061 secs. Pages in use: 233
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 240/396 33/2000 DLCround-PT-12b-CTLFireability-2023-12 4475221 m, 18308 m/sec, 9694473 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1066 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 245/396 34/2000 DLCround-PT-12b-CTLFireability-2023-12 4566405 m, 18236 m/sec, 9897063 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1071 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 250/396 34/2000 DLCround-PT-12b-CTLFireability-2023-12 4657588 m, 18236 m/sec, 10101104 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1076 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 255/396 35/2000 DLCround-PT-12b-CTLFireability-2023-12 4749906 m, 18463 m/sec, 10301824 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1081 secs. Pages in use: 236
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 260/396 36/2000 DLCround-PT-12b-CTLFireability-2023-12 4843889 m, 18796 m/sec, 10501111 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1086 secs. Pages in use: 237
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 265/396 36/2000 DLCround-PT-12b-CTLFireability-2023-12 4935737 m, 18369 m/sec, 10702894 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1091 secs. Pages in use: 237
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 270/396 37/2000 DLCround-PT-12b-CTLFireability-2023-12 5027865 m, 18425 m/sec, 10902803 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1096 secs. Pages in use: 238
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 275/396 37/2000 DLCround-PT-12b-CTLFireability-2023-12 5119770 m, 18381 m/sec, 11102181 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1101 secs. Pages in use: 238
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 280/396 38/2000 DLCround-PT-12b-CTLFireability-2023-12 5211378 m, 18321 m/sec, 11302035 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1106 secs. Pages in use: 239
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 285/396 39/2000 DLCround-PT-12b-CTLFireability-2023-12 5303407 m, 18405 m/sec, 11502906 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1111 secs. Pages in use: 240
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 290/396 39/2000 DLCround-PT-12b-CTLFireability-2023-12 5394692 m, 18257 m/sec, 11704991 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1116 secs. Pages in use: 240
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 295/396 40/2000 DLCround-PT-12b-CTLFireability-2023-12 5485374 m, 18136 m/sec, 11906989 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1121 secs. Pages in use: 241
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 300/396 41/2000 DLCround-PT-12b-CTLFireability-2023-12 5576756 m, 18276 m/sec, 12108334 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1126 secs. Pages in use: 242
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 305/396 41/2000 DLCround-PT-12b-CTLFireability-2023-12 5666859 m, 18020 m/sec, 12312074 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1131 secs. Pages in use: 242
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 310/396 42/2000 DLCround-PT-12b-CTLFireability-2023-12 5759468 m, 18521 m/sec, 12512210 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1136 secs. Pages in use: 243
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 315/396 43/2000 DLCround-PT-12b-CTLFireability-2023-12 5850363 m, 18179 m/sec, 12712025 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1141 secs. Pages in use: 244
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 320/396 43/2000 DLCround-PT-12b-CTLFireability-2023-12 5940386 m, 18004 m/sec, 12912511 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1146 secs. Pages in use: 244
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 325/396 44/2000 DLCround-PT-12b-CTLFireability-2023-12 6028013 m, 17525 m/sec, 13118078 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1151 secs. Pages in use: 245
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 330/396 45/2000 DLCround-PT-12b-CTLFireability-2023-12 6120380 m, 18473 m/sec, 13317251 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1156 secs. Pages in use: 246
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 335/396 45/2000 DLCround-PT-12b-CTLFireability-2023-12 6211677 m, 18259 m/sec, 13518113 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1161 secs. Pages in use: 246
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 340/396 46/2000 DLCround-PT-12b-CTLFireability-2023-12 6302752 m, 18215 m/sec, 13717415 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1166 secs. Pages in use: 247
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 345/396 46/2000 DLCround-PT-12b-CTLFireability-2023-12 6392261 m, 17901 m/sec, 13920401 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1171 secs. Pages in use: 247
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 350/396 47/2000 DLCround-PT-12b-CTLFireability-2023-12 6484452 m, 18438 m/sec, 14120639 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1176 secs. Pages in use: 248
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 355/396 48/2000 DLCround-PT-12b-CTLFireability-2023-12 6575865 m, 18282 m/sec, 14319424 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1181 secs. Pages in use: 249
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 360/396 48/2000 DLCround-PT-12b-CTLFireability-2023-12 6667456 m, 18318 m/sec, 14519626 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1186 secs. Pages in use: 249
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 365/396 49/2000 DLCround-PT-12b-CTLFireability-2023-12 6759355 m, 18379 m/sec, 14719405 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1191 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 370/396 50/2000 DLCround-PT-12b-CTLFireability-2023-12 6852292 m, 18587 m/sec, 14916943 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1196 secs. Pages in use: 251
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 375/396 50/2000 DLCround-PT-12b-CTLFireability-2023-12 6942595 m, 18060 m/sec, 15116235 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1201 secs. Pages in use: 251
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 380/396 51/2000 DLCround-PT-12b-CTLFireability-2023-12 7034773 m, 18435 m/sec, 15315152 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1206 secs. Pages in use: 252
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 385/396 52/2000 DLCround-PT-12b-CTLFireability-2023-12 7125348 m, 18115 m/sec, 15514657 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1211 secs. Pages in use: 253
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 390/396 52/2000 DLCround-PT-12b-CTLFireability-2023-12 7215052 m, 17940 m/sec, 15716567 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1216 secs. Pages in use: 253
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 395/396 53/2000 DLCround-PT-12b-CTLFireability-2023-12 7306923 m, 18374 m/sec, 15917111 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1221 secs. Pages in use: 254
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 41 (type EXCL) for DLCround-PT-12b-CTLFireability-2023-12 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1226 secs. Pages in use: 255
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 32 (type EXCL) for 31 DLCround-PT-12b-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 395 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 41 (type EXCL) for 40 DLCround-PT-12b-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 2374 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 32 (type EXCL) for DLCround-PT-12b-CTLFireability-2024-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 135
[[35mlola[0m][I] fired transitions : 271
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 5/395 1/5 DLCround-PT-12b-CTLFireability-2023-12 71952 m, -1446994 m/sec, 148264 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1231 secs. Pages in use: 257
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 10/395 2/5 DLCround-PT-12b-CTLFireability-2023-12 165979 m, 18805 m/sec, 342389 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1236 secs. Pages in use: 257
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 15/395 3/5 DLCround-PT-12b-CTLFireability-2023-12 266546 m, 20113 m/sec, 550353 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1241 secs. Pages in use: 258
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 20/395 3/5 DLCround-PT-12b-CTLFireability-2023-12 366767 m, 20044 m/sec, 757408 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1246 secs. Pages in use: 258
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 25/395 4/5 DLCround-PT-12b-CTLFireability-2023-12 465042 m, 19655 m/sec, 966000 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1251 secs. Pages in use: 259
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 30/395 5/5 DLCround-PT-12b-CTLFireability-2023-12 564845 m, 19960 m/sec, 1173546 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1256 secs. Pages in use: 260
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 41 (type EXCL) for DLCround-PT-12b-CTLFireability-2023-12 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1261 secs. Pages in use: 260
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 29 (type EXCL) for 28 DLCround-PT-12b-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 467 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 29 (type EXCL) for DLCround-PT-12b-CTLFireability-2024-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 134
[[35mlola[0m][I] fired transitions : 134
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 13 (type EXCL) for 12 DLCround-PT-12b-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 584 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 13 (type EXCL) for DLCround-PT-12b-CTLFireability-2024-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 55072
[[35mlola[0m][I] fired transitions : 58606
[[35mlola[0m][I] time used : 2
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 DLCround-PT-12b-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 779 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 3/779 2/2000 DLCround-PT-12b-CTLFireability-2024-03 112157 m, 22431 m/sec, 133868 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1266 secs. Pages in use: 260
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 8/779 5/2000 DLCround-PT-12b-CTLFireability-2024-03 319202 m, 41409 m/sec, 364799 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1271 secs. Pages in use: 260
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 13/779 7/2000 DLCround-PT-12b-CTLFireability-2024-03 523513 m, 40862 m/sec, 591187 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1276 secs. Pages in use: 262
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 18/779 10/2000 DLCround-PT-12b-CTLFireability-2024-03 728100 m, 40917 m/sec, 817654 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1281 secs. Pages in use: 265
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 23/779 12/2000 DLCround-PT-12b-CTLFireability-2024-03 920089 m, 38397 m/sec, 1030117 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1286 secs. Pages in use: 267
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 28/779 14/2000 DLCround-PT-12b-CTLFireability-2024-03 1102072 m, 36396 m/sec, 1231901 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1291 secs. Pages in use: 269
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 34/779 15/2000 DLCround-PT-12b-CTLFireability-2024-03 1185599 m, 16705 m/sec, 1324428 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1297 secs. Pages in use: 270
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 41/779 15/2000 DLCround-PT-12b-CTLFireability-2024-03 1209664 m, 4813 m/sec, 1351035 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1304 secs. Pages in use: 270
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-05: EFEG true state space /EFEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-06: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-12b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-12b-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-12b-CTLFireability-2023-14: CONJ 0 0 0 0 4 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 47/779 16/2000 DLCround-PT-12b-CTLFireability-2024-03 1216019 m, 1271 m/sec, 1357872 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1310 secs. Pages in use: 271
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 398 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-12b"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is DLCround-PT-12b, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r115-smll-171624276700266"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-12b.tgz
mv DLCround-PT-12b execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;