MCC'2024- Execution of r115-smll-171624276700258

About the Execution of LoLA for DLCround-PT-12a

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
16208.775	999104.00	741878.00	4143.10	F?F?F???????????	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r115-smll-171624276700258.qcow2',
Waiting for the VM to be ready (probing ssh)
............................................................
======================================
Generated by BenchKit 2-5568
Executing tool lola
Input is DLCround-PT-12a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r115-smll-171624276700258
============================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.4M
-rw-r--r-- 1 mcc users 8.3K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 94K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.9K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 56K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDe
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertiesVe
-rw-r--r-- 1 mcc users 3.1K Apr 22 14:38 LTLCardinality.txt
-rw-r--r-- 1 mcc users 22K Apr 22 14:38 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Apr 22 14:38 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Apr 22 14:38 LTLFireability.xml
-rw-r--r-- 1 mcc users 16K Apr 13 18:35 ReachabilityCardina
-rw-r--r-- 1 mcc users 173K Apr 13 18:35 ReachabilityCardina
-rw-r--r-- 1 mcc users 8.7K Apr 13 17:27 ReachabilityFireabi
-rw-r--r-- 1 mcc users 74K Apr 13 17:27 ReachabilityFireabi
-rw-r--r-- 1 mcc users 1.6K Apr 22 14:38 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Apr 22 14:38 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 4 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 871K May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from
FORMULA_NAME DLCround-PT-12a-CTLFireability-2024-00
FORMULA_NAME DLCround-PT-12a-CTLFireability-2024-01
FORMULA_NAME DLCround-PT-12a-CTLFireability-2024-02
FORMULA_NAME DLCround-PT-12a-CTLFireability-2024-03
FORMULA_NAME DLCround-PT-12a-CTLFireability-2024-04
FORMULA_NAME DLCround-PT-12a-CTLFireability-2024-05
FORMULA_NAME DLCround-PT-12a-CTLFireability-2024-06
FORMULA_NAME DLCround-PT-12a-CTLFireability-2024-07
FORMULA_NAME DLCround-PT-12a-CTLFireability-2024-08
FORMULA_NAME DLCround-PT-12a-CTLFireability-2024-09
FORMULA_NAME DLCround-PT-12a-CTLFireability-2024-10
FORMULA_NAME DLCround-PT-12a-CTLFireability-2024-11
FORMULA_NAME DLCround-PT-12a-CTLFireability-2023-12
FORMULA_NAME DLCround-PT-12a-CTLFireability-2023-13
FORMULA_NAME DLCround-PT-12a-CTLFireability-2023-14
FORMULA_NAME DLCround-PT-12a-CTLFireability-2023-15

=== Now, execution of the tool begins

BK_START 1717099998462

FORMULA DLCround-PT-12a-CTLFireability-2024-02
FORMULA DLCround-PT-12a-CTLFireability-2024-00
FORMULA DLCround-PT-12a-CTLFireability-2024-04

BK_STOP 1717100997566

--------------------
content from stderr:

[[35mlola[0m][I] LoLA will run for 3600 seconds at
[[35mlola[0m][W] [1m[33munknown unit in memory
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mm
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] Rule S: 0 transitions removed,0
[[35mlola[0m][I] LAUNCH task # 54 (type SKEL/FNDP)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 55 (type SKEL/EQUN)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 56 (type SKEL/SRCH)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 56 (type SKEL/SRCH)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 5
[[35mlola[0m][I] fired transitions : 4
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 54 (type FNDP)
[[35mlola[0m][W] CANCELED task # 55 (type EQUN)
[[35mlola[0m][I] FINISHED task # 54 (type SKEL/FNDP)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] FINISHED task # 55 (type SKEL/EQUN)
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 58 (type EXCL) for
[[35mlola[0m][I] time limit : 199 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 61 (type EQUN) for
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 63 (type EQUN) for
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 58 (type EXCL)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 2
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 61 (type EQUN)
[[35mlola[0m][W] CANCELED task # 63 (type EQUN)
[[35mlola[0m][I] FINISHED task # 63 (type EQUN)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 61 (type EQUN)
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for
[[35mlola[0m][I] time limit : 224 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 65 (type FNDP) for
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 66 (type EQUN) for
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 1 (type EXCL)
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 23
[[35mlola[0m][I] fired transitions : 404
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 67 (type EXCL) for
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 67 (type EXCL)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 3
[[35mlola[0m][I] fired transitions : 2
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 65 (type FNDP)
[[35mlola[0m][W] CANCELED task # 66 (type EQUN)
[[35mlola[0m][I] FINISHED task # 65 (type FNDP)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] LAUNCH task # 15 (type EXCL) for
[[35mlola[0m][I] time limit : 256 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 15 (type EXCL)
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] FINISHED task # 66 (type EQUN)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 32 (type EXCL) for
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 3/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 7 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 8/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 12 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 13/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 17 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 18/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 22 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 23/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 27 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 28/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 32 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 33/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 37 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 38/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 42 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 43/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 47 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 48/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 52 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 53/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 57 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 58/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 62 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 63/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 67 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 68/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 72 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 73/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 77 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 78/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 82 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 83/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 87 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 88/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 92 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 93/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 97 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 98/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 102 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 103/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 107 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 108/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 112 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 113/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 117 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 118/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 122 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 123/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 127 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 128/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 132 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 133/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 137 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 138/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 142 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 143/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 147 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 148/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 152 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 153/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 157 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 158/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 162 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 163/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 167 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 168/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 172 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 173/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 177 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 178/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 182 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 183/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 187 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 188/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 192 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 193/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 197 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 198/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 202 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 203/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 207 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 208/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 212 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 213/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 217 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 218/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 222 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 223/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 227 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 228/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 232 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 233/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 237 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 238/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 242 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 243/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 247 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 248/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 252 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 253/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 257 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 258/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 262 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 263/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 267 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 268/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 272 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 273/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 277 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 32 (type EXCL)
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 282 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 50 (type EXCL) for
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 32 (type EXCL) for
[[35mlola[0m][I] time limit : 3318 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 5/3318
[[35mlola[0m][.] 50 CTL EXCL 5/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 287 secs. Pages
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 10/3318
[[35mlola[0m][.] 50 CTL EXCL 10/255
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 292 secs. Pages
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 15/3318
[[35mlola[0m][.] 50 CTL EXCL 15/255
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 297 secs. Pages
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 20/3318
[[35mlola[0m][.] 50 CTL EXCL 20/255
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 302 secs. Pages
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 25/3318
[[35mlola[0m][.] 50 CTL EXCL 25/255
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 307 secs. Pages
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 30/3318
[[35mlola[0m][.] 50 CTL EXCL 30/255
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 312 secs. Pages
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 35/3318
[[35mlola[0m][.] 50 CTL EXCL 35/255
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 317 secs. Pages
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 40/3318
[[35mlola[0m][.] 50 CTL EXCL 40/255
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 322 secs. Pages
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 45/3318
[[35mlola[0m][.] 50 CTL EXCL 45/255
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 327 secs. Pages
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 50/3318
[[35mlola[0m][.] 50 CTL EXCL 50/255
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 332 secs. Pages
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 55/3318
[[35mlola[0m][.] 50 CTL EXCL 55/255
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 337 secs. Pages
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 60/3318
[[35mlola[0m][.] 50 CTL EXCL 60/255
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 342 secs. Pages
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 65/3318
[[35mlola[0m][.] 50 CTL EXCL 65/255
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 347 secs. Pages
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 70/3318
[[35mlola[0m][.] 50 CTL EXCL 70/255
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 352 secs. Pages
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 75/3318
[[35mlola[0m][.] 50 CTL EXCL 75/255
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 357 secs. Pages
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 80/3318
[[35mlola[0m][.] 50 CTL EXCL 80/255
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 362 secs. Pages
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 85/3318
[[35mlola[0m][.] 50 CTL EXCL 85/255
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 367 secs. Pages
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 90/3318
[[35mlola[0m][.] 50 CTL EXCL 90/255
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 372 secs. Pages
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 95/3318
[[35mlola[0m][.] 50 CTL EXCL 95/255
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 377 secs. Pages
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 100/3318
[[35mlola[0m][.] 50 CTL EXCL 100/255
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 382 secs. Pages
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 32 CTL EXCL 105/3318
[[35mlola[0m][.] 50 CTL EXCL 105/255
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 387 secs. Pages
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 32 (type EXCL)
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 50 CTL EXCL 110/255
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 392 secs. Pages
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 50 CTL EXCL 115/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 397 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 50 CTL EXCL 120/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 402 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 50 CTL EXCL 125/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 407 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 50 CTL EXCL 130/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 412 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 50 CTL EXCL 135/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 417 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 50 CTL EXCL 140/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 422 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 50 CTL EXCL 145/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 427 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 50 CTL EXCL 150/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 432 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 50 CTL EXCL 155/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 437 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 50 CTL EXCL 160/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 442 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 50 CTL EXCL 165/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 447 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 50 CTL EXCL 170/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 452 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 50 CTL EXCL 175/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 457 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 50 CTL EXCL 180/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 462 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 50 CTL EXCL 185/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 467 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 50 CTL EXCL 190/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 472 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 50 CTL EXCL 195/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 477 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 50 CTL EXCL 200/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 482 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 50 CTL EXCL 205/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 487 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 50 CTL EXCL 210/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 492 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 50 CTL EXCL 215/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 497 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 50 CTL EXCL 220/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 502 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 50 CTL EXCL 225/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 507 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 50 CTL EXCL 230/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 512 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 50 CTL EXCL 235/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 517 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 50 CTL EXCL 240/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 522 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 50 CTL EXCL 245/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 527 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 50 CTL EXCL 250/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 532 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 50 CTL EXCL 255/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 537 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 50 CTL EXCL 260/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 542 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 50 CTL EXCL 265/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 547 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 50 CTL EXCL 270/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 552 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 50 CTL EXCL 275/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 557 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 50 (type EXCL)
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 562 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 47 (type EXCL) for
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 50 (type EXCL) for
[[35mlola[0m][I] time limit : 3038 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 47 CTL EXCL 5/276
[[35mlola[0m][.] 50 CTL EXCL 5/3038
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 567 secs. Pages
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 47 CTL EXCL 10/276
[[35mlola[0m][.] 50 CTL EXCL 10/253
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 572 secs. Pages
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 47 CTL EXCL 15/276
[[35mlola[0m][.] 50 CTL EXCL 15/253
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 577 secs. Pages
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 47 CTL EXCL 63/276
[[35mlola[0m][.] 50 CTL EXCL 66/253
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 631 secs. Pages
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 47 CTL EXCL 134/276
[[35mlola[0m][.] 50 CTL EXCL 136/253
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 703 secs. Pages
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 47 CTL EXCL 220/276
[[35mlola[0m][.] 50 CTL EXCL 223/253
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 788 secs. Pages
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.] 47 CTL EXCL 322/276
[[35mlola[0m][.] 50 CTL EXCL 323/253
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 890 secs. Pages
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 47 (type EXCL)
[[35mlola[0m][W] CANCELED task # 50 (type EXCL)
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mDLCround-PT-12a-CTLFireability-2024-04:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-01:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-03:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-05:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-06:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-07:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-08:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-09:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-10:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2024-11:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-12:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-13:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-14:
[[35mlola[0m][.] DLCround-PT-12a-CTLFireability-2023-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 979 secs. Pages
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 44 (type EXCL) for
[[35mlola[0m][I] time limit : 261 sec
[[35mlola[0m][I] memory limit: 2000 pages
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 409 Killed
fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16 ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... =============================== ========= finition.xml rdict.xml lity.txt lity.xml lity.txt lity.xml template) text file) FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT most ([1m[36m--timelimit[0m) specification: using default[0m [4m[34mmodel.pnml[0m m) odel.pnml[0m [0m) [4m[34mCTLFireability.xml[0m places removed for 12 DLCround-PT-12a-CTLFireability-2024-04 for 12 DLCround-PT-12a-CTLFireability-2024-04 for 12 DLCround-PT-12a-CTLFireability-2024-04 for DLCround-PT-12a-CTLFireability-2024-04 for DLCround-PT-12a-CTLFireability-2024-04 (obsolete) for DLCround-PT-12a-CTLFireability-2024-04 (obsolete) for DLCround-PT-12a-CTLFireability-2024-04 for DLCround-PT-12a-CTLFireability-2024-04 6 DLCround-PT-12a-CTLFireability-2024-02 6 DLCround-PT-12a-CTLFireability-2024-02 6 DLCround-PT-12a-CTLFireability-2024-02 for DLCround-PT-12a-CTLFireability-2024-02 for DLCround-PT-12a-CTLFireability-2024-02 (obsolete) for DLCround-PT-12a-CTLFireability-2024-02 (obsolete) for DLCround-PT-12a-CTLFireability-2024-02 for DLCround-PT-12a-CTLFireability-2024-02 0 DLCround-PT-12a-CTLFireability-2024-00 12 DLCround-PT-12a-CTLFireability-2024-04 12 DLCround-PT-12a-CTLFireability-2024-04 for DLCround-PT-12a-CTLFireability-2024-00 12 DLCround-PT-12a-CTLFireability-2024-04 for DLCround-PT-12a-CTLFireability-2024-04 for DLCround-PT-12a-CTLFireability-2024-04 (obsolete) for DLCround-PT-12a-CTLFireability-2024-04 (obsolete) for DLCround-PT-12a-CTLFireability-2024-04 12 DLCround-PT-12a-CTLFireability-2024-04 for DLCround-PT-12a-CTLFireability-2024-04 for DLCround-PT-12a-CTLFireability-2024-04 31 DLCround-PT-12a-CTLFireability-2024-09 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCround-PT-12a-CTLFireability-2024-09 20073 m, 4014 m/sec, 1575833 t fired, . in use: 1 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCround-PT-12a-CTLFireability-2024-09 74481 m, 10881 m/sec, 5968853 t fired, . in use: 1 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCround-PT-12a-CTLFireability-2024-09 131183 m, 11340 m/sec, 10524094 t fired, . in use: 1 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCround-PT-12a-CTLFireability-2024-09 188954 m, 11554 m/sec, 14999135 t fired, . in use: 1 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 2/2000 DLCround-PT-12a-CTLFireability-2024-09 244926 m, 11194 m/sec, 19487392 t fired, . in use: 2 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 2/2000 DLCround-PT-12a-CTLFireability-2024-09 299997 m, 11014 m/sec, 24020386 t fired, . in use: 2 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 2/2000 DLCround-PT-12a-CTLFireability-2024-09 353658 m, 10732 m/sec, 28317618 t fired, . in use: 2 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 2/2000 DLCround-PT-12a-CTLFireability-2024-09 408671 m, 11002 m/sec, 32802636 t fired, . in use: 2 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 2/2000 DLCround-PT-12a-CTLFireability-2024-09 461717 m, 10609 m/sec, 37275056 t fired, . in use: 2 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 3/2000 DLCround-PT-12a-CTLFireability-2024-09 518457 m, 11348 m/sec, 41809993 t fired, . in use: 3 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 3/2000 DLCround-PT-12a-CTLFireability-2024-09 571049 m, 10518 m/sec, 46280972 t fired, . in use: 3 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 3/2000 DLCround-PT-12a-CTLFireability-2024-09 623646 m, 10519 m/sec, 50658901 t fired, . in use: 3 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 3/2000 DLCround-PT-12a-CTLFireability-2024-09 682119 m, 11694 m/sec, 54992494 t fired, . in use: 3 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 4/2000 DLCround-PT-12a-CTLFireability-2024-09 739577 m, 11491 m/sec, 59371050 t fired, . in use: 4 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 4/2000 DLCround-PT-12a-CTLFireability-2024-09 797382 m, 11561 m/sec, 63772945 t fired, . in use: 4 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 4/2000 DLCround-PT-12a-CTLFireability-2024-09 856476 m, 11818 m/sec, 68206351 t fired, . in use: 4 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 4/2000 DLCround-PT-12a-CTLFireability-2024-09 911178 m, 10940 m/sec, 72594870 t fired, . in use: 4 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 5/2000 DLCround-PT-12a-CTLFireability-2024-09 969548 m, 11674 m/sec, 77018547 t fired, . in use: 5 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 5/2000 DLCround-PT-12a-CTLFireability-2024-09 1030205 m, 12131 m/sec, 81417760 t fired, . in use: 5 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 5/2000 DLCround-PT-12a-CTLFireability-2024-09 1086238 m, 11206 m/sec, 85732993 t fired, . in use: 5 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 5/2000 DLCround-PT-12a-CTLFireability-2024-09 1148462 m, 12444 m/sec, 90016218 t fired, . in use: 5 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 6/2000 DLCround-PT-12a-CTLFireability-2024-09 1205276 m, 11362 m/sec, 94366171 t fired, . in use: 6 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 6/2000 DLCround-PT-12a-CTLFireability-2024-09 1260866 m, 11118 m/sec, 98712007 t fired, . in use: 6 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 6/2000 DLCround-PT-12a-CTLFireability-2024-09 1316926 m, 11212 m/sec, 102992971 t fired, . in use: 6 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 6/2000 DLCround-PT-12a-CTLFireability-2024-09 1371266 m, 10868 m/sec, 107339604 t fired, . in use: 6 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 7/2000 DLCround-PT-12a-CTLFireability-2024-09 1431442 m, 12035 m/sec, 111562776 t fired, . in use: 7 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 7/2000 DLCround-PT-12a-CTLFireability-2024-09 1491010 m, 11913 m/sec, 115897369 t fired, . in use: 7 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 7/2000 DLCround-PT-12a-CTLFireability-2024-09 1548629 m, 11523 m/sec, 120193035 t fired, . in use: 7 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 7/2000 DLCround-PT-12a-CTLFireability-2024-09 1605595 m, 11393 m/sec, 124509465 t fired, . in use: 7 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 7/2000 DLCround-PT-12a-CTLFireability-2024-09 1666139 m, 12108 m/sec, 129244071 t fired, . in use: 7 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 8/2000 DLCround-PT-12a-CTLFireability-2024-09 1726689 m, 12110 m/sec, 133947134 t fired, . in use: 8 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 8/2000 DLCround-PT-12a-CTLFireability-2024-09 1783394 m, 11341 m/sec, 138198720 t fired, . in use: 8 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 8/2000 DLCround-PT-12a-CTLFireability-2024-09 1837671 m, 10855 m/sec, 142498295 t fired, . in use: 8 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 8/2000 DLCround-PT-12a-CTLFireability-2024-09 1896961 m, 11858 m/sec, 146788908 t fired, . in use: 8 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 9/2000 DLCround-PT-12a-CTLFireability-2024-09 1956171 m, 11842 m/sec, 151018558 t fired, . in use: 9 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 9/2000 DLCround-PT-12a-CTLFireability-2024-09 2012042 m, 11174 m/sec, 155211126 t fired, . in use: 9 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 9/2000 DLCround-PT-12a-CTLFireability-2024-09 2074338 m, 12459 m/sec, 159939870 t fired, . in use: 9 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 9/2000 DLCround-PT-12a-CTLFireability-2024-09 2134569 m, 12046 m/sec, 164725424 t fired, . in use: 9 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 10/2000 DLCround-PT-12a-CTLFireability-2024-09 2192271 m, 11540 m/sec, 169062100 t fired, . in use: 10 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 10/2000 DLCround-PT-12a-CTLFireability-2024-09 2248926 m, 11331 m/sec, 173275576 t fired, . in use: 10 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 10/2000 DLCround-PT-12a-CTLFireability-2024-09 2308027 m, 11820 m/sec, 177562951 t fired, . in use: 10 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 10/2000 DLCround-PT-12a-CTLFireability-2024-09 2364205 m, 11235 m/sec, 181752606 t fired, . in use: 10 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 11/2000 DLCround-PT-12a-CTLFireability-2024-09 2418542 m, 10867 m/sec, 186060404 t fired, . in use: 11 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 11/2000 DLCround-PT-12a-CTLFireability-2024-09 2473026 m, 10896 m/sec, 190366163 t fired, . in use: 11 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 11/2000 DLCround-PT-12a-CTLFireability-2024-09 2528195 m, 11033 m/sec, 194517148 t fired, . in use: 11 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 11/2000 DLCround-PT-12a-CTLFireability-2024-09 2589909 m, 12342 m/sec, 198736432 t fired, . in use: 11 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 12/2000 DLCround-PT-12a-CTLFireability-2024-09 2646775 m, 11373 m/sec, 202964012 t fired, . in use: 12 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 12/2000 DLCround-PT-12a-CTLFireability-2024-09 2704017 m, 11448 m/sec, 207209888 t fired, . in use: 12 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 12/2000 DLCround-PT-12a-CTLFireability-2024-09 2762663 m, 11729 m/sec, 211372133 t fired, . in use: 12 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 12/2000 DLCround-PT-12a-CTLFireability-2024-09 2824865 m, 12440 m/sec, 215568325 t fired, . in use: 12 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 13/2000 DLCround-PT-12a-CTLFireability-2024-09 2884889 m, 12004 m/sec, 219777427 t fired, . in use: 13 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 13/2000 DLCround-PT-12a-CTLFireability-2024-09 2942503 m, 11522 m/sec, 223975514 t fired, . in use: 13 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 13/2000 DLCround-PT-12a-CTLFireability-2024-09 3000680 m, 11635 m/sec, 228211688 t fired, . in use: 13 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 13/2000 DLCround-PT-12a-CTLFireability-2024-09 3061221 m, 12108 m/sec, 232434208 t fired, . in use: 13 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 14/2000 DLCround-PT-12a-CTLFireability-2024-09 3117637 m, 11283 m/sec, 236634047 t fired, . in use: 14 for DLCround-PT-12a-CTLFireability-2024-09 (local timeout) CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 1 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m in use: 14 49 DLCround-PT-12a-CTLFireability-2023-15 31 DLCround-PT-12a-CTLFireability-2024-09 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 1/5 DLCround-PT-12a-CTLFireability-2024-09 57596 m, -612008 m/sec, 4606456 t fired, . 1/2000 DLCround-PT-12a-CTLFireability-2023-15 40445 m, 8089 m/sec, 5010910 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 1/5 DLCround-PT-12a-CTLFireability-2024-09 113387 m, 11158 m/sec, 9147913 t fired, . 1/2000 DLCround-PT-12a-CTLFireability-2023-15 86943 m, 9299 m/sec, 10108531 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 1/5 DLCround-PT-12a-CTLFireability-2024-09 171265 m, 11575 m/sec, 13621324 t fired, . 1/2000 DLCround-PT-12a-CTLFireability-2023-15 148110 m, 12233 m/sec, 15095479 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 1/5 DLCround-PT-12a-CTLFireability-2024-09 227051 m, 11157 m/sec, 18042974 t fired, . 1/2000 DLCround-PT-12a-CTLFireability-2023-15 213509 m, 13079 m/sec, 20182392 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 2/5 DLCround-PT-12a-CTLFireability-2024-09 281039 m, 10797 m/sec, 22470001 t fired, . 2/2000 DLCround-PT-12a-CTLFireability-2023-15 281606 m, 13619 m/sec, 25377076 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 2/5 DLCround-PT-12a-CTLFireability-2024-09 336256 m, 11043 m/sec, 26896899 t fired, . 2/2000 DLCround-PT-12a-CTLFireability-2023-15 351331 m, 13945 m/sec, 30539592 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 2/5 DLCround-PT-12a-CTLFireability-2024-09 390658 m, 10880 m/sec, 31318804 t fired, . 2/2000 DLCround-PT-12a-CTLFireability-2023-15 422557 m, 14245 m/sec, 35802234 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 2/5 DLCround-PT-12a-CTLFireability-2024-09 443396 m, 10547 m/sec, 35736098 t fired, . 3/2000 DLCround-PT-12a-CTLFireability-2023-15 492509 m, 13990 m/sec, 41066404 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 3/5 DLCround-PT-12a-CTLFireability-2024-09 498807 m, 11082 m/sec, 40215014 t fired, . 3/2000 DLCround-PT-12a-CTLFireability-2023-15 560376 m, 13573 m/sec, 46155410 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 3/5 DLCround-PT-12a-CTLFireability-2024-09 551816 m, 10601 m/sec, 44677920 t fired, . 3/2000 DLCround-PT-12a-CTLFireability-2023-15 630271 m, 13979 m/sec, 51258973 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 3/5 DLCround-PT-12a-CTLFireability-2024-09 603854 m, 10407 m/sec, 49039590 t fired, . 3/2000 DLCround-PT-12a-CTLFireability-2023-15 694961 m, 12938 m/sec, 56157013 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 3/5 DLCround-PT-12a-CTLFireability-2024-09 658234 m, 10876 m/sec, 53371538 t fired, . 4/2000 DLCround-PT-12a-CTLFireability-2023-15 765110 m, 14029 m/sec, 61164743 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 4/5 DLCround-PT-12a-CTLFireability-2024-09 717196 m, 11792 m/sec, 57627846 t fired, . 4/2000 DLCround-PT-12a-CTLFireability-2023-15 835063 m, 13990 m/sec, 66297618 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 4/5 DLCround-PT-12a-CTLFireability-2024-09 775116 m, 11584 m/sec, 62008479 t fired, . 4/2000 DLCround-PT-12a-CTLFireability-2023-15 901857 m, 13358 m/sec, 71249794 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 4/5 DLCround-PT-12a-CTLFireability-2024-09 831988 m, 11374 m/sec, 66308962 t fired, . 5/2000 DLCround-PT-12a-CTLFireability-2023-15 975402 m, 14709 m/sec, 76495540 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 4/5 DLCround-PT-12a-CTLFireability-2024-09 887741 m, 11150 m/sec, 70636567 t fired, . 5/2000 DLCround-PT-12a-CTLFireability-2023-15 1048796 m, 14678 m/sec, 81816430 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 4/5 DLCround-PT-12a-CTLFireability-2024-09 941074 m, 10666 m/sec, 74882962 t fired, . 5/2000 DLCround-PT-12a-CTLFireability-2023-15 1116605 m, 13561 m/sec, 86766700 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 5/5 DLCround-PT-12a-CTLFireability-2024-09 1000416 m, 11868 m/sec, 79263076 t fired, . 5/2000 DLCround-PT-12a-CTLFireability-2023-15 1182514 m, 13181 m/sec, 91646477 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 5/5 DLCround-PT-12a-CTLFireability-2024-09 1057322 m, 11381 m/sec, 83555819 t fired, . 6/2000 DLCround-PT-12a-CTLFireability-2023-15 1256945 m, 14886 m/sec, 96827164 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 5/5 DLCround-PT-12a-CTLFireability-2024-09 1116182 m, 11772 m/sec, 87751393 t fired, . 6/2000 DLCround-PT-12a-CTLFireability-2023-15 1327509 m, 14112 m/sec, 101814562 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 5/5 DLCround-PT-12a-CTLFireability-2024-09 1174744 m, 11712 m/sec, 91994505 t fired, . 6/2000 DLCround-PT-12a-CTLFireability-2023-15 1394284 m, 13355 m/sec, 106680215 t fired, . in use: 14 for DLCround-PT-12a-CTLFireability-2024-09 (memory limit exceeded) CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 7/2000 DLCround-PT-12a-CTLFireability-2023-15 1465867 m, 14316 m/sec, 111689007 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 7/2000 DLCround-PT-12a-CTLFireability-2023-15 1534777 m, 13782 m/sec, 116770037 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 7/2000 DLCround-PT-12a-CTLFireability-2023-15 1606263 m, 14297 m/sec, 121888699 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 7/2000 DLCround-PT-12a-CTLFireability-2023-15 1668045 m, 12356 m/sec, 126745792 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 8/2000 DLCround-PT-12a-CTLFireability-2023-15 1736391 m, 13669 m/sec, 131720021 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 8/2000 DLCround-PT-12a-CTLFireability-2023-15 1808940 m, 14509 m/sec, 136823587 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 8/2000 DLCround-PT-12a-CTLFireability-2023-15 1881614 m, 14534 m/sec, 141946322 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 9/2000 DLCround-PT-12a-CTLFireability-2023-15 1954517 m, 14580 m/sec, 147046523 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 9/2000 DLCround-PT-12a-CTLFireability-2023-15 2028226 m, 14741 m/sec, 152187996 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 9/2000 DLCround-PT-12a-CTLFireability-2023-15 2100366 m, 14428 m/sec, 157253805 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 10/2000 DLCround-PT-12a-CTLFireability-2023-15 2171780 m, 14282 m/sec, 162200543 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 10/2000 DLCround-PT-12a-CTLFireability-2023-15 2244643 m, 14572 m/sec, 167259994 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 10/2000 DLCround-PT-12a-CTLFireability-2023-15 2314997 m, 14070 m/sec, 172243868 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 11/2000 DLCround-PT-12a-CTLFireability-2023-15 2386048 m, 14210 m/sec, 177218876 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 11/2000 DLCround-PT-12a-CTLFireability-2023-15 2459439 m, 14678 m/sec, 182279420 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 11/2000 DLCround-PT-12a-CTLFireability-2023-15 2532501 m, 14612 m/sec, 187355232 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 11/2000 DLCround-PT-12a-CTLFireability-2023-15 2604369 m, 14373 m/sec, 192329130 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 12/2000 DLCround-PT-12a-CTLFireability-2023-15 2677224 m, 14571 m/sec, 197419314 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 12/2000 DLCround-PT-12a-CTLFireability-2023-15 2751169 m, 14789 m/sec, 202467654 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 12/2000 DLCround-PT-12a-CTLFireability-2023-15 2816424 m, 13051 m/sec, 207408947 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 13/2000 DLCround-PT-12a-CTLFireability-2023-15 2888697 m, 14454 m/sec, 212402535 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 13/2000 DLCround-PT-12a-CTLFireability-2023-15 2960690 m, 14398 m/sec, 217351415 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 13/2000 DLCround-PT-12a-CTLFireability-2023-15 3025933 m, 13048 m/sec, 222194936 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 13/2000 DLCround-PT-12a-CTLFireability-2023-15 3087208 m, 12255 m/sec, 227018584 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 14/2000 DLCround-PT-12a-CTLFireability-2023-15 3148870 m, 12332 m/sec, 231841393 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 14/2000 DLCround-PT-12a-CTLFireability-2023-15 3218643 m, 13954 m/sec, 236895088 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 14/2000 DLCround-PT-12a-CTLFireability-2023-15 3290401 m, 14351 m/sec, 241825891 t fired, . in use: 14 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 15/2000 DLCround-PT-12a-CTLFireability-2023-15 3361405 m, 14200 m/sec, 246690670 t fired, . in use: 15 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 15/2000 DLCround-PT-12a-CTLFireability-2023-15 3424712 m, 12661 m/sec, 251481836 t fired, . in use: 15 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 15/2000 DLCround-PT-12a-CTLFireability-2023-15 3488236 m, 12704 m/sec, 256313360 t fired, . in use: 15 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 15/2000 DLCround-PT-12a-CTLFireability-2023-15 3560708 m, 14494 m/sec, 261276307 t fired, . in use: 15 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 16/2000 DLCround-PT-12a-CTLFireability-2023-15 3633456 m, 14549 m/sec, 266288256 t fired, . in use: 16 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 16/2000 DLCround-PT-12a-CTLFireability-2023-15 3704140 m, 14136 m/sec, 271194576 t fired, . in use: 16 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 16/2000 DLCround-PT-12a-CTLFireability-2023-15 3776437 m, 14459 m/sec, 276218242 t fired, . in use: 16 for DLCround-PT-12a-CTLFireability-2023-15 (local timeout) CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 1 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m in use: 17 46 DLCround-PT-12a-CTLFireability-2023-14 49 DLCround-PT-12a-CTLFireability-2023-15 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCround-PT-12a-CTLFireability-2023-14 164021 m, 32804 m/sec, 3405416 t fired, . 1/5 DLCround-PT-12a-CTLFireability-2023-15 39850 m, -747317 m/sec, 4972459 t fired, . in use: 20 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 2/2000 DLCround-PT-12a-CTLFireability-2023-14 321710 m, 31537 m/sec, 6793390 t fired, . 1/5 DLCround-PT-12a-CTLFireability-2023-15 83864 m, 8802 m/sec, 9844518 t fired, . in use: 21 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 2/2000 DLCround-PT-12a-CTLFireability-2023-14 474180 m, 30494 m/sec, 10204124 t fired, . 1/5 DLCround-PT-12a-CTLFireability-2023-15 142245 m, 11676 m/sec, 14622290 t fired, . in use: 21 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 3/2000 DLCround-PT-12a-CTLFireability-2023-14 584026 m, 21969 m/sec, 12019491 t fired, . 1/5 DLCround-PT-12a-CTLFireability-2023-15 177296 m, 7010 m/sec, 17383937 t fired, . in use: 22 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 3/2000 DLCround-PT-12a-CTLFireability-2023-14 584305 m, 55 m/sec, 12022752 t fired, . 1/5 DLCround-PT-12a-CTLFireability-2023-15 177393 m, 19 m/sec, 17389849 t fired, . in use: 22 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 3/2000 DLCround-PT-12a-CTLFireability-2023-14 586854 m, 509 m/sec, 12063335 t fired, . 1/5 DLCround-PT-12a-CTLFireability-2023-15 178081 m, 137 m/sec, 17437132 t fired, . in use: 22 CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 3/2000 DLCround-PT-12a-CTLFireability-2023-14 587416 m, 112 m/sec, 12071863 t fired, . 1/5 DLCround-PT-12a-CTLFireability-2023-15 178122 m, 8 m/sec, 17440296 t fired, . in use: 22 for DLCround-PT-12a-CTLFireability-2023-14 (local timeout) for DLCround-PT-12a-CTLFireability-2023-15 (local timeout) CATEGORY VALUE PRODUCED BY[0m CTL false CTL model checker[0m AGAF false state space /EFEG[0m DISJ false DISJ[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 1 0 0 CTL 0 0 0 0 1 1 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m in use: 22 43 DLCround-PT-12a-CTLFireability-2023-13 $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-12a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is DLCround-PT-12a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r115-smll-171624276700258"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-12a.tgz
mv DLCround-PT-12a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;