fond
Model Checking Contest 2024
14th edition, Geneva, Switzerland, June 25, 2024
Execution of r115-smll-171624276600228
Last Updated
July 7, 2024

About the Execution of LoLA for DLCround-PT-10a

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
16204.044 882771.00 892348.00 2518.80 ???F???????????? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r115-smll-171624276600228.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is DLCround-PT-10a, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r115-smll-171624276600228
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.2M
-rw-r--r-- 1 mcc users 5.8K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 61K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.0K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 44K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.3K Apr 22 14:38 LTLCardinality.txt
-rw-r--r-- 1 mcc users 22K Apr 22 14:38 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Apr 22 14:38 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 22 14:38 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Apr 13 16:48 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 148K Apr 13 16:48 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.0K Apr 13 16:08 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 78K Apr 13 16:08 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 22 14:38 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Apr 22 14:38 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 4 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 660K May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-10a-LTLFireability-00
FORMULA_NAME DLCround-PT-10a-LTLFireability-01
FORMULA_NAME DLCround-PT-10a-LTLFireability-02
FORMULA_NAME DLCround-PT-10a-LTLFireability-03
FORMULA_NAME DLCround-PT-10a-LTLFireability-04
FORMULA_NAME DLCround-PT-10a-LTLFireability-05
FORMULA_NAME DLCround-PT-10a-LTLFireability-06
FORMULA_NAME DLCround-PT-10a-LTLFireability-07
FORMULA_NAME DLCround-PT-10a-LTLFireability-08
FORMULA_NAME DLCround-PT-10a-LTLFireability-09
FORMULA_NAME DLCround-PT-10a-LTLFireability-10
FORMULA_NAME DLCround-PT-10a-LTLFireability-11
FORMULA_NAME DLCround-PT-10a-LTLFireability-12
FORMULA_NAME DLCround-PT-10a-LTLFireability-13
FORMULA_NAME DLCround-PT-10a-LTLFireability-14
FORMULA_NAME DLCround-PT-10a-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1717087971494

FORMULA DLCround-PT-10a-LTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1717088854265

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains place/transition net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading formula.
[lola][I] Using XML format (--xmlformula)
[lola][I] reading XML formula
[lola][I] reading formula from LTLFireability.xml
[lola][I] NOTDEADLOCKFREE
[lola][I] LAUNCH task # 64 (type SKEL/SRCH) for 3 DLCround-PT-10a-LTLFireability-01
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 64 (type SKEL/SRCH) for DLCround-PT-10a-LTLFireability-01
[lola][I] result : true
[lola][I] markings : 2
[lola][I] fired transitions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] Rule S: 0 transitions removed,0 places removed
[*** LOG ERROR #0001 ***] [2024-05-30 16:52:51] [status_logger] string pointer is null
[lola][I] NOTDEADLOCKFREE
[lola][I] NOTDEADLOCKFREE
[lola][I] LAUNCH task # 65 (type SKEL/SRCH) for 19 DLCround-PT-10a-LTLFireability-05
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 65 (type SKEL/SRCH) for DLCround-PT-10a-LTLFireability-05
[lola][I] result : true
[lola][I] markings : 2
[lola][I] fired transitions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] NOTDEADLOCKFREE
[lola][I] NOTDEADLOCKFREE
[lola][I] LAUNCH task # 22 (type EXCL) for 19 DLCround-PT-10a-LTLFireability-05
[lola][I] time limit : 149 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 22 (type EXCL) for DLCround-PT-10a-LTLFireability-05
[lola][I] result : true
[lola][I] markings : 2
[lola][I] fired transitions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 14 (type EXCL) for 13 DLCround-PT-10a-LTLFireability-03
[lola][I] time limit : 156 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 67 (type FNDP) for 19 DLCround-PT-10a-LTLFireability-05
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 68 (type EQUN) for 19 DLCround-PT-10a-LTLFireability-05
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 14 (type EXCL) for DLCround-PT-10a-LTLFireability-03
[lola][I] result : false
[lola][I] markings : 6
[lola][I] fired transitions : 6
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 69 (type EXCL) for 19 DLCround-PT-10a-LTLFireability-05
[lola][I] time limit : 163 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 69 (type EXCL) for DLCround-PT-10a-LTLFireability-05
[lola][I] result : true
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 67 (type FNDP) for DLCround-PT-10a-LTLFireability-05 (obsolete)
[lola][W] CANCELED task # 68 (type EQUN) for DLCround-PT-10a-LTLFireability-05 (obsolete)
[lola][I] LAUNCH task # 1 (type EXCL) for 0 DLCround-PT-10a-LTLFireability-00
[lola][I] time limit : 179 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 1 (type EXCL) for DLCround-PT-10a-LTLFireability-00
[lola][I] result : false
[lola][I] markings : 2
[lola][I] fired transitions : 2
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] FINISHED task # 68 (type EQUN) for DLCround-PT-10a-LTLFireability-05
[lola][I] result : unknown
[lola][I] FINISHED task # 67 (type FNDP) for DLCround-PT-10a-LTLFireability-05
[lola][I] result : true
[lola][I] tried executions : 1
[lola][I] time used : 1
[lola][I] memory pages used : 0
[lola][I] LAUNCH task # 40 (type EXCL) for 39 DLCround-PT-10a-LTLFireability-09
[lola][I] time limit : 199 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 40 (type EXCL) for DLCround-PT-10a-LTLFireability-09
[lola][I] result : false
[lola][I] markings : 4
[lola][I] fired transitions : 4
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] NOTDEADLOCKFREE
[lola][I] LAUNCH task # 8 (type EXCL) for 3 DLCround-PT-10a-LTLFireability-01
[lola][I] time limit : 239 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 8 (type EXCL) for DLCround-PT-10a-LTLFireability-01
[lola][I] result : false
[lola][I] markings : 4
[lola][I] fired transitions : 4
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 56 (type EXCL) for 55 DLCround-PT-10a-LTLFireability-13
[lola][I] time limit : 257 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 56 (type EXCL) for DLCround-PT-10a-LTLFireability-13
[lola][I] result : false
[lola][I] markings : 4
[lola][I] fired transitions : 4
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 47 (type EXCL) for 42 DLCround-PT-10a-LTLFireability-10
[lola][I] time limit : 276 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 47 (type EXCL) for DLCround-PT-10a-LTLFireability-10
[lola][I] result : false
[lola][I] markings : 4
[lola][I] fired transitions : 4
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 37 (type EXCL) for 36 DLCround-PT-10a-LTLFireability-08
[lola][I] time limit : 327 sec
[lola][I] memory limit: 2000 pages
[lola][I] NOTDEADLOCKFREE
[lola][I] FINISHED task # 37 (type EXCL) for DLCround-PT-10a-LTLFireability-08
[lola][I] result : false
[lola][I] markings : 4
[lola][I] fired transitions : 4
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 50 (type EXCL) for 49 DLCround-PT-10a-LTLFireability-11
[lola][I] time limit : 399 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 50 (type EXCL) for DLCround-PT-10a-LTLFireability-11
[lola][I] result : false
[lola][I] markings : 4
[lola][I] fired transitions : 4
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 34 (type EXCL) for 33 DLCround-PT-10a-LTLFireability-07
[lola][I] time limit : 449 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-10a-LTLFireability-00: LTL false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-01: CONJ false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-03: LTL false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-05: CONJ false state space
[lola][.] DLCround-PT-10a-LTLFireability-08: LTL false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-09: LTL false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-10: CONJ false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-11: LTL false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-13: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-10a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-10a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-10a-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCround-PT-10a-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-10a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-10a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-10a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 34 LTL EXCL 3/449 1/2000 DLCround-PT-10a-LTLFireability-07 101158 m, 20231 m/sec, 3802908 t fired, .
[lola][.]
[lola][.] Time elapsed: 5 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-10a-LTLFireability-00: LTL false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-01: CONJ false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-03: LTL false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-05: CONJ false state space
[lola][.] DLCround-PT-10a-LTLFireability-08: LTL false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-09: LTL false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-10: CONJ false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-11: LTL false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-13: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-10a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-10a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-10a-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCround-PT-10a-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-10a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-10a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-10a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 34 LTL EXCL 8/449 2/2000 DLCround-PT-10a-LTLFireability-07 233010 m, 26370 m/sec, 8949591 t fired, .
[lola][.]
[lola][.] Time elapsed: 10 secs. Pages in use: 2
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] FINISHED task # 34 (type EXCL) for DLCround-PT-10a-LTLFireability-07
[lola][I] result : false
[lola][I] markings : 260284
[lola][I] fired transitions : 10017427
[lola][I] time used : 9
[lola][I] memory pages used : 2
[lola][I] LAUNCH task # 59 (type EXCL) for 58 DLCround-PT-10a-LTLFireability-14
[lola][I] time limit : 512 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 59 (type EXCL) for DLCround-PT-10a-LTLFireability-14
[lola][I] result : false
[lola][I] markings : 16
[lola][I] fired transitions : 64
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 53 (type EXCL) for 52 DLCround-PT-10a-LTLFireability-12
[lola][I] time limit : 598 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 53 (type EXCL) for DLCround-PT-10a-LTLFireability-12
[lola][I] result : true
[lola][I] markings : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 29 (type EXCL) for 26 DLCround-PT-10a-LTLFireability-06
[lola][I] time limit : 717 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 29 (type EXCL) for DLCround-PT-10a-LTLFireability-06
[lola][I] result : true
[lola][I] markings : 2
[lola][I] fired transitions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 17 (type EXCL) for 16 DLCround-PT-10a-LTLFireability-04
[lola][I] time limit : 897 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 17 (type EXCL) for DLCround-PT-10a-LTLFireability-04
[lola][I] result : false
[lola][I] markings : 4
[lola][I] fired transitions : 4
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 11 (type EXCL) for 10 DLCround-PT-10a-LTLFireability-02
[lola][I] time limit : 1196 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-10a-LTLFireability-00: LTL false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-01: CONJ false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-03: LTL false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-04: LTL false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-05: CONJ false state space
[lola][.] DLCround-PT-10a-LTLFireability-07: LTL false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-08: LTL false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-09: LTL false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-10: CONJ false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-11: LTL false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-12: LTL true LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-13: LTL false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-14: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-10a-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-10a-LTLFireability-06: CONJ 0 1 0 0 3 0 0 0
[lola][.] DLCround-PT-10a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 11 LTL EXCL 4/1196 1/2000 DLCround-PT-10a-LTLFireability-02 104376 m, 20875 m/sec, 3929033 t fired, .
[lola][.]
[lola][.] Time elapsed: 15 secs. Pages in use: 2
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-10a-LTLFireability-00: LTL false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-01: CONJ false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-03: LTL false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-04: LTL false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-05: CONJ false state space
[lola][.] DLCround-PT-10a-LTLFireability-07: LTL false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-08: LTL false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-09: LTL false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-10: CONJ false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-11: LTL false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-12: LTL true LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-13: LTL false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-14: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-10a-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-10a-LTLFireability-06: CONJ 0 1 0 0 3 0 0 0
[lola][.] DLCround-PT-10a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 11 LTL EXCL 9/1196 2/2000 DLCround-PT-10a-LTLFireability-02 241994 m, 27523 m/sec, 9305703 t fired, .
[lola][.]
[lola][.] Time elapsed: 20 secs. Pages in use: 2
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-10a-LTLFireability-00: LTL false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-01: CONJ false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-03: LTL false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-04: LTL false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-05: CONJ false state space
[lola][.] DLCround-PT-10a-LTLFireability-07: LTL false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-08: LTL false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-09: LTL false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-10: CONJ false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-11: LTL false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-12: LTL true LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-13: LTL false LTL model checker
[lola][.] DLCround-PT-10a-LTLFireability-14: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-10a-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-10a-LTLFireability-06: CONJ 0 1 0 0 3 0 0 0
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[lola][.] 11 LTL EXCL 14/1196 3/2000 DLCround-PT-10a-LTLFireability-02 375539 m, 26709 m/sec, 14637531 t fired, .
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[lola][.] 11 LTL EXCL 19/1196 4/2000 DLCround-PT-10a-LTLFireability-02 507024 m, 26297 m/sec, 19928573 t fired, .
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[lola][.] 11 LTL EXCL 24/1196 5/2000 DLCround-PT-10a-LTLFireability-02 637886 m, 26172 m/sec, 25225801 t fired, .
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[lola][.] 11 LTL EXCL 29/1196 5/2000 DLCround-PT-10a-LTLFireability-02 769282 m, 26279 m/sec, 30461561 t fired, .
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[lola][.] 11 LTL EXCL 34/1196 6/2000 DLCround-PT-10a-LTLFireability-02 892351 m, 24613 m/sec, 35474810 t fired, .
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[lola][.] 11 LTL EXCL 39/1196 7/2000 DLCround-PT-10a-LTLFireability-02 1023060 m, 26141 m/sec, 40740184 t fired, .
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[lola][.] 11 LTL EXCL 49/1196 9/2000 DLCround-PT-10a-LTLFireability-02 1277711 m, 25316 m/sec, 51172980 t fired, .
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[lola][.] 11 LTL EXCL 74/1196 13/2000 DLCround-PT-10a-LTLFireability-02 1889120 m, 24343 m/sec, 76398745 t fired, .
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[lola][.] 11 LTL EXCL 79/1196 13/2000 DLCround-PT-10a-LTLFireability-02 1999521 m, 22080 m/sec, 80996038 t fired, .
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[lola][.] 11 LTL EXCL 89/1196 15/2000 DLCround-PT-10a-LTLFireability-02 2238156 m, 23886 m/sec, 90950315 t fired, .
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[lola][.] 11 LTL EXCL 189/1196 31/2000 DLCround-PT-10a-LTLFireability-02 4655062 m, 23408 m/sec, 191650819 t fired, .
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[lola][.] 11 LTL EXCL 304/1196 48/2000 DLCround-PT-10a-LTLFireability-02 7385101 m, 23671 m/sec, 306181840 t fired, .
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[lola][.] 11 LTL EXCL 819/1196 127/2000 DLCround-PT-10a-LTLFireability-02 19502634 m, 22948 m/sec, 816935425 t fired, .
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[lola][.]
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[lola][.] 11 LTL EXCL 824/1196 128/2000 DLCround-PT-10a-LTLFireability-02 19617175 m, 22908 m/sec, 821788969 t fired, .
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[lola][.] 11 LTL EXCL 829/1196 129/2000 DLCround-PT-10a-LTLFireability-02 19738784 m, 24321 m/sec, 826794113 t fired, .
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[lola][.] 11 LTL EXCL 834/1196 129/2000 DLCround-PT-10a-LTLFireability-02 19854493 m, 23141 m/sec, 831660511 t fired, .
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[lola][.] 11 LTL EXCL 839/1196 130/2000 DLCround-PT-10a-LTLFireability-02 19967331 m, 22567 m/sec, 836434619 t fired, .
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[lola][.] 11 LTL EXCL 844/1196 131/2000 DLCround-PT-10a-LTLFireability-02 20084859 m, 23505 m/sec, 841357665 t fired, .
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[lola][.] 11 LTL EXCL 849/1196 132/2000 DLCround-PT-10a-LTLFireability-02 20205369 m, 24102 m/sec, 846328400 t fired, .
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[lola][.] 11 LTL EXCL 854/1196 132/2000 DLCround-PT-10a-LTLFireability-02 20322578 m, 23441 m/sec, 851220763 t fired, .
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[lola][.] 11 LTL EXCL 859/1196 133/2000 DLCround-PT-10a-LTLFireability-02 20438972 m, 23278 m/sec, 856104379 t fired, .
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[lola][.] 11 LTL EXCL 864/1196 134/2000 DLCround-PT-10a-LTLFireability-02 20553876 m, 22980 m/sec, 860956102 t fired, .
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/home/mcc/BenchKit/BenchKit_head.sh: line 23: 408 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-10a"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is DLCround-PT-10a, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r115-smll-171624276600228"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-10a.tgz
mv DLCround-PT-10a execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;