About the Execution of LoLA for DLCround-PT-08a
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
16200.968 | 691435.00 | 667426.00 | 2349.60 | ?????????F?????F | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r115-smll-171624276600194.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is DLCround-PT-08a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r115-smll-171624276600194
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 940K
-rw-r--r-- 1 mcc users 7.3K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 81K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.6K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 49K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Apr 22 14:38 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Apr 22 14:38 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Apr 22 14:38 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 22 14:38 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.8K Apr 13 15:30 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 106K Apr 13 15:30 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.5K Apr 13 14:56 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 84K Apr 13 14:56 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 22 14:38 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Apr 22 14:38 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 4 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 479K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-08a-CTLFireability-2024-00
FORMULA_NAME DLCround-PT-08a-CTLFireability-2024-01
FORMULA_NAME DLCround-PT-08a-CTLFireability-2024-02
FORMULA_NAME DLCround-PT-08a-CTLFireability-2024-03
FORMULA_NAME DLCround-PT-08a-CTLFireability-2024-04
FORMULA_NAME DLCround-PT-08a-CTLFireability-2024-05
FORMULA_NAME DLCround-PT-08a-CTLFireability-2024-06
FORMULA_NAME DLCround-PT-08a-CTLFireability-2024-07
FORMULA_NAME DLCround-PT-08a-CTLFireability-2024-08
FORMULA_NAME DLCround-PT-08a-CTLFireability-2024-09
FORMULA_NAME DLCround-PT-08a-CTLFireability-2024-10
FORMULA_NAME DLCround-PT-08a-CTLFireability-2024-11
FORMULA_NAME DLCround-PT-08a-CTLFireability-2023-12
FORMULA_NAME DLCround-PT-08a-CTLFireability-2023-13
FORMULA_NAME DLCround-PT-08a-CTLFireability-2023-14
FORMULA_NAME DLCround-PT-08a-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717077187243
FORMULA DLCround-PT-08a-CTLFireability-2024-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-08a-CTLFireability-2023-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717077878678
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 91 (type SKEL/EQUN) for 13 DLCround-PT-08a-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 89 (type SKEL/SRCH) for 13 DLCround-PT-08a-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 89 (type SKEL/SRCH) for DLCround-PT-08a-CTLFireability-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 4
[[35mlola[0m][I] fired transitions : 3
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 91 (type EQUN) for DLCround-PT-08a-CTLFireability-2024-03 (obsolete)
[[35mlola[0m][I] FINISHED task # 91 (type SKEL/EQUN) for DLCround-PT-08a-CTLFireability-2024-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 92 (type SKEL/SRCH) for 13 DLCround-PT-08a-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 92 (type SKEL/SRCH) for DLCround-PT-08a-CTLFireability-2024-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] NOTDEADLOCKFREE
[*** LOG ERROR #0001 ***] [2024-05-30 13:53:08] [status_logger] string pointer is null
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 74 (type EXCL) for 71 DLCround-PT-08a-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 102 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 74 (type EXCL) for DLCround-PT-08a-CTLFireability-2023-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 94 (type SKEL/FNDP) for 55 DLCround-PT-08a-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 95 (type SKEL/EQUN) for 55 DLCround-PT-08a-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 96 (type SKEL/SRCH) for 55 DLCround-PT-08a-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 95 (type SKEL/EQUN) for DLCround-PT-08a-CTLFireability-2024-09
[[35mlola[0m][I] result : false
[[35mlola[0m][W] CANCELED task # 94 (type FNDP) for DLCround-PT-08a-CTLFireability-2024-09 (obsolete)
[[35mlola[0m][W] CANCELED task # 96 (type SRCH) for DLCround-PT-08a-CTLFireability-2024-09 (obsolete)
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 DLCround-PT-08a-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 116 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 94 (type SKEL/FNDP) for DLCround-PT-08a-CTLFireability-2024-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] LAUNCH task # 100 (type EQUN) for 32 DLCround-PT-08a-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 104 (type EQUN) for 32 DLCround-PT-08a-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 113 (type EQUN) for 13 DLCround-PT-08a-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 104 (type EQUN) for DLCround-PT-08a-CTLFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 103 (type FNDP) for 81 DLCround-PT-08a-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 103 (type FNDP) for DLCround-PT-08a-CTLFireability-2023-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] LAUNCH task # 116 (type EQUN) for 13 DLCround-PT-08a-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 113 (type EQUN) for DLCround-PT-08a-CTLFireability-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 119 (type EQUN) for 13 DLCround-PT-08a-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 100 (type EQUN) for DLCround-PT-08a-CTLFireability-2024-04
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 116 (type EQUN) for DLCround-PT-08a-CTLFireability-2024-03
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 119 (type EQUN) for DLCround-PT-08a-CTLFireability-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 123 (type EQUN) for 6 DLCround-PT-08a-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 125 (type EQUN) for 6 DLCround-PT-08a-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 126 (type SKEL/SRCH) for 58 DLCround-PT-08a-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 126 (type SKEL/SRCH) for DLCround-PT-08a-CTLFireability-2024-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] FINISHED task # 125 (type EQUN) for DLCround-PT-08a-CTLFireability-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 123 (type EQUN) for DLCround-PT-08a-CTLFireability-2024-02
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 127 (type SKEL/SRCH) for 71 DLCround-PT-08a-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 127 (type SKEL/SRCH) for DLCround-PT-08a-CTLFireability-2023-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 4 0 0 10 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 4/179 1/2000 DLCround-PT-08a-CTLFireability-2024-00 187317 m, 37463 m/sec, 5642728 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 6 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 4 0 0 10 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 9/179 2/2000 DLCround-PT-08a-CTLFireability-2024-00 435617 m, 49660 m/sec, 13096137 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 11 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 4 0 0 10 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 14/179 3/2000 DLCround-PT-08a-CTLFireability-2024-00 677190 m, 48314 m/sec, 20533975 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 16 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 4 0 0 10 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 19/179 4/2000 DLCround-PT-08a-CTLFireability-2024-00 918310 m, 48224 m/sec, 27834080 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 21 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 4 0 0 10 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 24/179 5/2000 DLCround-PT-08a-CTLFireability-2024-00 1144525 m, 45243 m/sec, 34765838 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 26 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 4 0 0 10 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 29/179 6/2000 DLCround-PT-08a-CTLFireability-2024-00 1363268 m, 43748 m/sec, 41712703 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 31 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 4 0 0 10 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 34/179 7/2000 DLCround-PT-08a-CTLFireability-2024-00 1574409 m, 42228 m/sec, 48659731 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 36 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 4 0 0 10 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 39/179 8/2000 DLCround-PT-08a-CTLFireability-2024-00 1790655 m, 43249 m/sec, 55704271 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 41 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 4 0 0 10 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 44/179 9/2000 DLCround-PT-08a-CTLFireability-2024-00 2013508 m, 44570 m/sec, 62981386 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 46 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 4 0 0 10 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 49/179 10/2000 DLCround-PT-08a-CTLFireability-2024-00 2224200 m, 42138 m/sec, 70106775 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 51 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 4 0 0 10 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 54/179 11/2000 DLCround-PT-08a-CTLFireability-2024-00 2446609 m, 44481 m/sec, 77317940 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 56 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 4 0 0 10 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 59/179 12/2000 DLCround-PT-08a-CTLFireability-2024-00 2691070 m, 48892 m/sec, 84769250 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 61 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 4 0 0 10 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 64/179 12/2000 DLCround-PT-08a-CTLFireability-2024-00 2927586 m, 47303 m/sec, 91998787 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 66 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 4 0 0 10 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 69/179 13/2000 DLCround-PT-08a-CTLFireability-2024-00 3152015 m, 44885 m/sec, 99220209 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 71 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 4 0 0 10 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 74/179 14/2000 DLCround-PT-08a-CTLFireability-2024-00 3372285 m, 44054 m/sec, 106252148 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 76 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 4 0 0 10 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 79/179 15/2000 DLCround-PT-08a-CTLFireability-2024-00 3607590 m, 47061 m/sec, 113462404 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 81 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 4 0 0 10 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 84/179 16/2000 DLCround-PT-08a-CTLFireability-2024-00 3841249 m, 46731 m/sec, 120548135 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 86 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 4 0 0 10 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 89/179 17/2000 DLCround-PT-08a-CTLFireability-2024-00 4065082 m, 44766 m/sec, 127542144 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 91 secs. Pages in use: 17
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 4 0 0 10 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 94/179 18/2000 DLCround-PT-08a-CTLFireability-2024-00 4279618 m, 42907 m/sec, 134397661 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 96 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 4 0 0 10 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 99/179 19/2000 DLCround-PT-08a-CTLFireability-2024-00 4485480 m, 41172 m/sec, 141185351 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 101 secs. Pages in use: 19
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 4 0 0 10 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 104/179 20/2000 DLCround-PT-08a-CTLFireability-2024-00 4690939 m, 41091 m/sec, 148079391 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 106 secs. Pages in use: 20
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 4 0 0 10 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 109/179 21/2000 DLCround-PT-08a-CTLFireability-2024-00 4892676 m, 40347 m/sec, 154947959 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 111 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 4 0 0 10 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 114/179 21/2000 DLCround-PT-08a-CTLFireability-2024-00 5096833 m, 40831 m/sec, 161931354 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 116 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 4 0 0 10 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 119/179 22/2000 DLCround-PT-08a-CTLFireability-2024-00 5302605 m, 41154 m/sec, 168846453 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 121 secs. Pages in use: 22
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 4 0 0 10 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 124/179 23/2000 DLCround-PT-08a-CTLFireability-2024-00 5507989 m, 41076 m/sec, 175627250 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 126 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 4 0 0 10 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 129/179 24/2000 DLCround-PT-08a-CTLFireability-2024-00 5709972 m, 40396 m/sec, 182515462 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 131 secs. Pages in use: 24
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 4 0 0 10 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 134/179 25/2000 DLCround-PT-08a-CTLFireability-2024-00 5914828 m, 40971 m/sec, 189414691 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 136 secs. Pages in use: 25
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 4 0 0 10 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 139/179 26/2000 DLCround-PT-08a-CTLFireability-2024-00 6120031 m, 41040 m/sec, 196308429 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 141 secs. Pages in use: 26
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 4 0 0 10 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 144/179 26/2000 DLCround-PT-08a-CTLFireability-2024-00 6318334 m, 39660 m/sec, 203105320 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 146 secs. Pages in use: 26
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 4 0 0 10 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 149/179 27/2000 DLCround-PT-08a-CTLFireability-2024-00 6529728 m, 42278 m/sec, 210189840 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 151 secs. Pages in use: 27
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 4 0 0 10 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 154/179 28/2000 DLCround-PT-08a-CTLFireability-2024-00 6758751 m, 45804 m/sec, 217343494 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 156 secs. Pages in use: 28
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 4 0 0 10 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 159/179 29/2000 DLCround-PT-08a-CTLFireability-2024-00 6971401 m, 42530 m/sec, 224232117 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 161 secs. Pages in use: 29
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 4 0 0 10 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 164/179 30/2000 DLCround-PT-08a-CTLFireability-2024-00 7186049 m, 42929 m/sec, 231165651 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 166 secs. Pages in use: 30
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 4 0 0 10 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 169/179 31/2000 DLCround-PT-08a-CTLFireability-2024-00 7420343 m, 46858 m/sec, 238287257 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 171 secs. Pages in use: 31
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 4 0 0 10 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 174/179 32/2000 DLCround-PT-08a-CTLFireability-2024-00 7655433 m, 47018 m/sec, 245533903 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 176 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 4 0 0 10 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 179/179 33/2000 DLCround-PT-08a-CTLFireability-2024-00 7851452 m, 39203 m/sec, 252454579 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 181 secs. Pages in use: 33
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 1 (type EXCL) for DLCround-PT-08a-CTLFireability-2024-00 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 4 0 0 10 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 186 secs. Pages in use: 33
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 111 (type EXCL) for 13 DLCround-PT-08a-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 179 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 DLCround-PT-08a-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 3414 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 111 (type EXCL) for DLCround-PT-08a-CTLFireability-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 4
[[35mlola[0m][I] fired transitions : 3
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 5/200 2/5 DLCround-PT-08a-CTLFireability-2024-00 254571 m, -1519376 m/sec, 7618904 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 191 secs. Pages in use: 35
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 10/200 3/5 DLCround-PT-08a-CTLFireability-2024-00 494751 m, 48036 m/sec, 14949180 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 196 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 15/200 4/5 DLCround-PT-08a-CTLFireability-2024-00 737828 m, 48615 m/sec, 22380745 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 201 secs. Pages in use: 37
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 20/200 4/5 DLCround-PT-08a-CTLFireability-2024-00 976659 m, 47766 m/sec, 29614222 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 206 secs. Pages in use: 37
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 25/200 5/5 DLCround-PT-08a-CTLFireability-2024-00 1200618 m, 44791 m/sec, 36535462 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 211 secs. Pages in use: 38
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 1 (type EXCL) for DLCround-PT-08a-CTLFireability-2024-00 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-13: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 216 secs. Pages in use: 38
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 76 (type EXCL) for 71 DLCround-PT-08a-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 76 (type EXCL) for DLCround-PT-08a-CTLFireability-2023-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 69 (type EXCL) for 68 DLCround-PT-08a-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 225 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 5/225 1/2000 DLCround-PT-08a-CTLFireability-2023-12 229347 m, 45869 m/sec, 5301067 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 221 secs. Pages in use: 38
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 10/225 2/2000 DLCround-PT-08a-CTLFireability-2023-12 458069 m, 45744 m/sec, 10450076 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 226 secs. Pages in use: 38
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 15/225 3/2000 DLCround-PT-08a-CTLFireability-2023-12 675371 m, 43460 m/sec, 15491142 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 231 secs. Pages in use: 38
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 20/225 4/2000 DLCround-PT-08a-CTLFireability-2023-12 894691 m, 43864 m/sec, 20480239 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 236 secs. Pages in use: 38
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 25/225 5/2000 DLCround-PT-08a-CTLFireability-2023-12 1108913 m, 42844 m/sec, 25395610 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 241 secs. Pages in use: 38
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 30/225 6/2000 DLCround-PT-08a-CTLFireability-2023-12 1321818 m, 42581 m/sec, 30277881 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 246 secs. Pages in use: 39
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 35/225 7/2000 DLCround-PT-08a-CTLFireability-2023-12 1533487 m, 42333 m/sec, 35135700 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 251 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 40/225 8/2000 DLCround-PT-08a-CTLFireability-2023-12 1738914 m, 41085 m/sec, 40014141 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 256 secs. Pages in use: 41
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 45/225 8/2000 DLCround-PT-08a-CTLFireability-2023-12 1874845 m, 27186 m/sec, 45250595 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 261 secs. Pages in use: 41
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 50/225 9/2000 DLCround-PT-08a-CTLFireability-2023-12 2010283 m, 27087 m/sec, 50397376 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 266 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 55/225 9/2000 DLCround-PT-08a-CTLFireability-2023-12 2141889 m, 26321 m/sec, 55518391 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 271 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 60/225 10/2000 DLCround-PT-08a-CTLFireability-2023-12 2273270 m, 26276 m/sec, 60596586 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 276 secs. Pages in use: 43
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 65/225 10/2000 DLCround-PT-08a-CTLFireability-2023-12 2406007 m, 26547 m/sec, 65710224 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 281 secs. Pages in use: 43
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 70/225 11/2000 DLCround-PT-08a-CTLFireability-2023-12 2540726 m, 26943 m/sec, 70799279 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 286 secs. Pages in use: 44
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 75/225 12/2000 DLCround-PT-08a-CTLFireability-2023-12 2668951 m, 25645 m/sec, 75812459 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 291 secs. Pages in use: 45
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 80/225 12/2000 DLCround-PT-08a-CTLFireability-2023-12 2796080 m, 25425 m/sec, 80838955 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 296 secs. Pages in use: 45
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 85/225 13/2000 DLCround-PT-08a-CTLFireability-2023-12 2928647 m, 26513 m/sec, 85970873 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 301 secs. Pages in use: 46
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 90/225 13/2000 DLCround-PT-08a-CTLFireability-2023-12 3067825 m, 27835 m/sec, 91366291 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 306 secs. Pages in use: 46
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 95/225 14/2000 DLCround-PT-08a-CTLFireability-2023-12 3240500 m, 34535 m/sec, 96573448 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 311 secs. Pages in use: 47
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 100/225 15/2000 DLCround-PT-08a-CTLFireability-2023-12 3450761 m, 42052 m/sec, 101503431 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 316 secs. Pages in use: 48
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 105/225 15/2000 DLCround-PT-08a-CTLFireability-2023-12 3593882 m, 28624 m/sec, 106622816 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 321 secs. Pages in use: 48
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 110/225 16/2000 DLCround-PT-08a-CTLFireability-2023-12 3725088 m, 26241 m/sec, 111607215 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 326 secs. Pages in use: 49
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 115/225 16/2000 DLCround-PT-08a-CTLFireability-2023-12 3854834 m, 25949 m/sec, 116636925 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 331 secs. Pages in use: 49
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 120/225 17/2000 DLCround-PT-08a-CTLFireability-2023-12 3997692 m, 28571 m/sec, 121693182 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 336 secs. Pages in use: 50
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 125/225 18/2000 DLCround-PT-08a-CTLFireability-2023-12 4175812 m, 35624 m/sec, 126612568 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 341 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 130/225 18/2000 DLCround-PT-08a-CTLFireability-2023-12 4309250 m, 26687 m/sec, 131809091 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 346 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 135/225 19/2000 DLCround-PT-08a-CTLFireability-2023-12 4451384 m, 28426 m/sec, 137310618 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 351 secs. Pages in use: 52
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 140/225 19/2000 DLCround-PT-08a-CTLFireability-2023-12 4593169 m, 28357 m/sec, 142692899 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 356 secs. Pages in use: 52
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 145/225 20/2000 DLCround-PT-08a-CTLFireability-2023-12 4731679 m, 27702 m/sec, 148035236 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 361 secs. Pages in use: 53
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 150/225 21/2000 DLCround-PT-08a-CTLFireability-2023-12 4869337 m, 27531 m/sec, 153317018 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 366 secs. Pages in use: 54
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 155/225 21/2000 DLCround-PT-08a-CTLFireability-2023-12 5004896 m, 27111 m/sec, 158590910 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 371 secs. Pages in use: 54
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 160/225 22/2000 DLCround-PT-08a-CTLFireability-2023-12 5137899 m, 26600 m/sec, 163837666 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 376 secs. Pages in use: 55
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 165/225 22/2000 DLCround-PT-08a-CTLFireability-2023-12 5271407 m, 26701 m/sec, 169049392 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 381 secs. Pages in use: 55
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 170/225 23/2000 DLCround-PT-08a-CTLFireability-2023-12 5407554 m, 27229 m/sec, 174287138 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 386 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 175/225 23/2000 DLCround-PT-08a-CTLFireability-2023-12 5543962 m, 27281 m/sec, 179482246 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 391 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 180/225 24/2000 DLCround-PT-08a-CTLFireability-2023-12 5682995 m, 27806 m/sec, 184676932 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 396 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 185/225 25/2000 DLCround-PT-08a-CTLFireability-2023-12 5820185 m, 27438 m/sec, 189948861 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 401 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 190/225 25/2000 DLCround-PT-08a-CTLFireability-2023-12 5987979 m, 33558 m/sec, 195111505 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 406 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 195/225 26/2000 DLCround-PT-08a-CTLFireability-2023-12 6188530 m, 40110 m/sec, 200122426 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 411 secs. Pages in use: 59
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 200/225 27/2000 DLCround-PT-08a-CTLFireability-2023-12 6404434 m, 43180 m/sec, 205016182 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 416 secs. Pages in use: 60
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 205/225 28/2000 DLCround-PT-08a-CTLFireability-2023-12 6595877 m, 38288 m/sec, 209896328 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 421 secs. Pages in use: 61
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 210/225 28/2000 DLCround-PT-08a-CTLFireability-2023-12 6732105 m, 27245 m/sec, 215157501 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 426 secs. Pages in use: 61
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 215/225 29/2000 DLCround-PT-08a-CTLFireability-2023-12 6865966 m, 26772 m/sec, 220314903 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 431 secs. Pages in use: 62
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 220/225 29/2000 DLCround-PT-08a-CTLFireability-2023-12 6979794 m, 22765 m/sec, 225476352 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 436 secs. Pages in use: 62
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 225/225 30/2000 DLCround-PT-08a-CTLFireability-2023-12 7108401 m, 25721 m/sec, 230614489 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 441 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 69 (type EXCL) for DLCround-PT-08a-CTLFireability-2023-12 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-10: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 446 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 61 (type EXCL) for 58 DLCround-PT-08a-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 225 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 69 (type EXCL) for 68 DLCround-PT-08a-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 3154 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 61 (type EXCL) for DLCround-PT-08a-CTLFireability-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 106
[[35mlola[0m][I] fired transitions : 366
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 5/225 1/5 DLCround-PT-08a-CTLFireability-2023-12 225131 m, -1376654 m/sec, 5208879 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 451 secs. Pages in use: 65
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 10/225 2/5 DLCround-PT-08a-CTLFireability-2023-12 453884 m, 45750 m/sec, 10332083 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 456 secs. Pages in use: 65
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 15/225 3/5 DLCround-PT-08a-CTLFireability-2023-12 669235 m, 43070 m/sec, 15364066 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 461 secs. Pages in use: 66
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 20/225 4/5 DLCround-PT-08a-CTLFireability-2023-12 888101 m, 43773 m/sec, 20326624 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 466 secs. Pages in use: 67
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 CTL EXCL 25/225 5/5 DLCround-PT-08a-CTLFireability-2023-12 1102144 m, 42808 m/sec, 25230560 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 471 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 69 (type EXCL) for DLCround-PT-08a-CTLFireability-2023-12 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 476 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 53 (type EXCL) for 52 DLCround-PT-08a-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 240 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 CTL EXCL 5/240 2/2000 DLCround-PT-08a-CTLFireability-2024-08 348920 m, 69784 m/sec, 5550460 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 481 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 CTL EXCL 10/240 3/2000 DLCround-PT-08a-CTLFireability-2024-08 674696 m, 65155 m/sec, 10829276 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 486 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 CTL EXCL 15/240 5/2000 DLCround-PT-08a-CTLFireability-2024-08 997404 m, 64541 m/sec, 16073160 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 491 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 CTL EXCL 20/240 6/2000 DLCround-PT-08a-CTLFireability-2024-08 1324305 m, 65380 m/sec, 21386276 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 496 secs. Pages in use: 69
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 CTL EXCL 25/240 7/2000 DLCround-PT-08a-CTLFireability-2024-08 1640983 m, 63335 m/sec, 26577751 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 501 secs. Pages in use: 70
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 CTL EXCL 30/240 9/2000 DLCround-PT-08a-CTLFireability-2024-08 1949225 m, 61648 m/sec, 31612201 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 506 secs. Pages in use: 72
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 CTL EXCL 35/240 10/2000 DLCround-PT-08a-CTLFireability-2024-08 2264336 m, 63022 m/sec, 36704944 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 511 secs. Pages in use: 73
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 CTL EXCL 40/240 11/2000 DLCround-PT-08a-CTLFireability-2024-08 2570065 m, 61145 m/sec, 41736828 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 516 secs. Pages in use: 74
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 CTL EXCL 45/240 12/2000 DLCround-PT-08a-CTLFireability-2024-08 2869513 m, 59889 m/sec, 46707799 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 521 secs. Pages in use: 75
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 CTL EXCL 50/240 14/2000 DLCround-PT-08a-CTLFireability-2024-08 3173751 m, 60847 m/sec, 51746999 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 526 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 CTL EXCL 55/240 15/2000 DLCround-PT-08a-CTLFireability-2024-08 3485065 m, 62262 m/sec, 56768840 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 531 secs. Pages in use: 78
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 CTL EXCL 60/240 16/2000 DLCround-PT-08a-CTLFireability-2024-08 3788955 m, 60778 m/sec, 61695174 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 536 secs. Pages in use: 79
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 CTL EXCL 65/240 17/2000 DLCround-PT-08a-CTLFireability-2024-08 4085499 m, 59308 m/sec, 66666332 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 541 secs. Pages in use: 80
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 CTL EXCL 70/240 19/2000 DLCround-PT-08a-CTLFireability-2024-08 4384404 m, 59781 m/sec, 71610494 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 546 secs. Pages in use: 82
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 CTL EXCL 75/240 20/2000 DLCround-PT-08a-CTLFireability-2024-08 4685915 m, 60302 m/sec, 76537720 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 551 secs. Pages in use: 83
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 CTL EXCL 80/240 21/2000 DLCround-PT-08a-CTLFireability-2024-08 4972991 m, 57415 m/sec, 81363425 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 556 secs. Pages in use: 84
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 CTL EXCL 85/240 22/2000 DLCround-PT-08a-CTLFireability-2024-08 5258357 m, 57073 m/sec, 86131046 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 561 secs. Pages in use: 85
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 CTL EXCL 90/240 24/2000 DLCround-PT-08a-CTLFireability-2024-08 5585313 m, 65391 m/sec, 91379190 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 566 secs. Pages in use: 87
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 CTL EXCL 95/240 25/2000 DLCround-PT-08a-CTLFireability-2024-08 5903494 m, 63636 m/sec, 96558825 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 571 secs. Pages in use: 88
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 CTL EXCL 100/240 26/2000 DLCround-PT-08a-CTLFireability-2024-08 6219808 m, 63262 m/sec, 101638478 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 576 secs. Pages in use: 89
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 CTL EXCL 105/240 27/2000 DLCround-PT-08a-CTLFireability-2024-08 6532148 m, 62468 m/sec, 106761017 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 581 secs. Pages in use: 90
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 CTL EXCL 110/240 29/2000 DLCround-PT-08a-CTLFireability-2024-08 6839761 m, 61522 m/sec, 111837697 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 586 secs. Pages in use: 92
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 CTL EXCL 115/240 30/2000 DLCround-PT-08a-CTLFireability-2024-08 7144847 m, 61017 m/sec, 116866534 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 591 secs. Pages in use: 93
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 CTL EXCL 120/240 31/2000 DLCround-PT-08a-CTLFireability-2024-08 7463653 m, 63761 m/sec, 122002698 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 596 secs. Pages in use: 94
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 CTL EXCL 125/240 33/2000 DLCround-PT-08a-CTLFireability-2024-08 7764971 m, 60263 m/sec, 126954122 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 601 secs. Pages in use: 96
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 CTL EXCL 130/240 34/2000 DLCround-PT-08a-CTLFireability-2024-08 8052431 m, 57492 m/sec, 131815881 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 606 secs. Pages in use: 97
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 CTL EXCL 135/240 35/2000 DLCround-PT-08a-CTLFireability-2024-08 8342745 m, 58062 m/sec, 136626941 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 611 secs. Pages in use: 98
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 CTL EXCL 140/240 36/2000 DLCround-PT-08a-CTLFireability-2024-08 8627980 m, 57047 m/sec, 141485841 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 616 secs. Pages in use: 99
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 CTL EXCL 145/240 37/2000 DLCround-PT-08a-CTLFireability-2024-08 8920324 m, 58468 m/sec, 146298256 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 621 secs. Pages in use: 100
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 CTL EXCL 150/240 38/2000 DLCround-PT-08a-CTLFireability-2024-08 9207878 m, 57510 m/sec, 151088513 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 626 secs. Pages in use: 101
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 CTL EXCL 155/240 40/2000 DLCround-PT-08a-CTLFireability-2024-08 9517515 m, 61927 m/sec, 156061112 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 631 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 CTL EXCL 160/240 41/2000 DLCround-PT-08a-CTLFireability-2024-08 9815992 m, 59695 m/sec, 160947711 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 636 secs. Pages in use: 104
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 CTL EXCL 165/240 42/2000 DLCround-PT-08a-CTLFireability-2024-08 10094872 m, 55776 m/sec, 165600393 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 641 secs. Pages in use: 105
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 CTL EXCL 170/240 43/2000 DLCround-PT-08a-CTLFireability-2024-08 10380829 m, 57191 m/sec, 170367240 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 646 secs. Pages in use: 106
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 CTL EXCL 175/240 45/2000 DLCround-PT-08a-CTLFireability-2024-08 10671292 m, 58092 m/sec, 175154046 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 651 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 CTL EXCL 180/240 46/2000 DLCround-PT-08a-CTLFireability-2024-08 10943159 m, 54373 m/sec, 179735580 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 656 secs. Pages in use: 109
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2024-09: EF false skeleton: state equation[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2024-10: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-08a-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-08a-CTLFireability-2023-15: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-03: CONJ 0 1 0 0 11 0 0 2
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-04: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-07: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-08a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 CTL EXCL 185/240 47/2000 DLCround-PT-08a-CTLFireability-2024-08 11224639 m, 56296 m/sec, 184404793 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 661 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 402 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-08a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is DLCround-PT-08a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r115-smll-171624276600194"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-08a.tgz
mv DLCround-PT-08a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;