MCC'2024- Execution of r115-smll-171624276500188

About the Execution of LoLA for DLCround-PT-07b

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
16198.300	818382.00	833813.00	3066.60	F???FF???F?F??F?	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r115-smll-171624276500188.qcow2',
Waiting for the VM to be ready (probing ssh)
.......................................................
=================================
Generated by BenchKit 2-5568
Executing tool lola
Input is DLCround-PT-07b, examination is LTLFireabi
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r115-smll-171624276500188
=======================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.5M
-rw-r--r-- 1 mcc users 7.7K May 14 13:22 CTLCardinality
-rw-r--r-- 1 mcc users 87K May 14 13:22 CTLCardinality
-rw-r--r-- 1 mcc users 5.5K May 14 13:22 CTLFireability
-rw-r--r-- 1 mcc users 48K May 14 13:22 CTLFireability
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropert
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropert
-rw-r--r-- 1 mcc users 3.9K Apr 22 14:38 LTLCardinality
-rw-r--r-- 1 mcc users 27K Apr 22 14:38 LTLCardinality
-rw-r--r-- 1 mcc users 2.3K Apr 22 14:38 LTLFireability
-rw-r--r-- 1 mcc users 18K Apr 22 14:38 LTLFireability
-rw-r--r-- 1 mcc users 14K Apr 13 12:32 ReachabilityCa
-rw-r--r-- 1 mcc users 154K Apr 13 12:32 ReachabilityCa
-rw-r--r-- 1 mcc users 6.5K Apr 13 12:31 ReachabilityFi
-rw-r--r-- 1 mcc users 51K Apr 13 12:31 ReachabilityFi
-rw-r--r-- 1 mcc users 1.6K Apr 22 14:38 UpperBounds.tx
-rw-r--r-- 1 mcc users 3.6K Apr 22 14:38 UpperBounds.xm
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 4 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 963K May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from
FORMULA_NAME DLCround-PT-07b-LTLFireability-00
FORMULA_NAME DLCround-PT-07b-LTLFireability-01
FORMULA_NAME DLCround-PT-07b-LTLFireability-02
FORMULA_NAME DLCround-PT-07b-LTLFireability-03
FORMULA_NAME DLCround-PT-07b-LTLFireability-04
FORMULA_NAME DLCround-PT-07b-LTLFireability-05
FORMULA_NAME DLCround-PT-07b-LTLFireability-06
FORMULA_NAME DLCround-PT-07b-LTLFireability-07
FORMULA_NAME DLCround-PT-07b-LTLFireability-08
FORMULA_NAME DLCround-PT-07b-LTLFireability-09
FORMULA_NAME DLCround-PT-07b-LTLFireability-10
FORMULA_NAME DLCround-PT-07b-LTLFireability-11
FORMULA_NAME DLCround-PT-07b-LTLFireability-12
FORMULA_NAME DLCround-PT-07b-LTLFireability-13
FORMULA_NAME DLCround-PT-07b-LTLFireability-14
FORMULA_NAME DLCround-PT-07b-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1717075681405

FORMULA DLCround-PT-07b-LTLFireability-14
FORMULA DLCround-PT-07b-LTLFireability-00
FORMULA DLCround-PT-07b-LTLFireability-05
FORMULA DLCround-PT-07b-LTLFireability-04
FORMULA DLCround-PT-07b-LTLFireability-09
FORMULA DLCround-PT-07b-LTLFireability-11

BK_STOP 1717076499787

--------------------
content from stderr:

[[35mlola[0m][I] LoLA will run for 3600 seconds
[[35mlola[0m][W] [1m[33munknown unit in memory
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmln
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition
[[35mlola[0m][I] closed [1m[34mnet[0m file
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlfo
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m
[[35mlola[0m][I] LAUNCH task # 57 (type CNST)
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 57 (type
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 3 (type CNST)
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 3 (type CNST)
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 22 (type CNST)
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 22 (type
[[35mlola[0m][I] result : false
[[35mlola[0m][I] Rule S: 0 transitions removed,0
[*** LOG ERROR #0001 ***] [2024-05-30 13:28:14]
[[35mlola[0m][I] LAUNCH task # 17 (type EXCL)
[[35mlola[0m][I] time limit : 275 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 17 (type
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 75 (type EXCL)
[[35mlola[0m][I] time limit : 298 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 73 (type FNDP)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 74 (type EQUN)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 75 (type
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][W] CANCELED task # 73 (type
[[35mlola[0m][W] CANCELED task # 74 (type
[[35mlola[0m][I] LAUNCH task # 46 (type EXCL)
[[35mlola[0m][I] time limit : 325 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 73 (type
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] FINISHED task # 46 (type
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-05:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-09:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-01:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-02:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-03:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-06:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-07:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-08:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-10:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-12:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-13:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs.
[[35mlola[0m][.] # running tasks: 0 of 4.
[[35mlola[0m][I] FINISHED task # 74 (type
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 70 (type EXCL)
[[35mlola[0m][I] time limit : 358 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 70 (type
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 34 (type EXCL)
[[35mlola[0m][I] time limit : 398 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-05:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-09:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-14:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-01:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-02:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-03:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-06:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-07:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-08:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-10:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-12:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-13:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 34 LTL EXCL 2/398
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs.
[[35mlola[0m][.] # running tasks: 1 of 4.
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-05:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-09:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-14:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-01:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-02:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-03:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-06:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-07:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-08:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-10:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-12:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-13:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 34 LTL EXCL 7/398
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs.
[[35mlola[0m][.] # running tasks: 1 of 4.
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-05:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-09:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-14:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-01:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-02:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-03:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-06:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-07:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-08:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-10:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-12:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-13:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 34 LTL EXCL 12/398
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs.
[[35mlola[0m][.] # running tasks: 1 of 4.
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-05:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-09:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-14:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-01:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-02:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-03:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-06:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-07:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-08:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-10:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-12:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-13:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 34 LTL EXCL 17/398
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs.
[[35mlola[0m][.] # running tasks: 1 of 4.
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-05:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-09:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-14:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-01:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-02:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-03:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-06:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-07:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-08:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-10:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-12:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-13:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 34 LTL EXCL 22/398
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs.
[[35mlola[0m][.] # running tasks: 1 of 4.
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-05:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-09:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-14:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-01:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-02:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-03:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-06:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-07:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-08:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-10:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-12:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-13:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 34 LTL EXCL 27/398
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs.
[[35mlola[0m][.] # running tasks: 1 of 4.
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-05:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-09:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-14:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-01:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-02:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-03:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-06:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-07:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-08:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-10:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-12:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-13:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 34 LTL EXCL 32/398
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs.
[[35mlola[0m][.] # running tasks: 1 of 4.
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-05:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-09:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-14:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
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[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-00:
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[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-09:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-14:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-01:
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[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-06:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-07:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-08:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-10:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-12:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-13:
[[35mlola[0m][.]
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[[35mlola[0m][.] 34 LTL EXCL 362/398
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 380 secs.
[[35mlola[0m][.] # running tasks: 1 of 4.
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-00:
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[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-05:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-09:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-14:
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[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-01:
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[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-03:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-06:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-07:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-08:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-10:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-12:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-13:
[[35mlola[0m][.]
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[[35mlola[0m][.] 34 LTL EXCL 367/398
[[35mlola[0m][.]
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[[35mlola[0m][.] # running tasks: 1 of 4.
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-00:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-05:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-09:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-14:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-01:
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[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-03:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-06:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-07:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-08:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-10:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-12:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-13:
[[35mlola[0m][.]
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[[35mlola[0m][.] 34 LTL EXCL 372/398
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 390 secs.
[[35mlola[0m][.] # running tasks: 1 of 4.
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-00:
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[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-09:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-14:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-01:
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[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-03:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-06:
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[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-08:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-10:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-12:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-13:
[[35mlola[0m][.]
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[[35mlola[0m][.] 34 LTL EXCL 377/398
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 395 secs.
[[35mlola[0m][.] # running tasks: 1 of 4.
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-00:
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[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-09:
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[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-14:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-01:
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[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-06:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-07:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-08:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-10:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-12:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-13:
[[35mlola[0m][.]
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[[35mlola[0m][.] 34 LTL EXCL 382/398
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 400 secs.
[[35mlola[0m][.] # running tasks: 1 of 4.
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-00:
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[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-01:
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[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-08:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-10:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-12:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-13:
[[35mlola[0m][.]
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[[35mlola[0m][.] 34 LTL EXCL 387/398
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 405 secs.
[[35mlola[0m][.] # running tasks: 1 of 4.
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-00:
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[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-01:
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[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-13:
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[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 410 secs.
[[35mlola[0m][.] # running tasks: 1 of 4.
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-00:
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[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-01:
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[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-03:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-06:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-07:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-08:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-10:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-12:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-13:
[[35mlola[0m][.]
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[[35mlola[0m][.] 34 LTL EXCL 397/398
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 415 secs.
[[35mlola[0m][.] # running tasks: 1 of 4.
[[35mlola[0m][W] CANCELED task # 34 (type
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-00:
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[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-01:
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[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-08:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-10:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-12:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-13:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 420 secs.
[[35mlola[0m][.] # running tasks: 1 of 4.
[[35mlola[0m][I] LAUNCH task # 52 (type EXCL)
[[35mlola[0m][I] time limit : 397 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 34 (type EXCL)
[[35mlola[0m][I] time limit : 3180 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 52 (type
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] CANCELED task # 34 (type
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-00:
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[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-01:
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[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-03:
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[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-07:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-08:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-10:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 425 secs.
[[35mlola[0m][.] # running tasks: 1 of 4.
[[35mlola[0m][I] LAUNCH task # 49 (type EXCL)
[[35mlola[0m][I] time limit : 453 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 49 (type
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 43 (type EXCL)
[[35mlola[0m][I] time limit : 529 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 43 (type
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 37 (type EXCL)
[[35mlola[0m][I] time limit : 635 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-00:
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[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-14:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-01:
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[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-03:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-06:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-07:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-08:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 37 LTL EXCL 5/635
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 430 secs.
[[35mlola[0m][.] # running tasks: 1 of 4.
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-00:
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[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-09:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-14:
[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-01:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-02:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-03:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-06:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-07:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-08:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 37 LTL EXCL 10/635
[[35mlola[0m][.]
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[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-13:
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[[35mlola[0m][.] [1m[31mDLCround-PT-07b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-01:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-02:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-03:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-06:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-07:
[[35mlola[0m][.] DLCround-PT-07b-LTLFireability-08:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 37 LTL EXCL 390/635
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 815 secs.
[[35mlola[0m][.] # running tasks: 1 of 4.
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 407 Killed
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==================================== lity ============== .txt .xml .txt .xml iesDefinition.xml iesVerdict.xml .txt .xml .txt .xml rdinality.txt rdinality.xml reability.txt reability.xml t l (invocation template) text file) FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT at most ([1m[36m--timelimit[0m) specification: using default[0m from [4m[34mmodel.pnml[0m et[0m) net [4m[34mmodel.pnml[0m rmula[0m) from [4m[34mLTLFireability.xml[0m for 54 DLCround-PT-07b-LTLFireability-14 CNST) for DLCround-PT-07b-LTLFireability-14 for 0 DLCround-PT-07b-LTLFireability-00 for DLCround-PT-07b-LTLFireability-00 for 19 DLCround-PT-07b-LTLFireability-05 CNST) for DLCround-PT-07b-LTLFireability-05 places removed [status_logger] string pointer is null for 16 DLCround-PT-07b-LTLFireability-04 EXCL) for DLCround-PT-07b-LTLFireability-04 124 125 0 1 for 39 DLCround-PT-07b-LTLFireability-09 for 39 DLCround-PT-07b-LTLFireability-09 for 39 DLCround-PT-07b-LTLFireability-09 EXCL) for DLCround-PT-07b-LTLFireability-09 3 2 0 1 FNDP) for DLCround-PT-07b-LTLFireability-09 (obsolete) EQUN) for DLCround-PT-07b-LTLFireability-09 (obsolete) for 45 DLCround-PT-07b-LTLFireability-11 FNDP) for DLCround-PT-07b-LTLFireability-09 1 0 0 EXCL) for DLCround-PT-07b-LTLFireability-11 122 122 0 1 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 Visible: 16 EQUN) for DLCround-PT-07b-LTLFireability-09 for 69 DLCround-PT-07b-LTLFireability-15 EXCL) for DLCround-PT-07b-LTLFireability-15 109 109 0 1 for 33 DLCround-PT-07b-LTLFireability-07 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 3/2000 DLCround-PT-07b-LTLFireability-07 121243 m, 24248 m/sec, 130844 t fired, . Pages in use: 3 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 8/2000 DLCround-PT-07b-LTLFireability-07 463056 m, 68362 m/sec, 499161 t fired, . Pages in use: 8 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 13/2000 DLCround-PT-07b-LTLFireability-07 797361 m, 66861 m/sec, 860290 t fired, . Pages in use: 13 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 18/2000 DLCround-PT-07b-LTLFireability-07 1104127 m, 61353 m/sec, 1191867 t fired, . Pages in use: 18 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 22/2000 DLCround-PT-07b-LTLFireability-07 1431483 m, 65471 m/sec, 1545439 t fired, . Pages in use: 22 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 27/2000 DLCround-PT-07b-LTLFireability-07 1759464 m, 65596 m/sec, 1899719 t fired, . Pages in use: 27 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 32/2000 DLCround-PT-07b-LTLFireability-07 2099714 m, 68050 m/sec, 2266556 t fired, . Pages in use: 32 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 37/2000 DLCround-PT-07b-LTLFireability-07 2436664 m, 67390 m/sec, 2630049 t fired, . Pages in use: 37 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 42/2000 DLCround-PT-07b-LTLFireability-07 2767767 m, 66220 m/sec, 2988321 t fired, . Pages in use: 42 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 47/2000 DLCround-PT-07b-LTLFireability-07 3098434 m, 66133 m/sec, 3345997 t fired, . Pages in use: 47 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 52/2000 DLCround-PT-07b-LTLFireability-07 3428245 m, 65962 m/sec, 3702684 t fired, . Pages in use: 52 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 57/2000 DLCround-PT-07b-LTLFireability-07 3752245 m, 64800 m/sec, 4052427 t fired, . Pages in use: 57 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 62/2000 DLCround-PT-07b-LTLFireability-07 4075037 m, 64558 m/sec, 4400144 t fired, . Pages in use: 62 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 66/2000 DLCround-PT-07b-LTLFireability-07 4400178 m, 65028 m/sec, 4751583 t fired, . Pages in use: 66 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 71/2000 DLCround-PT-07b-LTLFireability-07 4720887 m, 64141 m/sec, 5097707 t fired, . Pages in use: 71 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 75/2000 DLCround-PT-07b-LTLFireability-07 5041874 m, 64197 m/sec, 5444043 t fired, . Pages in use: 75 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 80/2000 DLCround-PT-07b-LTLFireability-07 5359449 m, 63515 m/sec, 5786472 t fired, . Pages in use: 80 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 85/2000 DLCround-PT-07b-LTLFireability-07 5681048 m, 64319 m/sec, 6133658 t fired, . Pages in use: 85 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 89/2000 DLCround-PT-07b-LTLFireability-07 6001392 m, 64068 m/sec, 6479969 t fired, . Pages in use: 89 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 94/2000 DLCround-PT-07b-LTLFireability-07 6330219 m, 65765 m/sec, 6835207 t fired, . Pages in use: 94 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 99/2000 DLCround-PT-07b-LTLFireability-07 6667373 m, 67430 m/sec, 7198790 t fired, . Pages in use: 99 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 104/2000 DLCround-PT-07b-LTLFireability-07 6998664 m, 66258 m/sec, 7556660 t fired, . Pages in use: 104 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 109/2000 DLCround-PT-07b-LTLFireability-07 7332784 m, 66824 m/sec, 7919119 t fired, . Pages in use: 109 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 114/2000 DLCround-PT-07b-LTLFireability-07 7670225 m, 67488 m/sec, 8284825 t fired, . Pages in use: 114 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 119/2000 DLCround-PT-07b-LTLFireability-07 8003450 m, 66645 m/sec, 8646237 t fired, . Pages in use: 119 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 124/2000 DLCround-PT-07b-LTLFireability-07 8332434 m, 65796 m/sec, 9002138 t fired, . Pages in use: 124 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 129/2000 DLCround-PT-07b-LTLFireability-07 8658975 m, 65308 m/sec, 9357042 t fired, . Pages in use: 129 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 134/2000 DLCround-PT-07b-LTLFireability-07 8987318 m, 65668 m/sec, 9713860 t fired, . Pages in use: 134 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 138/2000 DLCround-PT-07b-LTLFireability-07 9310122 m, 64560 m/sec, 10064115 t fired, . Pages in use: 138 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 143/2000 DLCround-PT-07b-LTLFireability-07 9635947 m, 65165 m/sec, 10415972 t fired, . Pages in use: 143 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 148/2000 DLCround-PT-07b-LTLFireability-07 9960332 m, 64877 m/sec, 10765928 t fired, . Pages in use: 148 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 152/2000 DLCround-PT-07b-LTLFireability-07 10283144 m, 64562 m/sec, 11114726 t fired, . Pages in use: 152 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 157/2000 DLCround-PT-07b-LTLFireability-07 10602642 m, 63899 m/sec, 11460920 t fired, . Pages in use: 157 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 162/2000 DLCround-PT-07b-LTLFireability-07 10922809 m, 64033 m/sec, 11809086 t fired, . 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Pages in use: 166 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 171/2000 DLCround-PT-07b-LTLFireability-07 11566310 m, 64052 m/sec, 12506384 t fired, . Pages in use: 171 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 175/2000 DLCround-PT-07b-LTLFireability-07 11888533 m, 64444 m/sec, 12856245 t fired, . Pages in use: 175 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 180/2000 DLCround-PT-07b-LTLFireability-07 12209764 m, 64246 m/sec, 13203844 t fired, . Pages in use: 180 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 185/2000 DLCround-PT-07b-LTLFireability-07 12529169 m, 63881 m/sec, 13551596 t fired, . Pages in use: 185 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 189/2000 DLCround-PT-07b-LTLFireability-07 12851402 m, 64446 m/sec, 13900596 t fired, . Pages in use: 189 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 194/2000 DLCround-PT-07b-LTLFireability-07 13173630 m, 64445 m/sec, 14248925 t fired, . Pages in use: 194 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 198/2000 DLCround-PT-07b-LTLFireability-07 13491913 m, 63656 m/sec, 14594463 t fired, . Pages in use: 198 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 203/2000 DLCround-PT-07b-LTLFireability-07 13814650 m, 64547 m/sec, 14943215 t fired, . Pages in use: 203 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 207/2000 DLCround-PT-07b-LTLFireability-07 14132220 m, 63514 m/sec, 15288300 t fired, . Pages in use: 207 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 212/2000 DLCround-PT-07b-LTLFireability-07 14448410 m, 63238 m/sec, 15632355 t fired, . Pages in use: 212 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 216/2000 DLCround-PT-07b-LTLFireability-07 14762787 m, 62875 m/sec, 15971930 t fired, . Pages in use: 216 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 221/2000 DLCround-PT-07b-LTLFireability-07 15074332 m, 62309 m/sec, 16310864 t fired, . Pages in use: 221 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 225/2000 DLCround-PT-07b-LTLFireability-07 15386658 m, 62465 m/sec, 16648792 t fired, . Pages in use: 225 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 230/2000 DLCround-PT-07b-LTLFireability-07 15700502 m, 62768 m/sec, 16987888 t fired, . Pages in use: 230 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 234/2000 DLCround-PT-07b-LTLFireability-07 16011502 m, 62200 m/sec, 17325241 t fired, . Pages in use: 234 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 238/2000 DLCround-PT-07b-LTLFireability-07 16295364 m, 56772 m/sec, 17632717 t fired, . Pages in use: 238 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 243/2000 DLCround-PT-07b-LTLFireability-07 16605548 m, 62036 m/sec, 17967549 t fired, . Pages in use: 243 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 247/2000 DLCround-PT-07b-LTLFireability-07 16914885 m, 61867 m/sec, 18301811 t fired, . Pages in use: 247 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 251/2000 DLCround-PT-07b-LTLFireability-07 17200801 m, 57183 m/sec, 18611126 t fired, . Pages in use: 251 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 255/2000 DLCround-PT-07b-LTLFireability-07 17507265 m, 61292 m/sec, 18941469 t fired, . Pages in use: 255 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 260/2000 DLCround-PT-07b-LTLFireability-07 17814950 m, 61537 m/sec, 19273768 t fired, . Pages in use: 260 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 264/2000 DLCround-PT-07b-LTLFireability-07 18119320 m, 60874 m/sec, 19605452 t fired, . Pages in use: 264 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 268/2000 DLCround-PT-07b-LTLFireability-07 18424459 m, 61027 m/sec, 19935518 t fired, . Pages in use: 268 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 273/2000 DLCround-PT-07b-LTLFireability-07 18730682 m, 61244 m/sec, 20266074 t fired, . Pages in use: 273 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 277/2000 DLCround-PT-07b-LTLFireability-07 19034539 m, 60771 m/sec, 20595866 t fired, . Pages in use: 277 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 281/2000 DLCround-PT-07b-LTLFireability-07 19334436 m, 59979 m/sec, 20920467 t fired, . Pages in use: 281 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 285/2000 DLCround-PT-07b-LTLFireability-07 19634932 m, 60099 m/sec, 21244886 t fired, . Pages in use: 285 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 290/2000 DLCround-PT-07b-LTLFireability-07 19938309 m, 60675 m/sec, 21572814 t fired, . Pages in use: 290 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 294/2000 DLCround-PT-07b-LTLFireability-07 20246700 m, 61678 m/sec, 21905597 t fired, . Pages in use: 294 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 299/2000 DLCround-PT-07b-LTLFireability-07 20556076 m, 61875 m/sec, 22240407 t fired, . Pages in use: 299 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 303/2000 DLCround-PT-07b-LTLFireability-07 20863122 m, 61409 m/sec, 22572885 t fired, . Pages in use: 303 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 307/2000 DLCround-PT-07b-LTLFireability-07 21167657 m, 60907 m/sec, 22902901 t fired, . Pages in use: 307 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 312/2000 DLCround-PT-07b-LTLFireability-07 21473809 m, 61230 m/sec, 23234132 t fired, . Pages in use: 312 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 316/2000 DLCround-PT-07b-LTLFireability-07 21777235 m, 60685 m/sec, 23564422 t fired, . Pages in use: 316 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 320/2000 DLCround-PT-07b-LTLFireability-07 22081195 m, 60792 m/sec, 23894998 t fired, . Pages in use: 320 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 324/2000 DLCround-PT-07b-LTLFireability-07 22386119 m, 60984 m/sec, 24225563 t fired, . Pages in use: 324 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 329/2000 DLCround-PT-07b-LTLFireability-07 22686594 m, 60095 m/sec, 24550840 t fired, . Pages in use: 329 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 333/2000 DLCround-PT-07b-LTLFireability-07 22985048 m, 59690 m/sec, 24874191 t fired, . Pages in use: 333 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 337/2000 DLCround-PT-07b-LTLFireability-07 23281855 m, 59361 m/sec, 25195448 t fired, . Pages in use: 337 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 341/2000 DLCround-PT-07b-LTLFireability-07 23581860 m, 60001 m/sec, 25519521 t fired, . Pages in use: 341 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 345/2000 DLCround-PT-07b-LTLFireability-07 23877007 m, 59029 m/sec, 25839866 t fired, . Pages in use: 345 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 350/2000 DLCround-PT-07b-LTLFireability-07 24176586 m, 59915 m/sec, 26164811 t fired, . Pages in use: 350 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 354/2000 DLCround-PT-07b-LTLFireability-07 24475353 m, 59753 m/sec, 26487634 t fired, . Pages in use: 354 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 358/2000 DLCround-PT-07b-LTLFireability-07 24770956 m, 59120 m/sec, 26808219 t fired, . Pages in use: 358 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 362/2000 DLCround-PT-07b-LTLFireability-07 25071233 m, 60055 m/sec, 27135595 t fired, . Pages in use: 362 Visible: 16 EXCL) for DLCround-PT-07b-LTLFireability-07 (local timeout) CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 1 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 366 Visible: 16 for 51 DLCround-PT-07b-LTLFireability-13 for 33 DLCround-PT-07b-LTLFireability-07 EXCL) for DLCround-PT-07b-LTLFireability-13 134 135 0 1 EXCL) for DLCround-PT-07b-LTLFireability-07 (memory limit exceeded) CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 371 Visible: 16 for 48 DLCround-PT-07b-LTLFireability-12 EXCL) for DLCround-PT-07b-LTLFireability-12 105 105 0 1 for 42 DLCround-PT-07b-LTLFireability-10 EXCL) for DLCround-PT-07b-LTLFireability-10 109 109 0 1 for 36 DLCround-PT-07b-LTLFireability-08 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 6/2000 DLCround-PT-07b-LTLFireability-08 334847 m, 66969 m/sec, 361144 t fired, . Pages in use: 372 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 11/2000 DLCround-PT-07b-LTLFireability-08 661331 m, 65296 m/sec, 713336 t fired, . Pages in use: 377 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 16/2000 DLCround-PT-07b-LTLFireability-08 989633 m, 65660 m/sec, 1067992 t fired, . Pages in use: 382 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 20/2000 DLCround-PT-07b-LTLFireability-08 1312432 m, 64559 m/sec, 1416731 t fired, . Pages in use: 386 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 25/2000 DLCround-PT-07b-LTLFireability-08 1639611 m, 65435 m/sec, 1770127 t fired, . Pages in use: 391 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 30/2000 DLCround-PT-07b-LTLFireability-08 1968697 m, 65817 m/sec, 2125208 t fired, . Pages in use: 396 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 35/2000 DLCround-PT-07b-LTLFireability-08 2302228 m, 66706 m/sec, 2485588 t fired, . Pages in use: 401 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 40/2000 DLCround-PT-07b-LTLFireability-08 2627016 m, 64957 m/sec, 2836247 t fired, . Pages in use: 406 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 45/2000 DLCround-PT-07b-LTLFireability-08 2947985 m, 64193 m/sec, 3184106 t fired, . Pages in use: 411 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 50/2000 DLCround-PT-07b-LTLFireability-08 3268777 m, 64158 m/sec, 3529522 t fired, . Pages in use: 416 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 54/2000 DLCround-PT-07b-LTLFireability-08 3585582 m, 63361 m/sec, 3871840 t fired, . Pages in use: 420 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 59/2000 DLCround-PT-07b-LTLFireability-08 3900048 m, 62893 m/sec, 4211858 t fired, . Pages in use: 425 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 64/2000 DLCround-PT-07b-LTLFireability-08 4214294 m, 62849 m/sec, 4550249 t fired, . Pages in use: 430 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 68/2000 DLCround-PT-07b-LTLFireability-08 4526345 m, 62410 m/sec, 4887834 t fired, . Pages in use: 434 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 73/2000 DLCround-PT-07b-LTLFireability-08 4835883 m, 61907 m/sec, 5222003 t fired, . Pages in use: 439 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 77/2000 DLCround-PT-07b-LTLFireability-08 5143321 m, 61487 m/sec, 5553289 t fired, . Pages in use: 443 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 81/2000 DLCround-PT-07b-LTLFireability-08 5447050 m, 60745 m/sec, 5881898 t fired, . Pages in use: 447 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 86/2000 DLCround-PT-07b-LTLFireability-08 5752547 m, 61099 m/sec, 6211159 t fired, . Pages in use: 452 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 90/2000 DLCround-PT-07b-LTLFireability-08 6047344 m, 58959 m/sec, 6529735 t fired, . Pages in use: 456 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 95/2000 DLCround-PT-07b-LTLFireability-08 6352445 m, 61020 m/sec, 6859128 t fired, . Pages in use: 461 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 99/2000 DLCround-PT-07b-LTLFireability-08 6665286 m, 62568 m/sec, 7196603 t fired, . Pages in use: 465 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 104/2000 DLCround-PT-07b-LTLFireability-08 6976119 m, 62166 m/sec, 7532341 t fired, . Pages in use: 470 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 109/2000 DLCround-PT-07b-LTLFireability-08 7299902 m, 64756 m/sec, 7883155 t fired, . Pages in use: 475 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 114/2000 DLCround-PT-07b-LTLFireability-08 7633991 m, 66817 m/sec, 8245903 t fired, . Pages in use: 480 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 119/2000 DLCround-PT-07b-LTLFireability-08 7961350 m, 65471 m/sec, 8600613 t fired, . Pages in use: 485 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 123/2000 DLCround-PT-07b-LTLFireability-08 8288216 m, 65373 m/sec, 8954390 t fired, . Pages in use: 489 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 128/2000 DLCround-PT-07b-LTLFireability-08 8606058 m, 63568 m/sec, 9299528 t fired, . Pages in use: 494 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 133/2000 DLCround-PT-07b-LTLFireability-08 8936344 m, 66057 m/sec, 9658638 t fired, . Pages in use: 499 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 137/2000 DLCround-PT-07b-LTLFireability-08 9258768 m, 64484 m/sec, 10008050 t fired, . Pages in use: 503 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 142/2000 DLCround-PT-07b-LTLFireability-08 9584592 m, 65164 m/sec, 10360537 t fired, . Pages in use: 508 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 147/2000 DLCround-PT-07b-LTLFireability-08 9907817 m, 64645 m/sec, 10709326 t fired, . Pages in use: 513 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 152/2000 DLCround-PT-07b-LTLFireability-08 10229912 m, 64419 m/sec, 11057278 t fired, . Pages in use: 518 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 156/2000 DLCround-PT-07b-LTLFireability-08 10550106 m, 64038 m/sec, 11403468 t fired, . Pages in use: 522 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 161/2000 DLCround-PT-07b-LTLFireability-08 10869912 m, 63961 m/sec, 11751471 t fired, . Pages in use: 527 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 165/2000 DLCround-PT-07b-LTLFireability-08 11194110 m, 64839 m/sec, 12103942 t fired, . Pages in use: 531 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 170/2000 DLCround-PT-07b-LTLFireability-08 11519544 m, 65086 m/sec, 12455817 t fired, . Pages in use: 536 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 175/2000 DLCround-PT-07b-LTLFireability-08 11844127 m, 64916 m/sec, 12807695 t fired, . Pages in use: 541 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 179/2000 DLCround-PT-07b-LTLFireability-08 12168595 m, 64893 m/sec, 13158737 t fired, . Pages in use: 545 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 184/2000 DLCround-PT-07b-LTLFireability-08 12492465 m, 64774 m/sec, 13511229 t fired, . Pages in use: 550 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 189/2000 DLCround-PT-07b-LTLFireability-08 12818611 m, 65229 m/sec, 13865317 t fired, . Pages in use: 555 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 193/2000 DLCround-PT-07b-LTLFireability-08 13142917 m, 64861 m/sec, 14215948 t fired, . Pages in use: 559 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 198/2000 DLCround-PT-07b-LTLFireability-08 13464918 m, 64400 m/sec, 14565088 t fired, . Pages in use: 564 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 203/2000 DLCround-PT-07b-LTLFireability-08 13788225 m, 64661 m/sec, 14914677 t fired, . Pages in use: 569 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 207/2000 DLCround-PT-07b-LTLFireability-08 14108889 m, 64132 m/sec, 15262710 t fired, . Pages in use: 573 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 212/2000 DLCround-PT-07b-LTLFireability-08 14428318 m, 63885 m/sec, 15610554 t fired, . Pages in use: 578 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 216/2000 DLCround-PT-07b-LTLFireability-08 14747104 m, 63757 m/sec, 15954965 t fired, . Pages in use: 582 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 221/2000 DLCround-PT-07b-LTLFireability-08 15061364 m, 62852 m/sec, 16296731 t fired, . Pages in use: 587 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 225/2000 DLCround-PT-07b-LTLFireability-08 15374819 m, 62691 m/sec, 16636107 t fired, . Pages in use: 591 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 230/2000 DLCround-PT-07b-LTLFireability-08 15689257 m, 62887 m/sec, 16975611 t fired, . Pages in use: 596 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 234/2000 DLCround-PT-07b-LTLFireability-08 16003913 m, 62931 m/sec, 17317076 t fired, . Pages in use: 600 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 239/2000 DLCround-PT-07b-LTLFireability-08 16316671 m, 62551 m/sec, 17655611 t fired, . Pages in use: 605 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 243/2000 DLCround-PT-07b-LTLFireability-08 16631059 m, 62877 m/sec, 17995127 t fired, . Pages in use: 609 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 247/2000 DLCround-PT-07b-LTLFireability-08 16946648 m, 63117 m/sec, 18335899 t fired, . Pages in use: 613 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 252/2000 DLCround-PT-07b-LTLFireability-08 17263065 m, 63283 m/sec, 18678208 t fired, . Pages in use: 618 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 256/2000 DLCround-PT-07b-LTLFireability-08 17577250 m, 62837 m/sec, 19017217 t fired, . Pages in use: 622 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 261/2000 DLCround-PT-07b-LTLFireability-08 17890028 m, 62555 m/sec, 19354475 t fired, . Pages in use: 627 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 265/2000 DLCround-PT-07b-LTLFireability-08 18200567 m, 62107 m/sec, 19693251 t fired, . Pages in use: 631 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 270/2000 DLCround-PT-07b-LTLFireability-08 18510880 m, 62062 m/sec, 20028365 t fired, . Pages in use: 636 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 274/2000 DLCround-PT-07b-LTLFireability-08 18823983 m, 62620 m/sec, 20366691 t fired, . Pages in use: 640 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 278/2000 DLCround-PT-07b-LTLFireability-08 19134064 m, 62016 m/sec, 20702926 t fired, . Pages in use: 644 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 283/2000 DLCround-PT-07b-LTLFireability-08 19441054 m, 61398 m/sec, 21035258 t fired, . Pages in use: 649 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 287/2000 DLCround-PT-07b-LTLFireability-08 19749859 m, 61761 m/sec, 21368961 t fired, . Pages in use: 653 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 292/2000 DLCround-PT-07b-LTLFireability-08 20060882 m, 62204 m/sec, 21704821 t fired, . Pages in use: 658 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 296/2000 DLCround-PT-07b-LTLFireability-08 20374879 m, 62799 m/sec, 22043855 t fired, . Pages in use: 662 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 300/2000 DLCround-PT-07b-LTLFireability-08 20688016 m, 62627 m/sec, 22382880 t fired, . Pages in use: 666 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 305/2000 DLCround-PT-07b-LTLFireability-08 20999509 m, 62298 m/sec, 22721343 t fired, . Pages in use: 671 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 309/2000 DLCround-PT-07b-LTLFireability-08 21311497 m, 62397 m/sec, 23058420 t fired, . Pages in use: 675 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 314/2000 DLCround-PT-07b-LTLFireability-08 21623030 m, 62306 m/sec, 23397230 t fired, . Pages in use: 680 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 318/2000 DLCround-PT-07b-LTLFireability-08 21933983 m, 62190 m/sec, 23734449 t fired, . Pages in use: 684 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 322/2000 DLCround-PT-07b-LTLFireability-08 22245355 m, 62274 m/sec, 24073327 t fired, . Pages in use: 688 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 327/2000 DLCround-PT-07b-LTLFireability-08 22555350 m, 61999 m/sec, 24409208 t fired, . Pages in use: 693 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 331/2000 DLCround-PT-07b-LTLFireability-08 22866327 m, 62195 m/sec, 24745257 t fired, . Pages in use: 697 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 335/2000 DLCround-PT-07b-LTLFireability-08 23172052 m, 61145 m/sec, 25076695 t fired, . Pages in use: 701 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 340/2000 DLCround-PT-07b-LTLFireability-08 23480179 m, 61625 m/sec, 25409968 t fired, . Pages in use: 706 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 344/2000 DLCround-PT-07b-LTLFireability-08 23785406 m, 61045 m/sec, 25740689 t fired, . Pages in use: 710 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 348/2000 DLCround-PT-07b-LTLFireability-08 24091088 m, 61136 m/sec, 26071975 t fired, . Pages in use: 714 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 353/2000 DLCround-PT-07b-LTLFireability-08 24395311 m, 60844 m/sec, 26401039 t fired, . Pages in use: 719 Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false preprocessing[0m AG false state space[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 357/2000 DLCround-PT-07b-LTLFireability-08 24697234 m, 60384 m/sec, 26728311 t fired, . Pages in use: 723 Visible: 16 $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-07b"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is DLCround-PT-07b, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r115-smll-171624276500188"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-07b.tgz
mv DLCround-PT-07b execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;