Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r115-smll-171624276500186.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is DLCround-PT-07b, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r115-smll-171624276500186
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.5M
-rw-r--r-- 1 mcc users 7.7K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 87K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.5K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 48K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.9K Apr 22 14:38 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Apr 22 14:38 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Apr 22 14:38 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Apr 22 14:38 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Apr 13 12:32 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 154K Apr 13 12:32 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.5K Apr 13 12:31 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 51K Apr 13 12:31 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 22 14:38 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Apr 22 14:38 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 4 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 963K May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-07b-CTLFireability-2024-00
FORMULA_NAME DLCround-PT-07b-CTLFireability-2024-01
FORMULA_NAME DLCround-PT-07b-CTLFireability-2024-02
FORMULA_NAME DLCround-PT-07b-CTLFireability-2024-03
FORMULA_NAME DLCround-PT-07b-CTLFireability-2024-04
FORMULA_NAME DLCround-PT-07b-CTLFireability-2024-05
FORMULA_NAME DLCround-PT-07b-CTLFireability-2024-06
FORMULA_NAME DLCround-PT-07b-CTLFireability-2024-07
FORMULA_NAME DLCround-PT-07b-CTLFireability-2024-08
FORMULA_NAME DLCround-PT-07b-CTLFireability-2024-09
FORMULA_NAME DLCround-PT-07b-CTLFireability-2024-10
FORMULA_NAME DLCround-PT-07b-CTLFireability-2024-11
FORMULA_NAME DLCround-PT-07b-CTLFireability-2023-12
FORMULA_NAME DLCround-PT-07b-CTLFireability-2023-13
FORMULA_NAME DLCround-PT-07b-CTLFireability-2023-14
FORMULA_NAME DLCround-PT-07b-CTLFireability-2023-15

=== Now, execution of the tool begins

BK_START 1717074238636

FORMULA DLCround-PT-07b-CTLFireability-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07b-CTLFireability-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1717074898433

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains place/transition net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading formula.
[lola][I] Using XML format (--xmlformula)
[lola][I] reading XML formula
[lola][I] reading formula from CTLFireability.xml
[lola][I] Rule S: 0 transitions removed,0 places removed
[lola][I] LAUNCH task # 65 (type EXCL) for 0 DLCround-PT-07b-CTLFireability-2024-00
[lola][I] time limit : 153 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 68 (type EQUN) for 0 DLCround-PT-07b-CTLFireability-2024-00
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 65 (type EXCL) for DLCround-PT-07b-CTLFireability-2024-00
[lola][I] result : true
[lola][I] markings : 121
[lola][I] fired transitions : 121
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 68 (type EQUN) for DLCround-PT-07b-CTLFireability-2024-00 (obsolete)
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 0 0 0 3 0 0 1
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ 0 0 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF 0 0 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 0 0 0 0 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 61 secs. Pages in use: 1
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I] LAUNCH task # 41 (type EXCL) for 28 DLCround-PT-07b-CTLFireability-2024-08
[lola][I] time limit : 168 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 68 (type EQUN) for DLCround-PT-07b-CTLFireability-2024-00
[lola][I] result : true
[lola][I] LAUNCH task # 73 (type EQUN) for 28 DLCround-PT-07b-CTLFireability-2024-08
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 75 (type EQUN) for 28 DLCround-PT-07b-CTLFireability-2024-08
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 41 (type EXCL) for DLCround-PT-07b-CTLFireability-2024-08
[lola][I] result : true
[lola][I] markings : 23
[lola][I] fired transitions : 46
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 73 (type EQUN) for DLCround-PT-07b-CTLFireability-2024-08 (obsolete)
[lola][W] CANCELED task # 75 (type EQUN) for DLCround-PT-07b-CTLFireability-2024-08 (obsolete)
[lola][I] LAUNCH task # 14 (type EXCL) for 13 DLCround-PT-07b-CTLFireability-2024-03
[lola][I] time limit : 221 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 76 (type FNDP) for 46 DLCround-PT-07b-CTLFireability-2024-10
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 77 (type EQUN) for 46 DLCround-PT-07b-CTLFireability-2024-10
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 76 (type FNDP) for DLCround-PT-07b-CTLFireability-2024-10
[lola][I] result : true
[lola][I] tried executions : 1
[lola][I] time used : 1
[lola][I] memory pages used : 0
[lola][W] CANCELED task # 77 (type EQUN) for DLCround-PT-07b-CTLFireability-2024-10 (obsolete)
[lola][I] FINISHED task # 75 (type EQUN) for DLCround-PT-07b-CTLFireability-2024-08
[lola][I] result : unknown
[lola][I] FINISHED task # 73 (type EQUN) for DLCround-PT-07b-CTLFireability-2024-08
[lola][I] result : true
[lola][I] FINISHED task # 77 (type EQUN) for DLCround-PT-07b-CTLFireability-2024-10
[lola][I] result : true
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 4/252 1/2000 DLCround-PT-07b-CTLFireability-2024-03 113453 m, 22690 m/sec, 544685 t fired, .
[lola][.]
[lola][.] Time elapsed: 66 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 9/252 3/2000 DLCround-PT-07b-CTLFireability-2024-03 376566 m, 52622 m/sec, 1817140 t fired, .
[lola][.]
[lola][.] Time elapsed: 71 secs. Pages in use: 3
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 14/252 4/2000 DLCround-PT-07b-CTLFireability-2024-03 648035 m, 54293 m/sec, 3128402 t fired, .
[lola][.]
[lola][.] Time elapsed: 76 secs. Pages in use: 4
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 19/252 6/2000 DLCround-PT-07b-CTLFireability-2024-03 918623 m, 54117 m/sec, 4433664 t fired, .
[lola][.]
[lola][.] Time elapsed: 81 secs. Pages in use: 6
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 24/252 7/2000 DLCround-PT-07b-CTLFireability-2024-03 1187167 m, 53708 m/sec, 5726081 t fired, .
[lola][.]
[lola][.] Time elapsed: 86 secs. Pages in use: 7
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 29/252 9/2000 DLCround-PT-07b-CTLFireability-2024-03 1452750 m, 53116 m/sec, 7008671 t fired, .
[lola][.]
[lola][.] Time elapsed: 91 secs. Pages in use: 9
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 34/252 10/2000 DLCround-PT-07b-CTLFireability-2024-03 1717800 m, 53010 m/sec, 8292977 t fired, .
[lola][.]
[lola][.] Time elapsed: 96 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 39/252 12/2000 DLCround-PT-07b-CTLFireability-2024-03 1981892 m, 52818 m/sec, 9570651 t fired, .
[lola][.]
[lola][.] Time elapsed: 101 secs. Pages in use: 12
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 44/252 13/2000 DLCround-PT-07b-CTLFireability-2024-03 2245609 m, 52743 m/sec, 10841785 t fired, .
[lola][.]
[lola][.] Time elapsed: 106 secs. Pages in use: 13
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 49/252 15/2000 DLCround-PT-07b-CTLFireability-2024-03 2506001 m, 52078 m/sec, 12111986 t fired, .
[lola][.]
[lola][.] Time elapsed: 111 secs. Pages in use: 15
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 54/252 16/2000 DLCround-PT-07b-CTLFireability-2024-03 2768944 m, 52588 m/sec, 13373318 t fired, .
[lola][.]
[lola][.] Time elapsed: 116 secs. Pages in use: 16
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 59/252 18/2000 DLCround-PT-07b-CTLFireability-2024-03 3030201 m, 52251 m/sec, 14633099 t fired, .
[lola][.]
[lola][.] Time elapsed: 121 secs. Pages in use: 18
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 64/252 19/2000 DLCround-PT-07b-CTLFireability-2024-03 3293476 m, 52655 m/sec, 15906028 t fired, .
[lola][.]
[lola][.] Time elapsed: 126 secs. Pages in use: 19
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 69/252 20/2000 DLCround-PT-07b-CTLFireability-2024-03 3547371 m, 50779 m/sec, 17137903 t fired, .
[lola][.]
[lola][.] Time elapsed: 131 secs. Pages in use: 20
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 74/252 22/2000 DLCround-PT-07b-CTLFireability-2024-03 3802632 m, 51052 m/sec, 18382109 t fired, .
[lola][.]
[lola][.] Time elapsed: 136 secs. Pages in use: 22
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 79/252 23/2000 DLCround-PT-07b-CTLFireability-2024-03 4063152 m, 52104 m/sec, 19640045 t fired, .
[lola][.]
[lola][.] Time elapsed: 141 secs. Pages in use: 23
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 84/252 25/2000 DLCround-PT-07b-CTLFireability-2024-03 4316638 m, 50697 m/sec, 20879120 t fired, .
[lola][.]
[lola][.] Time elapsed: 146 secs. Pages in use: 25
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 89/252 26/2000 DLCround-PT-07b-CTLFireability-2024-03 4566282 m, 49928 m/sec, 22086605 t fired, .
[lola][.]
[lola][.] Time elapsed: 151 secs. Pages in use: 26
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 94/252 27/2000 DLCround-PT-07b-CTLFireability-2024-03 4816478 m, 50039 m/sec, 23296242 t fired, .
[lola][.]
[lola][.] Time elapsed: 156 secs. Pages in use: 27
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 99/252 29/2000 DLCround-PT-07b-CTLFireability-2024-03 5068866 m, 50477 m/sec, 24517076 t fired, .
[lola][.]
[lola][.] Time elapsed: 161 secs. Pages in use: 29
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 104/252 30/2000 DLCround-PT-07b-CTLFireability-2024-03 5323857 m, 50998 m/sec, 25748861 t fired, .
[lola][.]
[lola][.] Time elapsed: 166 secs. Pages in use: 30
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 109/252 32/2000 DLCround-PT-07b-CTLFireability-2024-03 5585941 m, 52416 m/sec, 27010215 t fired, .
[lola][.]
[lola][.] Time elapsed: 171 secs. Pages in use: 32
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 114/252 33/2000 DLCround-PT-07b-CTLFireability-2024-03 5842061 m, 51224 m/sec, 28235811 t fired, .
[lola][.]
[lola][.] Time elapsed: 176 secs. Pages in use: 33
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 119/252 34/2000 DLCround-PT-07b-CTLFireability-2024-03 6097001 m, 50988 m/sec, 29466025 t fired, .
[lola][.]
[lola][.] Time elapsed: 181 secs. Pages in use: 34
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 124/252 36/2000 DLCround-PT-07b-CTLFireability-2024-03 6348303 m, 50260 m/sec, 30678846 t fired, .
[lola][.]
[lola][.] Time elapsed: 186 secs. Pages in use: 36
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 129/252 37/2000 DLCround-PT-07b-CTLFireability-2024-03 6602365 m, 50812 m/sec, 31901384 t fired, .
[lola][.]
[lola][.] Time elapsed: 191 secs. Pages in use: 37
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 134/252 38/2000 DLCround-PT-07b-CTLFireability-2024-03 6856733 m, 50873 m/sec, 33134841 t fired, .
[lola][.]
[lola][.] Time elapsed: 196 secs. Pages in use: 38
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 139/252 40/2000 DLCround-PT-07b-CTLFireability-2024-03 7105364 m, 49726 m/sec, 34325895 t fired, .
[lola][.]
[lola][.] Time elapsed: 201 secs. Pages in use: 40
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 144/252 41/2000 DLCround-PT-07b-CTLFireability-2024-03 7356077 m, 50142 m/sec, 35538115 t fired, .
[lola][.]
[lola][.] Time elapsed: 206 secs. Pages in use: 41
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 149/252 43/2000 DLCround-PT-07b-CTLFireability-2024-03 7612766 m, 51337 m/sec, 36775775 t fired, .
[lola][.]
[lola][.] Time elapsed: 211 secs. Pages in use: 43
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 154/252 44/2000 DLCround-PT-07b-CTLFireability-2024-03 7865994 m, 50645 m/sec, 37987300 t fired, .
[lola][.]
[lola][.] Time elapsed: 216 secs. Pages in use: 44
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 159/252 45/2000 DLCround-PT-07b-CTLFireability-2024-03 8111716 m, 49144 m/sec, 39175362 t fired, .
[lola][.]
[lola][.] Time elapsed: 221 secs. Pages in use: 45
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 164/252 47/2000 DLCround-PT-07b-CTLFireability-2024-03 8365457 m, 50748 m/sec, 40394669 t fired, .
[lola][.]
[lola][.] Time elapsed: 226 secs. Pages in use: 47
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 169/252 48/2000 DLCround-PT-07b-CTLFireability-2024-03 8615467 m, 50002 m/sec, 41602362 t fired, .
[lola][.]
[lola][.] Time elapsed: 231 secs. Pages in use: 48
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 174/252 49/2000 DLCround-PT-07b-CTLFireability-2024-03 8868206 m, 50547 m/sec, 42824708 t fired, .
[lola][.]
[lola][.] Time elapsed: 236 secs. Pages in use: 49
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 179/252 51/2000 DLCround-PT-07b-CTLFireability-2024-03 9114342 m, 49227 m/sec, 44006941 t fired, .
[lola][.]
[lola][.] Time elapsed: 241 secs. Pages in use: 51
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 184/252 52/2000 DLCround-PT-07b-CTLFireability-2024-03 9354815 m, 48094 m/sec, 45171810 t fired, .
[lola][.]
[lola][.] Time elapsed: 246 secs. Pages in use: 52
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 189/252 53/2000 DLCround-PT-07b-CTLFireability-2024-03 9599286 m, 48894 m/sec, 46352774 t fired, .
[lola][.]
[lola][.] Time elapsed: 251 secs. Pages in use: 53
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 194/252 54/2000 DLCround-PT-07b-CTLFireability-2024-03 9844778 m, 49098 m/sec, 47529716 t fired, .
[lola][.]
[lola][.] Time elapsed: 256 secs. Pages in use: 54
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 199/252 56/2000 DLCround-PT-07b-CTLFireability-2024-03 10095330 m, 50110 m/sec, 48734875 t fired, .
[lola][.]
[lola][.] Time elapsed: 261 secs. Pages in use: 56
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 204/252 57/2000 DLCround-PT-07b-CTLFireability-2024-03 10347518 m, 50437 m/sec, 49958159 t fired, .
[lola][.]
[lola][.] Time elapsed: 266 secs. Pages in use: 57
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 209/252 59/2000 DLCround-PT-07b-CTLFireability-2024-03 10599056 m, 50307 m/sec, 51182401 t fired, .
[lola][.]
[lola][.] Time elapsed: 271 secs. Pages in use: 59
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 214/252 60/2000 DLCround-PT-07b-CTLFireability-2024-03 10847668 m, 49722 m/sec, 52385607 t fired, .
[lola][.]
[lola][.] Time elapsed: 276 secs. Pages in use: 60
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 219/252 61/2000 DLCround-PT-07b-CTLFireability-2024-03 11099593 m, 50385 m/sec, 53583050 t fired, .
[lola][.]
[lola][.] Time elapsed: 281 secs. Pages in use: 61
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 224/252 63/2000 DLCround-PT-07b-CTLFireability-2024-03 11351399 m, 50361 m/sec, 54799373 t fired, .
[lola][.]
[lola][.] Time elapsed: 286 secs. Pages in use: 63
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 229/252 64/2000 DLCround-PT-07b-CTLFireability-2024-03 11605511 m, 50822 m/sec, 56022971 t fired, .
[lola][.]
[lola][.] Time elapsed: 291 secs. Pages in use: 64
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 234/252 65/2000 DLCround-PT-07b-CTLFireability-2024-03 11850958 m, 49089 m/sec, 57211282 t fired, .
[lola][.]
[lola][.] Time elapsed: 296 secs. Pages in use: 65
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 239/252 67/2000 DLCround-PT-07b-CTLFireability-2024-03 12092410 m, 48290 m/sec, 58385424 t fired, .
[lola][.]
[lola][.] Time elapsed: 301 secs. Pages in use: 67
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 244/252 68/2000 DLCround-PT-07b-CTLFireability-2024-03 12332035 m, 47925 m/sec, 59546858 t fired, .
[lola][.]
[lola][.] Time elapsed: 306 secs. Pages in use: 68
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 249/252 69/2000 DLCround-PT-07b-CTLFireability-2024-03 12576079 m, 48808 m/sec, 60714047 t fired, .
[lola][.]
[lola][.] Time elapsed: 311 secs. Pages in use: 69
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][W] CANCELED task # 14 (type EXCL) for DLCround-PT-07b-CTLFireability-2024-03 (local timeout)
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 1 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 316 secs. Pages in use: 70
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] LAUNCH task # 59 (type EXCL) for 58 DLCround-PT-07b-CTLFireability-2023-14
[lola][I] time limit : 252 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 14 (type EXCL) for 13 DLCround-PT-07b-CTLFireability-2024-03
[lola][I] time limit : 3284 sec
[lola][I] memory limit: 5 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 5/3284 2/5 DLCround-PT-07b-CTLFireability-2024-03 260315 m, -2463152 m/sec, 1253202 t fired, .
[lola][.] 59 CTL EXCL 5/252 2/2000 DLCround-PT-07b-CTLFireability-2023-14 134485 m, 26897 m/sec, 279626 t fired, .
[lola][.]
[lola][.] Time elapsed: 321 secs. Pages in use: 74
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 10/3284 4/5 DLCround-PT-07b-CTLFireability-2024-03 516012 m, 51139 m/sec, 2492663 t fired, .
[lola][.] 59 CTL EXCL 10/234 4/2000 DLCround-PT-07b-CTLFireability-2023-14 274416 m, 27986 m/sec, 570401 t fired, .
[lola][.]
[lola][.] Time elapsed: 326 secs. Pages in use: 78
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 14 CTL EXCL 15/3284 5/5 DLCround-PT-07b-CTLFireability-2024-03 777304 m, 52258 m/sec, 3752778 t fired, .
[lola][.] 59 CTL EXCL 15/234 6/2000 DLCround-PT-07b-CTLFireability-2023-14 417622 m, 28641 m/sec, 867988 t fired, .
[lola][.]
[lola][.] Time elapsed: 331 secs. Pages in use: 81
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I] CANCELED task # 14 (type EXCL) for DLCround-PT-07b-CTLFireability-2024-03 (memory limit exceeded)
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 20/234 8/2000 DLCround-PT-07b-CTLFireability-2023-14 566198 m, 29715 m/sec, 1176750 t fired, .
[lola][.]
[lola][.] Time elapsed: 336 secs. Pages in use: 82
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 25/252 10/2000 DLCround-PT-07b-CTLFireability-2023-14 711699 m, 29100 m/sec, 1479412 t fired, .
[lola][.]
[lola][.] Time elapsed: 341 secs. Pages in use: 82
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 30/252 12/2000 DLCround-PT-07b-CTLFireability-2023-14 856897 m, 29039 m/sec, 1781610 t fired, .
[lola][.]
[lola][.] Time elapsed: 346 secs. Pages in use: 82
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 35/252 14/2000 DLCround-PT-07b-CTLFireability-2023-14 1002222 m, 29065 m/sec, 2083900 t fired, .
[lola][.]
[lola][.] Time elapsed: 351 secs. Pages in use: 84
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 40/252 15/2000 DLCround-PT-07b-CTLFireability-2023-14 1147038 m, 28963 m/sec, 2385085 t fired, .
[lola][.]
[lola][.] Time elapsed: 356 secs. Pages in use: 85
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 45/252 17/2000 DLCround-PT-07b-CTLFireability-2023-14 1291630 m, 28918 m/sec, 2686092 t fired, .
[lola][.]
[lola][.] Time elapsed: 361 secs. Pages in use: 87
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 50/252 19/2000 DLCround-PT-07b-CTLFireability-2023-14 1436150 m, 28904 m/sec, 2986552 t fired, .
[lola][.]
[lola][.] Time elapsed: 366 secs. Pages in use: 89
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 55/252 21/2000 DLCround-PT-07b-CTLFireability-2023-14 1574174 m, 27604 m/sec, 3273681 t fired, .
[lola][.]
[lola][.] Time elapsed: 371 secs. Pages in use: 91
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 60/252 22/2000 DLCround-PT-07b-CTLFireability-2023-14 1715379 m, 28241 m/sec, 3567538 t fired, .
[lola][.]
[lola][.] Time elapsed: 376 secs. Pages in use: 92
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 65/252 24/2000 DLCround-PT-07b-CTLFireability-2023-14 1859898 m, 28903 m/sec, 3868124 t fired, .
[lola][.]
[lola][.] Time elapsed: 381 secs. Pages in use: 94
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 70/252 26/2000 DLCround-PT-07b-CTLFireability-2023-14 2005675 m, 29155 m/sec, 4170648 t fired, .
[lola][.]
[lola][.] Time elapsed: 386 secs. Pages in use: 96
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 75/252 28/2000 DLCround-PT-07b-CTLFireability-2023-14 2151369 m, 29138 m/sec, 4473974 t fired, .
[lola][.]
[lola][.] Time elapsed: 391 secs. Pages in use: 98
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 80/252 30/2000 DLCround-PT-07b-CTLFireability-2023-14 2297485 m, 29223 m/sec, 4777919 t fired, .
[lola][.]
[lola][.] Time elapsed: 396 secs. Pages in use: 100
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 85/252 32/2000 DLCround-PT-07b-CTLFireability-2023-14 2442067 m, 28916 m/sec, 5078018 t fired, .
[lola][.]
[lola][.] Time elapsed: 401 secs. Pages in use: 102
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 90/252 34/2000 DLCround-PT-07b-CTLFireability-2023-14 2585312 m, 28649 m/sec, 5376456 t fired, .
[lola][.]
[lola][.] Time elapsed: 406 secs. Pages in use: 104
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 95/252 35/2000 DLCround-PT-07b-CTLFireability-2023-14 2727661 m, 28469 m/sec, 5672554 t fired, .
[lola][.]
[lola][.] Time elapsed: 411 secs. Pages in use: 105
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 100/252 37/2000 DLCround-PT-07b-CTLFireability-2023-14 2870174 m, 28502 m/sec, 5970229 t fired, .
[lola][.]
[lola][.] Time elapsed: 416 secs. Pages in use: 107
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 105/252 39/2000 DLCround-PT-07b-CTLFireability-2023-14 3014133 m, 28791 m/sec, 6269069 t fired, .
[lola][.]
[lola][.] Time elapsed: 421 secs. Pages in use: 109
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 110/252 41/2000 DLCround-PT-07b-CTLFireability-2023-14 3159911 m, 29155 m/sec, 6571965 t fired, .
[lola][.]
[lola][.] Time elapsed: 426 secs. Pages in use: 111
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 115/252 43/2000 DLCround-PT-07b-CTLFireability-2023-14 3305506 m, 29119 m/sec, 6874846 t fired, .
[lola][.]
[lola][.] Time elapsed: 431 secs. Pages in use: 113
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 120/252 45/2000 DLCround-PT-07b-CTLFireability-2023-14 3451325 m, 29163 m/sec, 7178769 t fired, .
[lola][.]
[lola][.] Time elapsed: 436 secs. Pages in use: 115
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 125/252 46/2000 DLCround-PT-07b-CTLFireability-2023-14 3593717 m, 28478 m/sec, 7474294 t fired, .
[lola][.]
[lola][.] Time elapsed: 441 secs. Pages in use: 116
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 130/252 48/2000 DLCround-PT-07b-CTLFireability-2023-14 3736850 m, 28626 m/sec, 7772578 t fired, .
[lola][.]
[lola][.] Time elapsed: 446 secs. Pages in use: 118
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 135/252 50/2000 DLCround-PT-07b-CTLFireability-2023-14 3880574 m, 28744 m/sec, 8071333 t fired, .
[lola][.]
[lola][.] Time elapsed: 451 secs. Pages in use: 120
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 140/252 52/2000 DLCround-PT-07b-CTLFireability-2023-14 4025262 m, 28937 m/sec, 8371771 t fired, .
[lola][.]
[lola][.] Time elapsed: 456 secs. Pages in use: 122
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 145/252 53/2000 DLCround-PT-07b-CTLFireability-2023-14 4169170 m, 28781 m/sec, 8670842 t fired, .
[lola][.]
[lola][.] Time elapsed: 461 secs. Pages in use: 123
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 150/252 55/2000 DLCround-PT-07b-CTLFireability-2023-14 4312431 m, 28652 m/sec, 8968666 t fired, .
[lola][.]
[lola][.] Time elapsed: 466 secs. Pages in use: 125
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 155/252 57/2000 DLCround-PT-07b-CTLFireability-2023-14 4456009 m, 28715 m/sec, 9268024 t fired, .
[lola][.]
[lola][.] Time elapsed: 471 secs. Pages in use: 127
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 160/252 59/2000 DLCround-PT-07b-CTLFireability-2023-14 4598388 m, 28475 m/sec, 9563565 t fired, .
[lola][.]
[lola][.] Time elapsed: 476 secs. Pages in use: 129
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 165/252 60/2000 DLCround-PT-07b-CTLFireability-2023-14 4741226 m, 28567 m/sec, 9860773 t fired, .
[lola][.]
[lola][.] Time elapsed: 481 secs. Pages in use: 130
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 170/252 62/2000 DLCround-PT-07b-CTLFireability-2023-14 4884434 m, 28641 m/sec, 10158676 t fired, .
[lola][.]
[lola][.] Time elapsed: 486 secs. Pages in use: 132
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 175/252 64/2000 DLCround-PT-07b-CTLFireability-2023-14 5027925 m, 28698 m/sec, 10457170 t fired, .
[lola][.]
[lola][.] Time elapsed: 491 secs. Pages in use: 134
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 180/252 65/2000 DLCround-PT-07b-CTLFireability-2023-14 5170589 m, 28532 m/sec, 10753382 t fired, .
[lola][.]
[lola][.] Time elapsed: 496 secs. Pages in use: 135
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 185/252 67/2000 DLCround-PT-07b-CTLFireability-2023-14 5311651 m, 28212 m/sec, 11046443 t fired, .
[lola][.]
[lola][.] Time elapsed: 501 secs. Pages in use: 137
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 190/252 69/2000 DLCround-PT-07b-CTLFireability-2023-14 5454321 m, 28534 m/sec, 11344167 t fired, .
[lola][.]
[lola][.] Time elapsed: 506 secs. Pages in use: 139
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 195/252 71/2000 DLCround-PT-07b-CTLFireability-2023-14 5597953 m, 28726 m/sec, 11642202 t fired, .
[lola][.]
[lola][.] Time elapsed: 511 secs. Pages in use: 141
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 200/252 72/2000 DLCround-PT-07b-CTLFireability-2023-14 5739185 m, 28246 m/sec, 11936181 t fired, .
[lola][.]
[lola][.] Time elapsed: 516 secs. Pages in use: 142
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 205/252 74/2000 DLCround-PT-07b-CTLFireability-2023-14 5878896 m, 27942 m/sec, 12226694 t fired, .
[lola][.]
[lola][.] Time elapsed: 521 secs. Pages in use: 144
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 210/252 76/2000 DLCround-PT-07b-CTLFireability-2023-14 6025798 m, 29380 m/sec, 12532371 t fired, .
[lola][.]
[lola][.] Time elapsed: 526 secs. Pages in use: 146
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 215/252 78/2000 DLCround-PT-07b-CTLFireability-2023-14 6169376 m, 28715 m/sec, 12830983 t fired, .
[lola][.]
[lola][.] Time elapsed: 531 secs. Pages in use: 148
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 220/252 80/2000 DLCround-PT-07b-CTLFireability-2023-14 6319722 m, 30069 m/sec, 13143406 t fired, .
[lola][.]
[lola][.] Time elapsed: 536 secs. Pages in use: 150
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 225/252 81/2000 DLCround-PT-07b-CTLFireability-2023-14 6468217 m, 29699 m/sec, 13452388 t fired, .
[lola][.]
[lola][.] Time elapsed: 541 secs. Pages in use: 151
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 230/252 83/2000 DLCround-PT-07b-CTLFireability-2023-14 6618906 m, 30137 m/sec, 13765687 t fired, .
[lola][.]
[lola][.] Time elapsed: 546 secs. Pages in use: 153
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 235/252 85/2000 DLCround-PT-07b-CTLFireability-2023-14 6768359 m, 29890 m/sec, 14076928 t fired, .
[lola][.]
[lola][.] Time elapsed: 551 secs. Pages in use: 155
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 240/252 87/2000 DLCround-PT-07b-CTLFireability-2023-14 6916676 m, 29663 m/sec, 14385135 t fired, .
[lola][.]
[lola][.] Time elapsed: 556 secs. Pages in use: 157
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 245/252 89/2000 DLCround-PT-07b-CTLFireability-2023-14 7063717 m, 29408 m/sec, 14690223 t fired, .
[lola][.]
[lola][.] Time elapsed: 561 secs. Pages in use: 159
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 CTL EXCL 250/252 91/2000 DLCround-PT-07b-CTLFireability-2023-14 7212436 m, 29743 m/sec, 15001357 t fired, .
[lola][.]
[lola][.] Time elapsed: 566 secs. Pages in use: 161
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][W] CANCELED task # 59 (type EXCL) for DLCround-PT-07b-CTLFireability-2023-14 (local timeout)
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 0 0 1 1 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 571 secs. Pages in use: 163
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] LAUNCH task # 53 (type EXCL) for 52 DLCround-PT-07b-CTLFireability-2023-12
[lola][I] time limit : 252 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 59 (type EXCL) for 58 DLCround-PT-07b-CTLFireability-2023-14
[lola][I] time limit : 3029 sec
[lola][I] memory limit: 5 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 53 CTL EXCL 5/252 5/2000 DLCround-PT-07b-CTLFireability-2023-12 333614 m, 66722 m/sec, 364093 t fired, .
[lola][.] 59 CTL EXCL 5/3029 3/5 DLCround-PT-07b-CTLFireability-2023-14 142611 m, -1413965 m/sec, 296383 t fired, .
[lola][.]
[lola][.] Time elapsed: 576 secs. Pages in use: 173
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 53 CTL EXCL 10/252 9/2000 DLCround-PT-07b-CTLFireability-2023-12 656692 m, 64615 m/sec, 722545 t fired, .
[lola][.] 59 CTL EXCL 10/233 4/5 DLCround-PT-07b-CTLFireability-2023-14 285670 m, 28611 m/sec, 593737 t fired, .
[lola][.]
[lola][.] Time elapsed: 581 secs. Pages in use: 180
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I] CANCELED task # 59 (type EXCL) for DLCround-PT-07b-CTLFireability-2023-14 (memory limit exceeded)
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 53 CTL EXCL 15/252 13/2000 DLCround-PT-07b-CTLFireability-2023-12 980711 m, 64803 m/sec, 1081137 t fired, .
[lola][.]
[lola][.] Time elapsed: 586 secs. Pages in use: 184
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 53 CTL EXCL 20/252 18/2000 DLCround-PT-07b-CTLFireability-2023-12 1325375 m, 68932 m/sec, 1459640 t fired, .
[lola][.]
[lola][.] Time elapsed: 591 secs. Pages in use: 189
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 53 CTL EXCL 25/252 22/2000 DLCround-PT-07b-CTLFireability-2023-12 1654264 m, 65777 m/sec, 1827681 t fired, .
[lola][.]
[lola][.] Time elapsed: 596 secs. Pages in use: 195
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 53 CTL EXCL 30/252 26/2000 DLCround-PT-07b-CTLFireability-2023-12 1991249 m, 67397 m/sec, 2204160 t fired, .
[lola][.]
[lola][.] Time elapsed: 601 secs. Pages in use: 201
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 53 CTL EXCL 35/252 30/2000 DLCround-PT-07b-CTLFireability-2023-12 2330010 m, 67752 m/sec, 2580202 t fired, .
[lola][.]
[lola][.] Time elapsed: 606 secs. Pages in use: 206
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 53 CTL EXCL 40/252 35/2000 DLCround-PT-07b-CTLFireability-2023-12 2660173 m, 66032 m/sec, 2947246 t fired, .
[lola][.]
[lola][.] Time elapsed: 611 secs. Pages in use: 213
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 53 CTL EXCL 45/252 38/2000 DLCround-PT-07b-CTLFireability-2023-12 2988596 m, 65684 m/sec, 3313406 t fired, .
[lola][.]
[lola][.] Time elapsed: 616 secs. Pages in use: 218
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 53 CTL EXCL 50/252 42/2000 DLCround-PT-07b-CTLFireability-2023-12 3314251 m, 65131 m/sec, 3680296 t fired, .
[lola][.]
[lola][.] Time elapsed: 621 secs. Pages in use: 224
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 53 CTL EXCL 55/252 46/2000 DLCround-PT-07b-CTLFireability-2023-12 3646057 m, 66361 m/sec, 4052144 t fired, .
[lola][.]
[lola][.] Time elapsed: 626 secs. Pages in use: 230
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 53 CTL EXCL 60/252 50/2000 DLCround-PT-07b-CTLFireability-2023-12 3972089 m, 65206 m/sec, 4418881 t fired, .
[lola][.]
[lola][.] Time elapsed: 631 secs. Pages in use: 235
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 53 CTL EXCL 65/252 53/2000 DLCround-PT-07b-CTLFireability-2023-12 4293411 m, 64264 m/sec, 4777565 t fired, .
[lola][.]
[lola][.] Time elapsed: 636 secs. Pages in use: 240
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 53 CTL EXCL 70/252 57/2000 DLCround-PT-07b-CTLFireability-2023-12 4616636 m, 64645 m/sec, 5139546 t fired, .
[lola][.]
[lola][.] Time elapsed: 641 secs. Pages in use: 246
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 53 CTL EXCL 75/252 61/2000 DLCround-PT-07b-CTLFireability-2023-12 4942345 m, 65141 m/sec, 5505851 t fired, .
[lola][.]
[lola][.] Time elapsed: 646 secs. Pages in use: 252
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 53 CTL EXCL 80/252 65/2000 DLCround-PT-07b-CTLFireability-2023-12 5273592 m, 66249 m/sec, 5875455 t fired, .
[lola][.]
[lola][.] Time elapsed: 651 secs. Pages in use: 258
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07b-CTLFireability-2024-08: DISJ true CTL model checker
[lola][.] DLCround-PT-07b-CTLFireability-2024-10: EF true findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07b-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-13: AFAG 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[lola][.] DLCround-PT-07b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 53 CTL EXCL 85/252 68/2000 DLCround-PT-07b-CTLFireability-2023-12 5559629 m, 57207 m/sec, 6194716 t fired, .
[lola][.]
[lola][.] Time elapsed: 656 secs. Pages in use: 262
[lola][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 407 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-07b"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is DLCround-PT-07b, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r115-smll-171624276500186"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-07b.tgz
mv DLCround-PT-07b execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;