Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r115-smll-171624276500180.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is DLCround-PT-07a, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r115-smll-171624276500180
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 888K
-rw-r--r-- 1 mcc users 6.7K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 71K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.4K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 49K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Apr 22 14:38 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Apr 22 14:38 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Apr 22 14:38 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Apr 22 14:38 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Apr 13 14:50 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 124K Apr 13 14:50 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 12K Apr 13 14:30 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 107K Apr 13 14:30 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 22 14:38 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Apr 22 14:38 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 4 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 398K May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-07a-LTLFireability-00
FORMULA_NAME DLCround-PT-07a-LTLFireability-01
FORMULA_NAME DLCround-PT-07a-LTLFireability-02
FORMULA_NAME DLCround-PT-07a-LTLFireability-03
FORMULA_NAME DLCround-PT-07a-LTLFireability-04
FORMULA_NAME DLCround-PT-07a-LTLFireability-05
FORMULA_NAME DLCround-PT-07a-LTLFireability-06
FORMULA_NAME DLCround-PT-07a-LTLFireability-07
FORMULA_NAME DLCround-PT-07a-LTLFireability-08
FORMULA_NAME DLCround-PT-07a-LTLFireability-09
FORMULA_NAME DLCround-PT-07a-LTLFireability-10
FORMULA_NAME DLCround-PT-07a-LTLFireability-11
FORMULA_NAME DLCround-PT-07a-LTLFireability-12
FORMULA_NAME DLCround-PT-07a-LTLFireability-13
FORMULA_NAME DLCround-PT-07a-LTLFireability-14
FORMULA_NAME DLCround-PT-07a-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1717073742176

FORMULA DLCround-PT-07a-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07a-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07a-LTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07a-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07a-LTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07a-LTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07a-LTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07a-LTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07a-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07a-LTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07a-LTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07a-LTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07a-LTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07a-LTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07a-LTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07a-LTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[lola] FINAL RESULTS
[lola]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola] DLCround-PT-07a-LTLFireability-00: CONJ false state space
[lola] DLCround-PT-07a-LTLFireability-01: LTL false LTL model checker
[lola] DLCround-PT-07a-LTLFireability-02: LTL false LTL model checker
[lola] DLCround-PT-07a-LTLFireability-03: LTL false LTL model checker
[lola] DLCround-PT-07a-LTLFireability-04: CONJ false LTL model checker
[lola] DLCround-PT-07a-LTLFireability-05: LTL false LTL model checker
[lola] DLCround-PT-07a-LTLFireability-06: LTL true LTL model checker
[lola] DLCround-PT-07a-LTLFireability-07: CONJ false LTL model checker
[lola] DLCround-PT-07a-LTLFireability-08: LTL false LTL model checker
[lola] DLCround-PT-07a-LTLFireability-09: LTL false LTL model checker
[lola] DLCround-PT-07a-LTLFireability-10: LTL false LTL model checker
[lola] DLCround-PT-07a-LTLFireability-11: LTL true LTL model checker
[lola] DLCround-PT-07a-LTLFireability-12: LTL false LTL model checker
[lola] DLCround-PT-07a-LTLFireability-13: LTL true LTL model checker
[lola] DLCround-PT-07a-LTLFireability-14: LTL false LTL model checker
[lola] DLCround-PT-07a-LTLFireability-15: LTL true LTL model checker
[lola]
[lola] Time elapsed: 63 secs. Pages in use: 13

BK_STOP 1717073805197

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains place/transition net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading formula.
[lola][I] Using XML format (--xmlformula)
[lola][I] reading XML formula
[lola][I] reading formula from LTLFireability.xml
[lola][I] Rule S: 0 transitions removed,0 places removed
[lola][I] NOTDEADLOCKFREE
[lola][I] LAUNCH task # 63 (type EXCL) for 0 DLCround-PT-07a-LTLFireability-00
[lola][I] time limit : 156 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 61 (type FNDP) for 0 DLCround-PT-07a-LTLFireability-00
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 62 (type EQUN) for 0 DLCround-PT-07a-LTLFireability-00
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 63 (type EXCL) for DLCround-PT-07a-LTLFireability-00
[lola][I] result : true
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 61 (type FNDP) for DLCround-PT-07a-LTLFireability-00 (obsolete)
[lola][W] CANCELED task # 62 (type EQUN) for DLCround-PT-07a-LTLFireability-00 (obsolete)
[lola][I] FINISHED task # 61 (type FNDP) for DLCround-PT-07a-LTLFireability-00
[lola][I] result : true
[lola][I] tried executions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 0
[lola][I] FINISHED task # 62 (type EQUN) for DLCround-PT-07a-LTLFireability-00
[lola][I] result : unknown
[*** LOG ERROR #0001 ***] [2024-05-30 12:55:42] [status_logger] string pointer is null
[lola][I] LAUNCH task # 11 (type EXCL) for 10 DLCround-PT-07a-LTLFireability-02
[lola][I] time limit : 199 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 65 (type FNDP) for 29 DLCround-PT-07a-LTLFireability-07
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 66 (type EQUN) for 29 DLCround-PT-07a-LTLFireability-07
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 11 (type EXCL) for DLCround-PT-07a-LTLFireability-02
[lola][I] result : false
[lola][I] markings : 5
[lola][I] fired transitions : 5
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 43 (type EXCL) for 42 DLCround-PT-07a-LTLFireability-10
[lola][I] time limit : 211 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 43 (type EXCL) for DLCround-PT-07a-LTLFireability-10
[lola][I] result : false
[lola][I] markings : 5
[lola][I] fired transitions : 5
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 40 (type EXCL) for 39 DLCround-PT-07a-LTLFireability-09
[lola][I] time limit : 224 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 40 (type EXCL) for DLCround-PT-07a-LTLFireability-09
[lola][I] result : false
[lola][I] markings : 9
[lola][I] fired transitions : 15
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 27 (type EXCL) for 26 DLCround-PT-07a-LTLFireability-06
[lola][I] time limit : 239 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 27 (type EXCL) for DLCround-PT-07a-LTLFireability-06
[lola][I] result : true
[lola][I] markings : 2
[lola][I] fired transitions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 55 (type EXCL) for 54 DLCround-PT-07a-LTLFireability-14
[lola][I] time limit : 257 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 55 (type EXCL) for DLCround-PT-07a-LTLFireability-14
[lola][I] result : false
[lola][I] markings : 32
[lola][I] fired transitions : 154
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 37 (type EXCL) for 36 DLCround-PT-07a-LTLFireability-08
[lola][I] time limit : 276 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 37 (type EXCL) for DLCround-PT-07a-LTLFireability-08
[lola][I] result : false
[lola][I] markings : 5
[lola][I] fired transitions : 5
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 58 (type EXCL) for 57 DLCround-PT-07a-LTLFireability-15
[lola][I] time limit : 299 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 58 (type EXCL) for DLCround-PT-07a-LTLFireability-15
[lola][I] result : true
[lola][I] markings : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 34 (type EXCL) for 29 DLCround-PT-07a-LTLFireability-07
[lola][I] time limit : 359 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 34 (type EXCL) for DLCround-PT-07a-LTLFireability-07
[lola][I] result : false
[lola][I] markings : 5
[lola][I] fired transitions : 5
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 65 (type FNDP) for DLCround-PT-07a-LTLFireability-07 (obsolete)
[lola][W] CANCELED task # 66 (type EQUN) for DLCround-PT-07a-LTLFireability-07 (obsolete)
[lola][I] LAUNCH task # 24 (type EXCL) for 23 DLCround-PT-07a-LTLFireability-05
[lola][I] time limit : 449 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 65 (type FNDP) for DLCround-PT-07a-LTLFireability-07
[lola][I] result : true
[lola][I] tried executions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 0
[lola][I] FINISHED task # 66 (type EQUN) for DLCround-PT-07a-LTLFireability-07
[lola][I] result : unknown
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07a-LTLFireability-00: CONJ false state space
[lola][.] DLCround-PT-07a-LTLFireability-02: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-06: LTL true LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-07: CONJ false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-08: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-09: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-10: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-14: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-15: LTL true LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-04: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 24 LTL EXCL 4/449 1/2000 DLCround-PT-07a-LTLFireability-05 139305 m, 27861 m/sec, 5164506 t fired, .
[lola][.]
[lola][.] Time elapsed: 5 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07a-LTLFireability-00: CONJ false state space
[lola][.] DLCround-PT-07a-LTLFireability-02: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-06: LTL true LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-07: CONJ false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-08: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-09: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-10: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-14: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-15: LTL true LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-04: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 24 LTL EXCL 9/449 3/2000 DLCround-PT-07a-LTLFireability-05 311254 m, 34389 m/sec, 11632595 t fired, .
[lola][.]
[lola][.] Time elapsed: 10 secs. Pages in use: 3
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07a-LTLFireability-00: CONJ false state space
[lola][.] DLCround-PT-07a-LTLFireability-02: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-06: LTL true LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-07: CONJ false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-08: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-09: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-10: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-14: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-15: LTL true LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-04: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 24 LTL EXCL 14/449 4/2000 DLCround-PT-07a-LTLFireability-05 476466 m, 33042 m/sec, 18148454 t fired, .
[lola][.]
[lola][.] Time elapsed: 15 secs. Pages in use: 4
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07a-LTLFireability-00: CONJ false state space
[lola][.] DLCround-PT-07a-LTLFireability-02: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-06: LTL true LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-07: CONJ false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-08: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-09: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-10: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-14: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-15: LTL true LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-04: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 24 LTL EXCL 19/449 5/2000 DLCround-PT-07a-LTLFireability-05 628903 m, 30487 m/sec, 24036885 t fired, .
[lola][.]
[lola][.] Time elapsed: 20 secs. Pages in use: 5
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-07a-LTLFireability-00: CONJ false state space
[lola][.] DLCround-PT-07a-LTLFireability-02: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-06: LTL true LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-07: CONJ false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-08: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-09: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-10: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-14: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-15: LTL true LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-04: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 24 LTL EXCL 24/449 6/2000 DLCround-PT-07a-LTLFireability-05 780818 m, 30383 m/sec, 30231189 t fired, .
[lola][.]
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[lola][.] DLCround-PT-07a-LTLFireability-00: CONJ false state space
[lola][.] DLCround-PT-07a-LTLFireability-02: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-06: LTL true LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-07: CONJ false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-08: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-09: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-10: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-14: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-15: LTL true LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-04: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 24 LTL EXCL 29/449 7/2000 DLCround-PT-07a-LTLFireability-05 931523 m, 30141 m/sec, 36409166 t fired, .
[lola][.]
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[lola][.] DLCround-PT-07a-LTLFireability-00: CONJ false state space
[lola][.] DLCround-PT-07a-LTLFireability-02: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-06: LTL true LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-07: CONJ false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-08: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-09: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-10: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-14: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-15: LTL true LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-04: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 24 LTL EXCL 34/449 7/2000 DLCround-PT-07a-LTLFireability-05 1072909 m, 28277 m/sec, 42334842 t fired, .
[lola][.]
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[lola][.] DLCround-PT-07a-LTLFireability-00: CONJ false state space
[lola][.] DLCround-PT-07a-LTLFireability-02: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-06: LTL true LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-07: CONJ false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-08: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-09: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-10: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-14: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-15: LTL true LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-04: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 24 LTL EXCL 39/449 8/2000 DLCround-PT-07a-LTLFireability-05 1219888 m, 29395 m/sec, 48495162 t fired, .
[lola][.]
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[lola][.] DLCround-PT-07a-LTLFireability-00: CONJ false state space
[lola][.] DLCround-PT-07a-LTLFireability-02: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-06: LTL true LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-07: CONJ false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-08: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-09: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-10: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-14: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-15: LTL true LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-04: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 24 LTL EXCL 44/449 10/2000 DLCround-PT-07a-LTLFireability-05 1403353 m, 36693 m/sec, 54955369 t fired, .
[lola][.]
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[lola][.] DLCround-PT-07a-LTLFireability-00: CONJ false state space
[lola][.] DLCround-PT-07a-LTLFireability-02: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-06: LTL true LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-07: CONJ false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-08: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-09: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-10: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-14: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-15: LTL true LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-04: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 24 LTL EXCL 49/449 11/2000 DLCround-PT-07a-LTLFireability-05 1581267 m, 35582 m/sec, 61230013 t fired, .
[lola][.]
[lola][.] Time elapsed: 50 secs. Pages in use: 11
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[lola][.] DLCround-PT-07a-LTLFireability-00: CONJ false state space
[lola][.] DLCround-PT-07a-LTLFireability-02: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-06: LTL true LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-07: CONJ false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-08: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-09: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-10: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-14: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-15: LTL true LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-04: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 24 LTL EXCL 54/449 12/2000 DLCround-PT-07a-LTLFireability-05 1748882 m, 33523 m/sec, 67391784 t fired, .
[lola][.]
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[lola][.] DLCround-PT-07a-LTLFireability-00: CONJ false state space
[lola][.] DLCround-PT-07a-LTLFireability-02: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-06: LTL true LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-07: CONJ false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-08: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-09: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-10: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-14: LTL false LTL model checker
[lola][.] DLCround-PT-07a-LTLFireability-15: LTL true LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-07a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-04: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 24 LTL EXCL 59/449 13/2000 DLCround-PT-07a-LTLFireability-05 1914277 m, 33079 m/sec, 73544374 t fired, .
[lola][.]
[lola][.] Time elapsed: 60 secs. Pages in use: 13
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] FINISHED task # 24 (type EXCL) for DLCround-PT-07a-LTLFireability-05
[lola][I] result : false
[lola][I] markings : 2003424
[lola][I] fired transitions : 76760494
[lola][I] time used : 62
[lola][I] memory pages used : 13
[lola][I] LAUNCH task # 49 (type EXCL) for 48 DLCround-PT-07a-LTLFireability-12
[lola][I] time limit : 505 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 49 (type EXCL) for DLCround-PT-07a-LTLFireability-12
[lola][I] result : false
[lola][I] markings : 5
[lola][I] fired transitions : 5
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 46 (type EXCL) for 45 DLCround-PT-07a-LTLFireability-11
[lola][I] time limit : 589 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 46 (type EXCL) for DLCround-PT-07a-LTLFireability-11
[lola][I] result : true
[lola][I] markings : 3
[lola][I] fired transitions : 2
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 19 (type EXCL) for 16 DLCround-PT-07a-LTLFireability-04
[lola][I] time limit : 707 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 19 (type EXCL) for DLCround-PT-07a-LTLFireability-04
[lola][I] result : false
[lola][I] markings : 5
[lola][I] fired transitions : 5
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 14 (type EXCL) for 13 DLCround-PT-07a-LTLFireability-03
[lola][I] time limit : 1179 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 14 (type EXCL) for DLCround-PT-07a-LTLFireability-03
[lola][I] result : false
[lola][I] markings : 16
[lola][I] fired transitions : 70
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 8 (type EXCL) for 7 DLCround-PT-07a-LTLFireability-01
[lola][I] time limit : 1768 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 8 (type EXCL) for DLCround-PT-07a-LTLFireability-01
[lola][I] result : false
[lola][I] markings : 2
[lola][I] fired transitions : 2
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 52 (type EXCL) for 51 DLCround-PT-07a-LTLFireability-13
[lola][I] time limit : 3537 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 52 (type EXCL) for DLCround-PT-07a-LTLFireability-13
[lola][I] result : true
[lola][I] markings : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] Portfolio finished: no open formulas

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-07a"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is DLCround-PT-07a, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r115-smll-171624276500180"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-07a.tgz
mv DLCround-PT-07a execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;