About the Execution of LoLA for DLCround-PT-06a
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 5338.604 | 254962.00 | 256861.00 | 1076.10 | ?FFFFTFFFFTFFFTF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r115-smll-171624276500164.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is DLCround-PT-06a, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r115-smll-171624276500164
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 804K
-rw-r--r-- 1 mcc users 6.3K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 66K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.4K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 63K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K Apr 22 14:38 LTLCardinality.txt
-rw-r--r-- 1 mcc users 22K Apr 22 14:38 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Apr 22 14:38 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 22 14:38 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Apr 13 13:36 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 128K Apr 13 13:36 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.6K Apr 13 13:19 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 86K Apr 13 13:19 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 22 14:38 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Apr 22 14:38 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 4 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 325K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-06a-LTLFireability-00
FORMULA_NAME DLCround-PT-06a-LTLFireability-01
FORMULA_NAME DLCround-PT-06a-LTLFireability-02
FORMULA_NAME DLCround-PT-06a-LTLFireability-03
FORMULA_NAME DLCround-PT-06a-LTLFireability-04
FORMULA_NAME DLCround-PT-06a-LTLFireability-05
FORMULA_NAME DLCround-PT-06a-LTLFireability-06
FORMULA_NAME DLCround-PT-06a-LTLFireability-07
FORMULA_NAME DLCround-PT-06a-LTLFireability-08
FORMULA_NAME DLCround-PT-06a-LTLFireability-09
FORMULA_NAME DLCround-PT-06a-LTLFireability-10
FORMULA_NAME DLCround-PT-06a-LTLFireability-11
FORMULA_NAME DLCround-PT-06a-LTLFireability-12
FORMULA_NAME DLCround-PT-06a-LTLFireability-13
FORMULA_NAME DLCround-PT-06a-LTLFireability-14
FORMULA_NAME DLCround-PT-06a-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717069842896
FORMULA DLCround-PT-06a-LTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-06a-LTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-06a-LTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-06a-LTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-06a-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-06a-LTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-06a-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-06a-LTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-06a-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-06a-LTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-06a-LTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-06a-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-06a-LTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-06a-LTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-06a-LTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[33mDLCround-PT-06a-LTLFireability-00: LTL unknown AGGR[0m
[[35mlola[0m] [1m[31mDLCround-PT-06a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mDLCround-PT-06a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mDLCround-PT-06a-LTLFireability-03: CONJ false LTL model checker[0m
[[35mlola[0m] [1m[31mDLCround-PT-06a-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m] [1m[32mDLCround-PT-06a-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m] [1m[31mDLCround-PT-06a-LTLFireability-06: CONJ false findpath[0m
[[35mlola[0m] [1m[31mDLCround-PT-06a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mDLCround-PT-06a-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mDLCround-PT-06a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m] [1m[32mDLCround-PT-06a-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m] [1m[31mDLCround-PT-06a-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mDLCround-PT-06a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mDLCround-PT-06a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m] [1m[32mDLCround-PT-06a-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m] [1m[31mDLCround-PT-06a-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 254 secs. Pages in use: 69
BK_STOP 1717070097858
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 56 (type SKEL/SRCH) for 35 DLCround-PT-06a-LTLFireability-09
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 DLCround-PT-06a-LTLFireability-00
[[35mlola[0m][I] time limit : 144 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 58 (type FNDP) for 22 DLCround-PT-06a-LTLFireability-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 59 (type EQUN) for 22 DLCround-PT-06a-LTLFireability-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] FINISHED task # 58 (type FNDP) for DLCround-PT-06a-LTLFireability-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 59 (type EQUN) for DLCround-PT-06a-LTLFireability-06 (obsolete)
[[35mlola[0m][I] FINISHED task # 59 (type EQUN) for DLCround-PT-06a-LTLFireability-06
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 56 (type SKEL/SRCH) for DLCround-PT-06a-LTLFireability-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 3916
[[35mlola[0m][I] fired transitions : 45440
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 62 (type SKEL/SRCH) for 41 DLCround-PT-06a-LTLFireability-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 62 (type SKEL/SRCH) for DLCround-PT-06a-LTLFireability-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 5
[[35mlola[0m][I] fired transitions : 5
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-06a-LTLFireability-06: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 5/225 2/2000 DLCround-PT-06a-LTLFireability-00 224428 m, 44885 m/sec, 5105118 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 10/225 4/2000 DLCround-PT-06a-LTLFireability-00 495844 m, 54283 m/sec, 11671855 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 15/225 5/2000 DLCround-PT-06a-LTLFireability-00 744855 m, 49802 m/sec, 17974697 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 20/225 7/2000 DLCround-PT-06a-LTLFireability-00 978855 m, 46800 m/sec, 24452244 t fired, .
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[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-06a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][I] FINISHED task # 17 (type EXCL) for DLCround-PT-06a-LTLFireability-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 6
[[35mlola[0m][I] fired transitions : 7
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 14 (type EXCL) for 9 DLCround-PT-06a-LTLFireability-03
[[35mlola[0m][I] time limit : 557 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 14 (type EXCL) for DLCround-PT-06a-LTLFireability-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 5
[[35mlola[0m][I] fired transitions : 5
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 DLCround-PT-06a-LTLFireability-02
[[35mlola[0m][I] time limit : 836 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 7 (type EXCL) for DLCround-PT-06a-LTLFireability-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 30145
[[35mlola[0m][I] fired transitions : 978802
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 DLCround-PT-06a-LTLFireability-01
[[35mlola[0m][I] time limit : 1115 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 4 (type EXCL) for DLCround-PT-06a-LTLFireability-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 27088
[[35mlola[0m][I] fired transitions : 581548
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 54 (type EXCL) for 53 DLCround-PT-06a-LTLFireability-15
[[35mlola[0m][I] time limit : 1673 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 54 (type EXCL) for DLCround-PT-06a-LTLFireability-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 11
[[35mlola[0m][I] fired transitions : 113
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 20 (type EXCL) for 19 DLCround-PT-06a-LTLFireability-05
[[35mlola[0m][I] time limit : 3346 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 20 (type EXCL) for DLCround-PT-06a-LTLFireability-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] Portfolio finished: no open tasks 16
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-06a"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is DLCround-PT-06a, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r115-smll-171624276500164"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-06a.tgz
mv DLCround-PT-06a execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;