fond
Model Checking Contest 2024
14th edition, Geneva, Switzerland, June 25, 2024
Execution of r115-smll-171624276500162
Last Updated
July 7, 2024

About the Execution of LoLA for DLCround-PT-06a

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
16207.495 528403.00 536712.00 2347.90 FF?????????????? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r115-smll-171624276500162.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is DLCround-PT-06a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r115-smll-171624276500162
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 804K
-rw-r--r-- 1 mcc users 6.3K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 66K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.4K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 63K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K Apr 22 14:38 LTLCardinality.txt
-rw-r--r-- 1 mcc users 22K Apr 22 14:38 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Apr 22 14:38 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 22 14:38 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Apr 13 13:36 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 128K Apr 13 13:36 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.6K Apr 13 13:19 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 86K Apr 13 13:19 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 22 14:38 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Apr 22 14:38 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 4 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 325K May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-06a-CTLFireability-2024-00
FORMULA_NAME DLCround-PT-06a-CTLFireability-2024-01
FORMULA_NAME DLCround-PT-06a-CTLFireability-2024-02
FORMULA_NAME DLCround-PT-06a-CTLFireability-2024-03
FORMULA_NAME DLCround-PT-06a-CTLFireability-2024-04
FORMULA_NAME DLCround-PT-06a-CTLFireability-2024-05
FORMULA_NAME DLCround-PT-06a-CTLFireability-2024-06
FORMULA_NAME DLCround-PT-06a-CTLFireability-2024-07
FORMULA_NAME DLCround-PT-06a-CTLFireability-2024-08
FORMULA_NAME DLCround-PT-06a-CTLFireability-2024-09
FORMULA_NAME DLCround-PT-06a-CTLFireability-2024-10
FORMULA_NAME DLCround-PT-06a-CTLFireability-2024-11
FORMULA_NAME DLCround-PT-06a-CTLFireability-2023-12
FORMULA_NAME DLCround-PT-06a-CTLFireability-2023-13
FORMULA_NAME DLCround-PT-06a-CTLFireability-2023-14
FORMULA_NAME DLCround-PT-06a-CTLFireability-2023-15

=== Now, execution of the tool begins

BK_START 1717069293234

FORMULA DLCround-PT-06a-CTLFireability-2024-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-06a-CTLFireability-2024-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1717069821637

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains place/transition net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading formula.
[lola][I] Using XML format (--xmlformula)
[lola][I] reading XML formula
[lola][I] reading formula from CTLFireability.xml
[lola][I] Rule S: 0 transitions removed,0 places removed
[lola][I] LAUNCH task # 4 (type CNST) for 3 DLCround-PT-06a-CTLFireability-2024-01
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] FINISHED task # 4 (type CNST) for DLCround-PT-06a-CTLFireability-2024-01
[lola][I] result : false
[lola][I] LAUNCH task # 10 (type EXCL) for 9 DLCround-PT-06a-CTLFireability-2024-03
[lola][I] time limit : 163 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 1 (type CNST) for 0 DLCround-PT-06a-CTLFireability-2024-00
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] FINISHED task # 1 (type CNST) for DLCround-PT-06a-CTLFireability-2024-00
[lola][I] result : false
[lola][I] LAUNCH task # 55 (type EQUN) for 37 DLCround-PT-06a-CTLFireability-2024-11
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 57 (type EQUN) for 37 DLCround-PT-06a-CTLFireability-2024-11
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 57 (type EQUN) for DLCround-PT-06a-CTLFireability-2024-11
[lola][I] result : true
[lola][I] FINISHED task # 55 (type EQUN) for DLCround-PT-06a-CTLFireability-2024-11
[lola][I] result : unknown
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-06a-CTLFireability-2024-00: INITIAL false preprocessing
[lola][.] DLCround-PT-06a-CTLFireability-2024-01: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-06a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-05: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-11: AGEF 0 1 0 0 3 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 10 CTL EXCL 5/239 1/2000 DLCround-PT-06a-CTLFireability-2024-03 139263 m, 27852 m/sec, 6210295 t fired, .
[lola][.]
[lola][.] Time elapsed: 6 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-06a-CTLFireability-2024-00: INITIAL false preprocessing
[lola][.] DLCround-PT-06a-CTLFireability-2024-01: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-06a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-05: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-11: AGEF 0 1 0 0 3 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 10 CTL EXCL 10/239 2/2000 DLCround-PT-06a-CTLFireability-2024-03 308236 m, 33794 m/sec, 13869457 t fired, .
[lola][.]
[lola][.] Time elapsed: 11 secs. Pages in use: 2
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-06a-CTLFireability-2024-00: INITIAL false preprocessing
[lola][.] DLCround-PT-06a-CTLFireability-2024-01: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-06a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-05: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-11: AGEF 0 1 0 0 3 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 10 CTL EXCL 15/239 2/2000 DLCround-PT-06a-CTLFireability-2024-03 473781 m, 33109 m/sec, 21570001 t fired, .
[lola][.]
[lola][.] Time elapsed: 16 secs. Pages in use: 2
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-06a-CTLFireability-2024-00: INITIAL false preprocessing
[lola][.] DLCround-PT-06a-CTLFireability-2024-01: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-06a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-05: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-11: AGEF 0 1 0 0 3 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 10 CTL EXCL 20/239 3/2000 DLCround-PT-06a-CTLFireability-2024-03 634981 m, 32240 m/sec, 29145154 t fired, .
[lola][.]
[lola][.] Time elapsed: 21 secs. Pages in use: 3
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-06a-CTLFireability-2024-00: INITIAL false preprocessing
[lola][.] DLCround-PT-06a-CTLFireability-2024-01: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-06a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-05: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-11: AGEF 0 1 0 0 3 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 10 CTL EXCL 25/239 4/2000 DLCround-PT-06a-CTLFireability-2024-03 797534 m, 32510 m/sec, 36865350 t fired, .
[lola][.]
[lola][.] Time elapsed: 26 secs. Pages in use: 4
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-06a-CTLFireability-2024-00: INITIAL false preprocessing
[lola][.] DLCround-PT-06a-CTLFireability-2024-01: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-06a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-05: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-11: AGEF 0 1 0 0 3 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 10 CTL EXCL 30/239 4/2000 DLCround-PT-06a-CTLFireability-2024-03 963011 m, 33095 m/sec, 44370333 t fired, .
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[lola][.] 10 CTL EXCL 35/239 5/2000 DLCround-PT-06a-CTLFireability-2024-03 1116329 m, 30663 m/sec, 51756834 t fired, .
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[lola][.] 10 CTL EXCL 40/239 6/2000 DLCround-PT-06a-CTLFireability-2024-03 1272120 m, 31158 m/sec, 59185861 t fired, .
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[lola][.] 10 CTL EXCL 45/239 6/2000 DLCround-PT-06a-CTLFireability-2024-03 1424595 m, 30495 m/sec, 66584918 t fired, .
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[lola][.] 10 CTL EXCL 50/239 7/2000 DLCround-PT-06a-CTLFireability-2024-03 1576373 m, 30355 m/sec, 73951985 t fired, .
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[lola][.] 10 CTL EXCL 55/239 8/2000 DLCround-PT-06a-CTLFireability-2024-03 1720744 m, 28874 m/sec, 81097998 t fired, .
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[lola][.] 10 CTL EXCL 60/239 8/2000 DLCround-PT-06a-CTLFireability-2024-03 1876119 m, 31075 m/sec, 88546288 t fired, .
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[lola][.] 10 CTL EXCL 65/239 9/2000 DLCround-PT-06a-CTLFireability-2024-03 2026032 m, 29982 m/sec, 95863162 t fired, .
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[lola][.] DLCround-PT-06a-CTLFireability-2024-05: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-11: AGEF 0 1 0 0 3 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 50 CTL EXCL 1/251 1/2000 DLCround-PT-06a-CTLFireability-2023-15 17827 m, 3565 m/sec, 338719 t fired, .
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[lola][I] FINISHED task # 50 (type EXCL) for DLCround-PT-06a-CTLFireability-2023-15
[lola][I] result : false
[lola][I] markings : 53428
[lola][I] fired transitions : 1030649
[lola][I] time used : 1
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 47 (type EXCL) for 46 DLCround-PT-06a-CTLFireability-2023-14
[lola][I] time limit : 270 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-06a-CTLFireability-2024-00: INITIAL false preprocessing
[lola][.] DLCround-PT-06a-CTLFireability-2024-01: INITIAL false preprocessing
[lola][.] DLCround-PT-06a-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] DLCround-PT-06a-CTLFireability-2023-15: CTL false CTL model checker
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[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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[lola][.] DLCround-PT-06a-CTLFireability-2024-05: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-11: AGEF 0 1 0 0 3 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 47 CTL EXCL 5/270 2/2000 DLCround-PT-06a-CTLFireability-2023-14 318415 m, 63683 m/sec, 5878376 t fired, .
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[lola][.] DLCround-PT-06a-CTLFireability-2024-01: INITIAL false preprocessing
[lola][.] DLCround-PT-06a-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] DLCround-PT-06a-CTLFireability-2023-15: CTL false CTL model checker
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[lola][.] DLCround-PT-06a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-05: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-11: AGEF 0 1 0 0 3 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 47 CTL EXCL 10/270 3/2000 DLCround-PT-06a-CTLFireability-2023-14 579899 m, 52296 m/sec, 10863681 t fired, .
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[lola][.] DLCround-PT-06a-CTLFireability-2024-01: INITIAL false preprocessing
[lola][.] DLCround-PT-06a-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] DLCround-PT-06a-CTLFireability-2023-15: CTL false CTL model checker
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[lola][.] DLCround-PT-06a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-05: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-11: AGEF 0 1 0 0 3 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 47 CTL EXCL 15/270 4/2000 DLCround-PT-06a-CTLFireability-2023-14 796658 m, 43351 m/sec, 15276410 t fired, .
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[lola][.] DLCround-PT-06a-CTLFireability-2024-01: INITIAL false preprocessing
[lola][.] DLCround-PT-06a-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] DLCround-PT-06a-CTLFireability-2023-15: CTL false CTL model checker
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[lola][.] DLCround-PT-06a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-05: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-11: AGEF 0 1 0 0 3 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 47 CTL EXCL 20/270 5/2000 DLCround-PT-06a-CTLFireability-2023-14 1071956 m, 55059 m/sec, 19331417 t fired, .
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[lola][.] DLCround-PT-06a-CTLFireability-2024-01: INITIAL false preprocessing
[lola][.] DLCround-PT-06a-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] DLCround-PT-06a-CTLFireability-2023-15: CTL false CTL model checker
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[lola][.] DLCround-PT-06a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-05: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-11: AGEF 0 1 0 0 3 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 47 CTL EXCL 25/270 6/2000 DLCround-PT-06a-CTLFireability-2023-14 1341075 m, 53823 m/sec, 23133946 t fired, .
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[lola][.] DLCround-PT-06a-CTLFireability-2024-01: INITIAL false preprocessing
[lola][.] DLCround-PT-06a-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] DLCround-PT-06a-CTLFireability-2023-15: CTL false CTL model checker
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[lola][.] DLCround-PT-06a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-05: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-11: AGEF 0 1 0 0 3 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 47 CTL EXCL 30/270 7/2000 DLCround-PT-06a-CTLFireability-2023-14 1619631 m, 55711 m/sec, 26913271 t fired, .
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[lola][.] DLCround-PT-06a-CTLFireability-2024-01: INITIAL false preprocessing
[lola][.] DLCround-PT-06a-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] DLCround-PT-06a-CTLFireability-2023-15: CTL false CTL model checker
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[lola][.] DLCround-PT-06a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-05: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-11: AGEF 0 1 0 0 3 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 47 CTL EXCL 35/270 8/2000 DLCround-PT-06a-CTLFireability-2023-14 1802983 m, 36670 m/sec, 31239702 t fired, .
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[lola][.] DLCround-PT-06a-CTLFireability-2024-05: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-11: AGEF 0 1 0 0 3 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[lola][.] 47 CTL EXCL 40/270 9/2000 DLCround-PT-06a-CTLFireability-2023-14 1985612 m, 36525 m/sec, 35557045 t fired, .
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[lola][.] DLCround-PT-06a-CTLFireability-2024-05: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-11: AGEF 0 1 0 0 3 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[lola][.] 47 CTL EXCL 45/270 10/2000 DLCround-PT-06a-CTLFireability-2023-14 2177718 m, 38421 m/sec, 39266741 t fired, .
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[lola][.] DLCround-PT-06a-CTLFireability-2024-05: CONJ 0 2 0 0 2 0 0 0
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[lola][.] DLCround-PT-06a-CTLFireability-2024-11: AGEF 0 1 0 0 3 0 0 0
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[lola][.] 47 CTL EXCL 50/270 10/2000 DLCround-PT-06a-CTLFireability-2023-14 2360565 m, 36569 m/sec, 43547999 t fired, .
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[lola][.] 47 CTL EXCL 55/270 11/2000 DLCround-PT-06a-CTLFireability-2023-14 2534265 m, 34740 m/sec, 47520344 t fired, .
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[lola][.] 47 CTL EXCL 60/270 12/2000 DLCround-PT-06a-CTLFireability-2023-14 2711191 m, 35385 m/sec, 51374592 t fired, .
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[lola][.] 47 CTL EXCL 65/270 12/2000 DLCround-PT-06a-CTLFireability-2023-14 2836950 m, 25151 m/sec, 56228943 t fired, .
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[lola][.] 47 CTL EXCL 70/270 13/2000 DLCround-PT-06a-CTLFireability-2023-14 2916407 m, 15891 m/sec, 61475840 t fired, .
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[lola][.] 47 CTL EXCL 75/270 13/2000 DLCround-PT-06a-CTLFireability-2023-14 3002595 m, 17237 m/sec, 66886512 t fired, .
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[lola][.] 47 CTL EXCL 105/270 16/2000 DLCround-PT-06a-CTLFireability-2023-14 3725007 m, 22601 m/sec, 97399767 t fired, .
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[lola][.] 47 CTL EXCL 160/270 24/2000 DLCround-PT-06a-CTLFireability-2023-14 5626625 m, 39255 m/sec, 151418631 t fired, .
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[lola][.] 41 CTL EXCL 40/269 1/2000 DLCround-PT-06a-CTLFireability-2023-12 234212 m, 4747 m/sec, 3980205 t fired, .
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[lola][.] 41 CTL EXCL 45/269 2/2000 DLCround-PT-06a-CTLFireability-2023-12 276859 m, 8529 m/sec, 4536417 t fired, .
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[lola][.] 41 CTL EXCL 95/269 4/2000 DLCround-PT-06a-CTLFireability-2023-12 733712 m, 8588 m/sec, 10019111 t fired, .
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[lola][.] 41 CTL EXCL 100/269 4/2000 DLCround-PT-06a-CTLFireability-2023-12 777295 m, 8716 m/sec, 10573435 t fired, .
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[lola][.] 41 CTL EXCL 105/269 4/2000 DLCround-PT-06a-CTLFireability-2023-12 820536 m, 8648 m/sec, 11119984 t fired, .
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[lola][.] 41 CTL EXCL 120/269 5/2000 DLCround-PT-06a-CTLFireability-2023-12 983318 m, 12326 m/sec, 12737211 t fired, .
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[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCround-PT-06a-CTLFireability-2024-00: INITIAL false preprocessing
[lola][.] DLCround-PT-06a-CTLFireability-2024-01: INITIAL false preprocessing
[lola][.] DLCround-PT-06a-CTLFireability-2024-03: CTL false CTL model checker
[lola][.] DLCround-PT-06a-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCround-PT-06a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-05: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2024-11: AGEF 0 1 0 0 3 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCround-PT-06a-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 41 CTL EXCL 161/269 5/2000 DLCround-PT-06a-CTLFireability-2023-12 1105530 m, 15 m/sec, 14816140 t fired, .
[lola][.]
[lola][.] Time elapsed: 524 secs. Pages in use: 48
[lola][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 407 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-06a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is DLCround-PT-06a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r115-smll-171624276500162"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-06a.tgz
mv DLCround-PT-06a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;