About the Execution of LoLA for DLCround-PT-05b
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
16206.892 | 888949.00 | 1002468.00 | 3752.30 | ???F???F?TF????F | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r115-smll-171624276500154.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is DLCround-PT-05b, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r115-smll-171624276500154
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.3M
-rw-r--r-- 1 mcc users 7.4K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 81K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.2K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 58K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K May 19 07:08 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K May 19 15:43 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Apr 22 14:37 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 22 14:37 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Apr 13 12:29 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 128K Apr 13 12:29 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 15K Apr 13 12:29 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 145K Apr 13 12:29 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 22 14:37 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Apr 22 14:37 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 4 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 674K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-05b-CTLFireability-2024-00
FORMULA_NAME DLCround-PT-05b-CTLFireability-2024-01
FORMULA_NAME DLCround-PT-05b-CTLFireability-2024-02
FORMULA_NAME DLCround-PT-05b-CTLFireability-2024-03
FORMULA_NAME DLCround-PT-05b-CTLFireability-2024-04
FORMULA_NAME DLCround-PT-05b-CTLFireability-2024-05
FORMULA_NAME DLCround-PT-05b-CTLFireability-2024-06
FORMULA_NAME DLCround-PT-05b-CTLFireability-2024-07
FORMULA_NAME DLCround-PT-05b-CTLFireability-2024-08
FORMULA_NAME DLCround-PT-05b-CTLFireability-2024-09
FORMULA_NAME DLCround-PT-05b-CTLFireability-2024-10
FORMULA_NAME DLCround-PT-05b-CTLFireability-2024-11
FORMULA_NAME DLCround-PT-05b-CTLFireability-2023-12
FORMULA_NAME DLCround-PT-05b-CTLFireability-2023-13
FORMULA_NAME DLCround-PT-05b-CTLFireability-2023-14
FORMULA_NAME DLCround-PT-05b-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717064852550
FORMULA DLCround-PT-05b-CTLFireability-2024-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-05b-CTLFireability-2024-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-05b-CTLFireability-2023-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-05b-CTLFireability-2024-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-05b-CTLFireability-2024-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717065741499
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 31 (type EXCL) for 30 DLCround-PT-05b-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 209 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 57 (type EQUN) for 45 DLCround-PT-05b-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 54 (type EQUN) for 21 DLCround-PT-05b-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 59 (type EQUN) for 21 DLCround-PT-05b-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 31 (type EXCL) for DLCround-PT-05b-CTLFireability-2024-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] fired transitions : 5
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 51 (type EXCL) for 21 DLCround-PT-05b-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 222 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 51 (type EXCL) for DLCround-PT-05b-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 80
[[35mlola[0m][I] fired transitions : 80
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 54 (type EQUN) for DLCround-PT-05b-CTLFireability-2024-07 (obsolete)
[[35mlola[0m][W] CANCELED task # 59 (type EQUN) for DLCround-PT-05b-CTLFireability-2024-07 (obsolete)
[[35mlola[0m][I] LAUNCH task # 49 (type EXCL) for 45 DLCround-PT-05b-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 237 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 49 (type EXCL) for DLCround-PT-05b-CTLFireability-2023-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 78
[[35mlola[0m][I] fired transitions : 78
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 57 (type EQUN) for DLCround-PT-05b-CTLFireability-2023-15 (obsolete)
[[35mlola[0m][I] LAUNCH task # 28 (type EXCL) for 27 DLCround-PT-05b-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 273 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 28 (type EXCL) for DLCround-PT-05b-CTLFireability-2024-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] fired transitions : 2
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 63 (type EXCL) for 9 DLCround-PT-05b-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 296 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 61 (type FNDP) for 9 DLCround-PT-05b-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 62 (type EQUN) for 9 DLCround-PT-05b-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 61 (type FNDP) for DLCround-PT-05b-CTLFireability-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] FINISHED task # 54 (type EQUN) for DLCround-PT-05b-CTLFireability-2024-07
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 57 (type EQUN) for DLCround-PT-05b-CTLFireability-2023-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 59 (type EQUN) for DLCround-PT-05b-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 1 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-03: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 1 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 EF STEQ 1/3555 0/5 DLCround-PT-05b-CTLFireability-2024-03 sara not yet started (preprocessing).
[[35mlola[0m][.] 63 EF EXCL 1/296 1/2000 DLCround-PT-05b-CTLFireability-2024-03 --
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 46 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 62 (type EQUN) for DLCround-PT-05b-CTLFireability-2024-03 (obsolete)
[[35mlola[0m][W] CANCELED task # 63 (type EXCL) for DLCround-PT-05b-CTLFireability-2024-03 (obsolete)
[[35mlola[0m][I] LAUNCH task # 43 (type EXCL) for 42 DLCround-PT-05b-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 323 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 63 (type EXCL) for DLCround-PT-05b-CTLFireability-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 8
[[35mlola[0m][I] fired transitions : 7
[[35mlola[0m][I] time used : 2
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] FINISHED task # 62 (type EQUN) for DLCround-PT-05b-CTLFireability-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 68 (type EQUN) for 0 DLCround-PT-05b-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 68 (type EQUN) for DLCround-PT-05b-CTLFireability-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 4/323 3/2000 DLCround-PT-05b-CTLFireability-2023-14 341107 m, 68221 m/sec, 393738 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 51 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 9/323 6/2000 DLCround-PT-05b-CTLFireability-2023-14 789092 m, 89597 m/sec, 917064 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 56 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 14/323 9/2000 DLCround-PT-05b-CTLFireability-2023-14 1234741 m, 89129 m/sec, 1436415 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 61 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 19/323 13/2000 DLCround-PT-05b-CTLFireability-2023-14 1688448 m, 90741 m/sec, 1963353 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 66 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 24/323 16/2000 DLCround-PT-05b-CTLFireability-2023-14 2139146 m, 90139 m/sec, 2486734 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 71 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 29/323 19/2000 DLCround-PT-05b-CTLFireability-2023-14 2582306 m, 88632 m/sec, 3001245 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 76 secs. Pages in use: 19
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 34/323 22/2000 DLCround-PT-05b-CTLFireability-2023-14 3031677 m, 89874 m/sec, 3523856 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 81 secs. Pages in use: 22
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 39/323 25/2000 DLCround-PT-05b-CTLFireability-2023-14 3471329 m, 87930 m/sec, 4036250 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 86 secs. Pages in use: 25
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 44/323 27/2000 DLCround-PT-05b-CTLFireability-2023-14 3906565 m, 87047 m/sec, 4546587 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 91 secs. Pages in use: 27
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 49/323 31/2000 DLCround-PT-05b-CTLFireability-2023-14 4358068 m, 90300 m/sec, 5072787 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 96 secs. Pages in use: 31
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 54/323 34/2000 DLCround-PT-05b-CTLFireability-2023-14 4802416 m, 88869 m/sec, 5590797 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 101 secs. Pages in use: 34
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 59/323 36/2000 DLCround-PT-05b-CTLFireability-2023-14 5246283 m, 88773 m/sec, 6108278 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 106 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 64/323 39/2000 DLCround-PT-05b-CTLFireability-2023-14 5690210 m, 88785 m/sec, 6624803 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 111 secs. Pages in use: 39
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 69/323 42/2000 DLCround-PT-05b-CTLFireability-2023-14 6120413 m, 86040 m/sec, 7127715 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 116 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 74/323 45/2000 DLCround-PT-05b-CTLFireability-2023-14 6549606 m, 85838 m/sec, 7629595 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 121 secs. Pages in use: 45
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 79/323 47/2000 DLCround-PT-05b-CTLFireability-2023-14 6982666 m, 86612 m/sec, 8138851 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 126 secs. Pages in use: 47
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 84/323 50/2000 DLCround-PT-05b-CTLFireability-2023-14 7412650 m, 85996 m/sec, 8641480 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 131 secs. Pages in use: 50
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 89/323 53/2000 DLCround-PT-05b-CTLFireability-2023-14 7838673 m, 85204 m/sec, 9143242 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 136 secs. Pages in use: 53
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 94/323 55/2000 DLCround-PT-05b-CTLFireability-2023-14 8265621 m, 85389 m/sec, 9644202 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 141 secs. Pages in use: 55
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 99/323 58/2000 DLCround-PT-05b-CTLFireability-2023-14 8691540 m, 85183 m/sec, 10148206 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 146 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 104/323 60/2000 DLCround-PT-05b-CTLFireability-2023-14 9115721 m, 84836 m/sec, 10649710 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 151 secs. Pages in use: 60
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 109/323 63/2000 DLCround-PT-05b-CTLFireability-2023-14 9537320 m, 84319 m/sec, 11144858 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 156 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 114/323 65/2000 DLCround-PT-05b-CTLFireability-2023-14 9957527 m, 84041 m/sec, 11637489 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 161 secs. Pages in use: 65
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 119/323 67/2000 DLCround-PT-05b-CTLFireability-2023-14 10376804 m, 83855 m/sec, 12132582 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 166 secs. Pages in use: 67
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 124/323 70/2000 DLCround-PT-05b-CTLFireability-2023-14 10794145 m, 83468 m/sec, 12624129 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 171 secs. Pages in use: 70
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 129/323 72/2000 DLCround-PT-05b-CTLFireability-2023-14 11216873 m, 84545 m/sec, 13120283 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 176 secs. Pages in use: 72
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 134/323 75/2000 DLCround-PT-05b-CTLFireability-2023-14 11639569 m, 84539 m/sec, 13617706 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 181 secs. Pages in use: 75
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 139/323 78/2000 DLCround-PT-05b-CTLFireability-2023-14 12070486 m, 86183 m/sec, 14119122 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 186 secs. Pages in use: 78
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 144/323 81/2000 DLCround-PT-05b-CTLFireability-2023-14 12493816 m, 84666 m/sec, 14615253 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 191 secs. Pages in use: 81
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 149/323 83/2000 DLCround-PT-05b-CTLFireability-2023-14 12902937 m, 81824 m/sec, 15093299 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 196 secs. Pages in use: 83
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 154/323 86/2000 DLCround-PT-05b-CTLFireability-2023-14 13334768 m, 86366 m/sec, 15596355 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 201 secs. Pages in use: 86
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 159/323 89/2000 DLCround-PT-05b-CTLFireability-2023-14 13769745 m, 86995 m/sec, 16102877 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 206 secs. Pages in use: 89
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 164/323 92/2000 DLCround-PT-05b-CTLFireability-2023-14 14190081 m, 84067 m/sec, 16600217 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 211 secs. Pages in use: 92
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 169/323 94/2000 DLCround-PT-05b-CTLFireability-2023-14 14615480 m, 85079 m/sec, 17099814 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 216 secs. Pages in use: 94
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 174/323 97/2000 DLCround-PT-05b-CTLFireability-2023-14 15045440 m, 85992 m/sec, 17601528 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 221 secs. Pages in use: 97
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 179/323 100/2000 DLCround-PT-05b-CTLFireability-2023-14 15465313 m, 83974 m/sec, 18098894 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 226 secs. Pages in use: 100
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 184/323 102/2000 DLCround-PT-05b-CTLFireability-2023-14 15880634 m, 83064 m/sec, 18587614 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 231 secs. Pages in use: 102
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 189/323 104/2000 DLCround-PT-05b-CTLFireability-2023-14 16293466 m, 82566 m/sec, 19075626 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 236 secs. Pages in use: 104
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 194/323 107/2000 DLCround-PT-05b-CTLFireability-2023-14 16712770 m, 83860 m/sec, 19564341 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 241 secs. Pages in use: 107
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 199/323 110/2000 DLCround-PT-05b-CTLFireability-2023-14 17121555 m, 81757 m/sec, 20041715 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 246 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 204/323 113/2000 DLCround-PT-05b-CTLFireability-2023-14 17548229 m, 85334 m/sec, 20539845 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 251 secs. Pages in use: 113
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 209/323 115/2000 DLCround-PT-05b-CTLFireability-2023-14 17982274 m, 86809 m/sec, 21048393 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 256 secs. Pages in use: 115
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 214/323 119/2000 DLCround-PT-05b-CTLFireability-2023-14 18427280 m, 89001 m/sec, 21565270 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 261 secs. Pages in use: 119
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 219/323 122/2000 DLCround-PT-05b-CTLFireability-2023-14 18876858 m, 89915 m/sec, 22087091 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 266 secs. Pages in use: 122
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 224/323 125/2000 DLCround-PT-05b-CTLFireability-2023-14 19319308 m, 88490 m/sec, 22604414 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 271 secs. Pages in use: 125
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 229/323 128/2000 DLCround-PT-05b-CTLFireability-2023-14 19768776 m, 89893 m/sec, 23126993 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 276 secs. Pages in use: 128
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 234/323 131/2000 DLCround-PT-05b-CTLFireability-2023-14 20208181 m, 87881 m/sec, 23641963 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 281 secs. Pages in use: 131
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 239/323 134/2000 DLCround-PT-05b-CTLFireability-2023-14 20647905 m, 87944 m/sec, 24156176 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 286 secs. Pages in use: 134
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 244/323 137/2000 DLCround-PT-05b-CTLFireability-2023-14 21094106 m, 89240 m/sec, 24678012 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 291 secs. Pages in use: 137
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 249/323 139/2000 DLCround-PT-05b-CTLFireability-2023-14 21531992 m, 87577 m/sec, 25189467 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 296 secs. Pages in use: 139
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 254/323 142/2000 DLCround-PT-05b-CTLFireability-2023-14 21964359 m, 86473 m/sec, 25697361 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 301 secs. Pages in use: 142
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 259/323 144/2000 DLCround-PT-05b-CTLFireability-2023-14 22392935 m, 85715 m/sec, 26202479 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 306 secs. Pages in use: 144
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 264/323 147/2000 DLCround-PT-05b-CTLFireability-2023-14 22819553 m, 85323 m/sec, 26706118 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 311 secs. Pages in use: 147
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 269/323 150/2000 DLCround-PT-05b-CTLFireability-2023-14 23244458 m, 84981 m/sec, 27205978 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 316 secs. Pages in use: 150
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 274/323 152/2000 DLCround-PT-05b-CTLFireability-2023-14 23670533 m, 85215 m/sec, 27701709 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 321 secs. Pages in use: 152
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 279/323 155/2000 DLCround-PT-05b-CTLFireability-2023-14 24055095 m, 76912 m/sec, 28152809 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 326 secs. Pages in use: 155
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 284/323 158/2000 DLCround-PT-05b-CTLFireability-2023-14 24479573 m, 84895 m/sec, 28646261 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 331 secs. Pages in use: 158
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 289/323 161/2000 DLCround-PT-05b-CTLFireability-2023-14 24902418 m, 84569 m/sec, 29139496 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 336 secs. Pages in use: 161
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 294/323 163/2000 DLCround-PT-05b-CTLFireability-2023-14 25328364 m, 85189 m/sec, 29635980 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 341 secs. Pages in use: 163
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 299/323 166/2000 DLCround-PT-05b-CTLFireability-2023-14 25751593 m, 84645 m/sec, 30131496 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 346 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 304/323 169/2000 DLCround-PT-05b-CTLFireability-2023-14 26172728 m, 84227 m/sec, 30626125 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 351 secs. Pages in use: 169
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 309/323 171/2000 DLCround-PT-05b-CTLFireability-2023-14 26593397 m, 84133 m/sec, 31118752 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 356 secs. Pages in use: 171
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 314/323 174/2000 DLCround-PT-05b-CTLFireability-2023-14 27012617 m, 83844 m/sec, 31609729 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 361 secs. Pages in use: 174
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 319/323 176/2000 DLCround-PT-05b-CTLFireability-2023-14 27429958 m, 83468 m/sec, 32098884 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 366 secs. Pages in use: 176
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 43 (type EXCL) for DLCround-PT-05b-CTLFireability-2023-14 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-00: AXAF 0 1 0 0 2 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 371 secs. Pages in use: 179
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 65 (type EXCL) for 0 DLCround-PT-05b-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 322 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 43 (type EXCL) for 42 DLCround-PT-05b-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 3229 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 65 (type EXCL) for DLCround-PT-05b-CTLFireability-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 471
[[35mlola[0m][I] fired transitions : 471
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 5/322 4/5 DLCround-PT-05b-CTLFireability-2023-14 423287 m, -5401334 m/sec, 489204 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 376 secs. Pages in use: 183
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 43 (type EXCL) for DLCround-PT-05b-CTLFireability-2023-14 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 381 secs. Pages in use: 184
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 40 (type EXCL) for 39 DLCround-PT-05b-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 357 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 40 (type EXCL) for DLCround-PT-05b-CTLFireability-2023-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 72
[[35mlola[0m][I] fired transitions : 72
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 37 (type EXCL) for 36 DLCround-PT-05b-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 402 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 5/402 4/2000 DLCround-PT-05b-CTLFireability-2023-12 445087 m, 89017 m/sec, 512080 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 386 secs. Pages in use: 184
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 10/402 7/2000 DLCround-PT-05b-CTLFireability-2023-12 892861 m, 89554 m/sec, 1033080 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 391 secs. Pages in use: 186
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 15/402 10/2000 DLCround-PT-05b-CTLFireability-2023-12 1339388 m, 89305 m/sec, 1551005 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 396 secs. Pages in use: 189
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 20/402 13/2000 DLCround-PT-05b-CTLFireability-2023-12 1779683 m, 88059 m/sec, 2062974 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 401 secs. Pages in use: 192
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 25/402 16/2000 DLCround-PT-05b-CTLFireability-2023-12 2224860 m, 89035 m/sec, 2580548 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 406 secs. Pages in use: 195
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 30/402 19/2000 DLCround-PT-05b-CTLFireability-2023-12 2658725 m, 86773 m/sec, 3085581 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 411 secs. Pages in use: 198
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 35/402 22/2000 DLCround-PT-05b-CTLFireability-2023-12 3087787 m, 85812 m/sec, 3588808 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 416 secs. Pages in use: 201
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 40/402 25/2000 DLCround-PT-05b-CTLFireability-2023-12 3523471 m, 87136 m/sec, 4096650 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 421 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 45/402 28/2000 DLCround-PT-05b-CTLFireability-2023-12 3964382 m, 88182 m/sec, 4609840 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 426 secs. Pages in use: 207
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 50/402 31/2000 DLCround-PT-05b-CTLFireability-2023-12 4392221 m, 85567 m/sec, 5111187 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 431 secs. Pages in use: 210
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 55/402 33/2000 DLCround-PT-05b-CTLFireability-2023-12 4819699 m, 85495 m/sec, 5611076 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 436 secs. Pages in use: 212
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 60/402 36/2000 DLCround-PT-05b-CTLFireability-2023-12 5243901 m, 84840 m/sec, 6108887 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 441 secs. Pages in use: 215
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 65/402 39/2000 DLCround-PT-05b-CTLFireability-2023-12 5683490 m, 87917 m/sec, 6620155 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 446 secs. Pages in use: 218
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 70/402 42/2000 DLCround-PT-05b-CTLFireability-2023-12 6110272 m, 85356 m/sec, 7119405 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 451 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 75/402 44/2000 DLCround-PT-05b-CTLFireability-2023-12 6533457 m, 84637 m/sec, 7616683 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 456 secs. Pages in use: 223
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 80/402 46/2000 DLCround-PT-05b-CTLFireability-2023-12 6954940 m, 84296 m/sec, 8109734 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 461 secs. Pages in use: 225
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 85/402 49/2000 DLCround-PT-05b-CTLFireability-2023-12 7375114 m, 84034 m/sec, 8602854 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 466 secs. Pages in use: 228
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 90/402 51/2000 DLCround-PT-05b-CTLFireability-2023-12 7796047 m, 84186 m/sec, 9096901 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 471 secs. Pages in use: 230
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 95/402 54/2000 DLCround-PT-05b-CTLFireability-2023-12 8209415 m, 82673 m/sec, 9585502 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 476 secs. Pages in use: 233
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 100/402 56/2000 DLCround-PT-05b-CTLFireability-2023-12 8623747 m, 82866 m/sec, 10076763 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 481 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 105/402 58/2000 DLCround-PT-05b-CTLFireability-2023-12 9041083 m, 83467 m/sec, 10568970 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 486 secs. Pages in use: 237
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 110/402 61/2000 DLCround-PT-05b-CTLFireability-2023-12 9457776 m, 83338 m/sec, 11057224 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 491 secs. Pages in use: 240
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 115/402 63/2000 DLCround-PT-05b-CTLFireability-2023-12 9872040 m, 82852 m/sec, 11546042 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 496 secs. Pages in use: 242
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 120/402 66/2000 DLCround-PT-05b-CTLFireability-2023-12 10288284 m, 83248 m/sec, 12036887 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 501 secs. Pages in use: 245
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 125/402 68/2000 DLCround-PT-05b-CTLFireability-2023-12 10708981 m, 84139 m/sec, 12528935 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 506 secs. Pages in use: 247
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 130/402 71/2000 DLCround-PT-05b-CTLFireability-2023-12 11127575 m, 83718 m/sec, 13021982 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 511 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 135/402 73/2000 DLCround-PT-05b-CTLFireability-2023-12 11541446 m, 82774 m/sec, 13509442 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 516 secs. Pages in use: 252
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 140/402 75/2000 DLCround-PT-05b-CTLFireability-2023-12 11932588 m, 78228 m/sec, 13971346 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 521 secs. Pages in use: 254
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 145/402 78/2000 DLCround-PT-05b-CTLFireability-2023-12 12340703 m, 81623 m/sec, 14454135 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 526 secs. Pages in use: 257
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 150/402 80/2000 DLCround-PT-05b-CTLFireability-2023-12 12756876 m, 83234 m/sec, 14944538 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 531 secs. Pages in use: 259
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 155/402 82/2000 DLCround-PT-05b-CTLFireability-2023-12 13168878 m, 82400 m/sec, 15432013 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 536 secs. Pages in use: 261
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 160/402 85/2000 DLCround-PT-05b-CTLFireability-2023-12 13580222 m, 82268 m/sec, 15919410 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 541 secs. Pages in use: 264
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 165/402 87/2000 DLCround-PT-05b-CTLFireability-2023-12 13988250 m, 81605 m/sec, 16398835 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 546 secs. Pages in use: 266
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 170/402 89/2000 DLCround-PT-05b-CTLFireability-2023-12 14398422 m, 82034 m/sec, 16884076 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 551 secs. Pages in use: 268
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 175/402 92/2000 DLCround-PT-05b-CTLFireability-2023-12 14808279 m, 81971 m/sec, 17368828 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 556 secs. Pages in use: 271
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 180/402 94/2000 DLCround-PT-05b-CTLFireability-2023-12 15227901 m, 83924 m/sec, 17862165 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 561 secs. Pages in use: 273
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 185/402 98/2000 DLCround-PT-05b-CTLFireability-2023-12 15675940 m, 89607 m/sec, 18382747 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 566 secs. Pages in use: 277
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 190/402 101/2000 DLCround-PT-05b-CTLFireability-2023-12 16115546 m, 87921 m/sec, 18894096 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 571 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 195/402 104/2000 DLCround-PT-05b-CTLFireability-2023-12 16550237 m, 86938 m/sec, 19401585 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 576 secs. Pages in use: 283
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 200/402 107/2000 DLCround-PT-05b-CTLFireability-2023-12 16993724 m, 88697 m/sec, 19918115 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 581 secs. Pages in use: 286
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 205/402 109/2000 DLCround-PT-05b-CTLFireability-2023-12 17427767 m, 86808 m/sec, 20426365 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 586 secs. Pages in use: 288
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 210/402 112/2000 DLCround-PT-05b-CTLFireability-2023-12 17856689 m, 85784 m/sec, 20928996 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 591 secs. Pages in use: 291
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 215/402 114/2000 DLCround-PT-05b-CTLFireability-2023-12 18282699 m, 85202 m/sec, 21430412 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 596 secs. Pages in use: 293
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 220/402 117/2000 DLCround-PT-05b-CTLFireability-2023-12 18717495 m, 86959 m/sec, 21938328 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 601 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 225/402 120/2000 DLCround-PT-05b-CTLFireability-2023-12 19150542 m, 86609 m/sec, 22444464 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 606 secs. Pages in use: 299
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 230/402 123/2000 DLCround-PT-05b-CTLFireability-2023-12 19592770 m, 88445 m/sec, 22961397 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 611 secs. Pages in use: 302
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 235/402 127/2000 DLCround-PT-05b-CTLFireability-2023-12 20047334 m, 90912 m/sec, 23483657 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 616 secs. Pages in use: 306
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 240/402 130/2000 DLCround-PT-05b-CTLFireability-2023-12 20483371 m, 87207 m/sec, 23992424 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 621 secs. Pages in use: 309
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 245/402 133/2000 DLCround-PT-05b-CTLFireability-2023-12 20920980 m, 87521 m/sec, 24500548 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 626 secs. Pages in use: 312
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 250/402 136/2000 DLCround-PT-05b-CTLFireability-2023-12 21356791 m, 87162 m/sec, 25006583 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 631 secs. Pages in use: 315
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 255/402 139/2000 DLCround-PT-05b-CTLFireability-2023-12 21789920 m, 86625 m/sec, 25509794 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 636 secs. Pages in use: 318
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 260/402 142/2000 DLCround-PT-05b-CTLFireability-2023-12 22219988 m, 86013 m/sec, 26009871 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 641 secs. Pages in use: 321
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 265/402 144/2000 DLCround-PT-05b-CTLFireability-2023-12 22639980 m, 83998 m/sec, 26501987 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 646 secs. Pages in use: 323
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 270/402 147/2000 DLCround-PT-05b-CTLFireability-2023-12 23066431 m, 85290 m/sec, 27000063 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 651 secs. Pages in use: 326
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 275/402 150/2000 DLCround-PT-05b-CTLFireability-2023-12 23499863 m, 86686 m/sec, 27503890 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 656 secs. Pages in use: 329
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 280/402 153/2000 DLCround-PT-05b-CTLFireability-2023-12 23922146 m, 84456 m/sec, 27998378 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 661 secs. Pages in use: 332
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 285/402 155/2000 DLCround-PT-05b-CTLFireability-2023-12 24340724 m, 83715 m/sec, 28487543 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 666 secs. Pages in use: 334
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 290/402 158/2000 DLCround-PT-05b-CTLFireability-2023-12 24751991 m, 82253 m/sec, 28971261 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 671 secs. Pages in use: 337
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 295/402 161/2000 DLCround-PT-05b-CTLFireability-2023-12 25180836 m, 85769 m/sec, 29470436 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 676 secs. Pages in use: 340
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 300/402 164/2000 DLCround-PT-05b-CTLFireability-2023-12 25608882 m, 85609 m/sec, 29968722 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 681 secs. Pages in use: 343
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 305/402 166/2000 DLCround-PT-05b-CTLFireability-2023-12 26026301 m, 83483 m/sec, 30458931 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 686 secs. Pages in use: 345
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 310/402 169/2000 DLCround-PT-05b-CTLFireability-2023-12 26440377 m, 82815 m/sec, 30944438 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 691 secs. Pages in use: 348
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 315/402 171/2000 DLCround-PT-05b-CTLFireability-2023-12 26847933 m, 81511 m/sec, 31423017 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 696 secs. Pages in use: 350
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 320/402 173/2000 DLCround-PT-05b-CTLFireability-2023-12 27254559 m, 81325 m/sec, 31900032 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 701 secs. Pages in use: 352
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 325/402 176/2000 DLCround-PT-05b-CTLFireability-2023-12 27663617 m, 81811 m/sec, 32379641 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 706 secs. Pages in use: 355
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 330/402 178/2000 DLCround-PT-05b-CTLFireability-2023-12 28066214 m, 80519 m/sec, 32856210 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 711 secs. Pages in use: 357
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 335/402 180/2000 DLCround-PT-05b-CTLFireability-2023-12 28476517 m, 82060 m/sec, 33341274 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 716 secs. Pages in use: 359
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 340/402 183/2000 DLCround-PT-05b-CTLFireability-2023-12 28890105 m, 82717 m/sec, 33829482 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 721 secs. Pages in use: 362
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 345/402 185/2000 DLCround-PT-05b-CTLFireability-2023-12 29298728 m, 81724 m/sec, 34309018 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 726 secs. Pages in use: 364
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 350/402 188/2000 DLCround-PT-05b-CTLFireability-2023-12 29703087 m, 80871 m/sec, 34786417 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 731 secs. Pages in use: 367
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 355/402 190/2000 DLCround-PT-05b-CTLFireability-2023-12 30114222 m, 82227 m/sec, 35269611 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 736 secs. Pages in use: 369
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 360/402 192/2000 DLCround-PT-05b-CTLFireability-2023-12 30526396 m, 82434 m/sec, 35752189 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 741 secs. Pages in use: 371
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 365/402 195/2000 DLCround-PT-05b-CTLFireability-2023-12 30934528 m, 81626 m/sec, 36234181 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 746 secs. Pages in use: 374
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 370/402 197/2000 DLCround-PT-05b-CTLFireability-2023-12 31340442 m, 81182 m/sec, 36711428 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 751 secs. Pages in use: 376
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 375/402 199/2000 DLCround-PT-05b-CTLFireability-2023-12 31742605 m, 80432 m/sec, 37187864 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 756 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 380/402 202/2000 DLCround-PT-05b-CTLFireability-2023-12 32145864 m, 80651 m/sec, 37663036 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 761 secs. Pages in use: 381
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 385/402 204/2000 DLCround-PT-05b-CTLFireability-2023-12 32549102 m, 80647 m/sec, 38138404 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 766 secs. Pages in use: 383
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 390/402 206/2000 DLCround-PT-05b-CTLFireability-2023-12 32951545 m, 80488 m/sec, 38616132 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 771 secs. Pages in use: 385
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 395/402 208/2000 DLCround-PT-05b-CTLFireability-2023-12 33357123 m, 81115 m/sec, 39094657 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 776 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 400/402 211/2000 DLCround-PT-05b-CTLFireability-2023-12 33756608 m, 79897 m/sec, 39564293 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 781 secs. Pages in use: 390
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 37 (type EXCL) for DLCround-PT-05b-CTLFireability-2023-12 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 786 secs. Pages in use: 392
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 34 (type EXCL) for 33 DLCround-PT-05b-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 402 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 37 (type EXCL) for 36 DLCround-PT-05b-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 2814 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 5/402 4/2000 DLCround-PT-05b-CTLFireability-2024-11 438832 m, 87766 m/sec, 505807 t fired, .
[[35mlola[0m][.] 37 CTL EXCL 4/2814 4/5 DLCround-PT-05b-CTLFireability-2023-12 422624 m, -6666796 m/sec, 486349 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 791 secs. Pages in use: 403
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 37 (type EXCL) for DLCround-PT-05b-CTLFireability-2023-12 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 10/402 7/2000 DLCround-PT-05b-CTLFireability-2024-11 892238 m, 90681 m/sec, 1033228 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 796 secs. Pages in use: 407
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 15/402 10/2000 DLCround-PT-05b-CTLFireability-2024-11 1358505 m, 93253 m/sec, 1574263 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 801 secs. Pages in use: 410
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 20/402 13/2000 DLCround-PT-05b-CTLFireability-2024-11 1816845 m, 91668 m/sec, 2106818 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 806 secs. Pages in use: 416
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 25/402 17/2000 DLCround-PT-05b-CTLFireability-2024-11 2280082 m, 92647 m/sec, 2645490 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 811 secs. Pages in use: 422
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 30/402 20/2000 DLCround-PT-05b-CTLFireability-2024-11 2730757 m, 90135 m/sec, 3171077 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 816 secs. Pages in use: 428
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 35/402 22/2000 DLCround-PT-05b-CTLFireability-2024-11 3169329 m, 87714 m/sec, 3685272 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 821 secs. Pages in use: 433
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 40/402 26/2000 DLCround-PT-05b-CTLFireability-2024-11 3626814 m, 91497 m/sec, 4217493 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 826 secs. Pages in use: 440
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 45/402 29/2000 DLCround-PT-05b-CTLFireability-2024-11 4080447 m, 90726 m/sec, 4747781 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 831 secs. Pages in use: 445
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 50/402 31/2000 DLCround-PT-05b-CTLFireability-2024-11 4526886 m, 89287 m/sec, 5269958 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 836 secs. Pages in use: 450
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 55/402 34/2000 DLCround-PT-05b-CTLFireability-2024-11 4969565 m, 88535 m/sec, 5788739 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 841 secs. Pages in use: 455
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 60/402 37/2000 DLCround-PT-05b-CTLFireability-2024-11 5422442 m, 90575 m/sec, 6317097 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 846 secs. Pages in use: 461
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 65/402 40/2000 DLCround-PT-05b-CTLFireability-2024-11 5871688 m, 89849 m/sec, 6840122 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 851 secs. Pages in use: 467
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 70/402 43/2000 DLCround-PT-05b-CTLFireability-2024-11 6296045 m, 84871 m/sec, 7338429 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 856 secs. Pages in use: 472
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 75/402 45/2000 DLCround-PT-05b-CTLFireability-2024-11 6716853 m, 84161 m/sec, 7831622 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 861 secs. Pages in use: 477
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 80/402 47/2000 DLCround-PT-05b-CTLFireability-2024-11 7138140 m, 84257 m/sec, 8326468 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 866 secs. Pages in use: 482
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 85/402 50/2000 DLCround-PT-05b-CTLFireability-2024-11 7556649 m, 83701 m/sec, 8818034 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 871 secs. Pages in use: 487
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 90/402 52/2000 DLCround-PT-05b-CTLFireability-2024-11 7973058 m, 83281 m/sec, 9305985 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 876 secs. Pages in use: 492
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 95/402 54/2000 DLCround-PT-05b-CTLFireability-2024-11 8324323 m, 70253 m/sec, 9721834 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 881 secs. Pages in use: 496
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-00: AXAF false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-03: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-07: AGAF false state space /EFEG[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCround-PT-05b-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCround-PT-05b-CTLFireability-2023-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCround-PT-05b-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 100/402 55/2000 DLCround-PT-05b-CTLFireability-2024-11 8398518 m, 14839 m/sec, 9810710 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 886 secs. Pages in use: 498
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 396 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-05b"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is DLCround-PT-05b, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r115-smll-171624276500154"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-05b.tgz
mv DLCround-PT-05b execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;