Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r115-smll-171624276400102.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is DLCflexbar-PT-8a, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r115-smll-171624276400102
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 9.2M
-rw-r--r-- 1 mcc users 7.9K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 86K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.5K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 48K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K Apr 22 14:37 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Apr 22 14:37 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Apr 22 14:37 LTLFireability.txt
-rw-r--r-- 1 mcc users 15K Apr 22 14:37 LTLFireability.xml
-rw-r--r-- 1 mcc users 15K Apr 14 12:51 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 157K Apr 14 12:51 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Apr 14 01:51 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 91K Apr 14 01:51 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 22 14:37 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Apr 22 14:37 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 3 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 8.7M May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCflexbar-PT-8a-ReachabilityCardinality-2024-00
FORMULA_NAME DLCflexbar-PT-8a-ReachabilityCardinality-2024-01
FORMULA_NAME DLCflexbar-PT-8a-ReachabilityCardinality-2024-02
FORMULA_NAME DLCflexbar-PT-8a-ReachabilityCardinality-2024-03
FORMULA_NAME DLCflexbar-PT-8a-ReachabilityCardinality-2024-04
FORMULA_NAME DLCflexbar-PT-8a-ReachabilityCardinality-2024-05
FORMULA_NAME DLCflexbar-PT-8a-ReachabilityCardinality-2024-06
FORMULA_NAME DLCflexbar-PT-8a-ReachabilityCardinality-2024-07
FORMULA_NAME DLCflexbar-PT-8a-ReachabilityCardinality-2024-08
FORMULA_NAME DLCflexbar-PT-8a-ReachabilityCardinality-2024-09
FORMULA_NAME DLCflexbar-PT-8a-ReachabilityCardinality-2024-10
FORMULA_NAME DLCflexbar-PT-8a-ReachabilityCardinality-2024-11
FORMULA_NAME DLCflexbar-PT-8a-ReachabilityCardinality-2024-12
FORMULA_NAME DLCflexbar-PT-8a-ReachabilityCardinality-2024-13
FORMULA_NAME DLCflexbar-PT-8a-ReachabilityCardinality-2024-14
FORMULA_NAME DLCflexbar-PT-8a-ReachabilityCardinality-2024-15

=== Now, execution of the tool begins

BK_START 1717042536526

FORMULA DLCflexbar-PT-8a-ReachabilityCardinality-2024-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-8a-ReachabilityCardinality-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-8a-ReachabilityCardinality-2024-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-8a-ReachabilityCardinality-2024-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-8a-ReachabilityCardinality-2024-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-8a-ReachabilityCardinality-2024-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-8a-ReachabilityCardinality-2024-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-8a-ReachabilityCardinality-2024-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-8a-ReachabilityCardinality-2024-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-8a-ReachabilityCardinality-2024-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-8a-ReachabilityCardinality-2024-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-8a-ReachabilityCardinality-2024-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-8a-ReachabilityCardinality-2024-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-8a-ReachabilityCardinality-2024-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-8a-ReachabilityCardinality-2024-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-8a-ReachabilityCardinality-2024-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[lola] FINAL RESULTS
[lola]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola] DLCflexbar-PT-8a-ReachabilityCardinality-2024-00: INITIAL true preprocessing
[lola] DLCflexbar-PT-8a-ReachabilityCardinality-2024-01: AG false state space
[lola] DLCflexbar-PT-8a-ReachabilityCardinality-2024-02: EF true state space
[lola] DLCflexbar-PT-8a-ReachabilityCardinality-2024-03: INITIAL false preprocessing
[lola] DLCflexbar-PT-8a-ReachabilityCardinality-2024-04: INITIAL true preprocessing
[lola] DLCflexbar-PT-8a-ReachabilityCardinality-2024-05: INITIAL true preprocessing
[lola] DLCflexbar-PT-8a-ReachabilityCardinality-2024-06: INITIAL false preprocessing
[lola] DLCflexbar-PT-8a-ReachabilityCardinality-2024-07: INITIAL true preprocessing
[lola] DLCflexbar-PT-8a-ReachabilityCardinality-2024-08: INITIAL false preprocessing
[lola] DLCflexbar-PT-8a-ReachabilityCardinality-2024-09: INITIAL true preprocessing
[lola] DLCflexbar-PT-8a-ReachabilityCardinality-2024-10: AG false state space
[lola] DLCflexbar-PT-8a-ReachabilityCardinality-2024-11: EF false skeleton: state space
[lola] DLCflexbar-PT-8a-ReachabilityCardinality-2024-12: INITIAL false preprocessing
[lola] DLCflexbar-PT-8a-ReachabilityCardinality-2024-13: AG false state space
[lola] DLCflexbar-PT-8a-ReachabilityCardinality-2024-14: AG false state space
[lola] DLCflexbar-PT-8a-ReachabilityCardinality-2024-15: INITIAL true preprocessing
[lola]
[lola] Time elapsed: 118 secs. Pages in use: 1

BK_STOP 1717042654805

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains place/transition net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading formula.
[lola][I] Using XML format (--xmlformula)
[lola][I] reading XML formula
[lola][I] reading formula from ReachabilityCardinality.xml
[lola][I] LAUNCH task # 50 (type SKEL/FNDP) for 3 DLCflexbar-PT-8a-ReachabilityCardinality-2024-01
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 51 (type SKEL/EQUN) for 3 DLCflexbar-PT-8a-ReachabilityCardinality-2024-01
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 52 (type SKEL/SRCH) for 3 DLCflexbar-PT-8a-ReachabilityCardinality-2024-01
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 52 (type SKEL/SRCH) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-01
[lola][I] result : true
[lola][I] markings : 5
[lola][I] fired transitions : 4
[lola][I] time used : 1
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 50 (type FNDP) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-01 (obsolete)
[lola][W] CANCELED task # 51 (type EQUN) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-01 (obsolete)
[lola][I] FINISHED task # 50 (type SKEL/FNDP) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-01
[lola][I] result : true
[lola][I] tried executions : 1
[lola][I] time used : 1
[lola][I] memory pages used : 0
[lola][I] FINISHED task # 51 (type SKEL/EQUN) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-01
[lola][I] result : false
[lola][I] Rule S: 0 transitions removed,0 places removed
[lola][I] LAUNCH task # 55 (type SKEL/FNDP) for 42 DLCflexbar-PT-8a-ReachabilityCardinality-2024-14
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 56 (type SKEL/EQUN) for 42 DLCflexbar-PT-8a-ReachabilityCardinality-2024-14
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 57 (type SKEL/SRCH) for 42 DLCflexbar-PT-8a-ReachabilityCardinality-2024-14
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 57 (type SKEL/SRCH) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-14
[lola][I] result : true
[lola][I] markings : 6
[lola][I] fired transitions : 5
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 55 (type FNDP) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-14 (obsolete)
[lola][W] CANCELED task # 56 (type EQUN) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-14 (obsolete)
[lola][I] FINISHED task # 55 (type SKEL/FNDP) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-14
[lola][I] result : true
[lola][I] tried executions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 0
[lola][I] FINISHED task # 56 (type SKEL/EQUN) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-14
[lola][I] result : false
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-00: INITIAL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-01: AG 0 0 0 0 3 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-02: EF 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-03: INITIAL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-04: INITIAL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-05: INITIAL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-06: INITIAL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-07: INITIAL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-08: INITIAL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-09: INITIAL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-10: AG 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-11: EF 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-12: INITIAL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-13: AG 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-14: AG 0 0 0 0 3 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-15: INITIAL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 85 secs. Pages in use: 1
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-00: INITIAL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-01: AG 0 0 0 0 3 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-02: EF 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-03: INITIAL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-04: INITIAL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-05: INITIAL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-06: INITIAL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-07: INITIAL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-08: INITIAL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-09: INITIAL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-10: AG 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-11: EF 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-12: INITIAL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-13: AG 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-14: AG 0 0 0 0 3 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-15: INITIAL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 90 secs. Pages in use: 1
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-00: INITIAL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-01: AG 0 0 0 0 3 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-02: EF 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-03: INITIAL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-04: INITIAL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-05: INITIAL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-06: INITIAL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-07: INITIAL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-08: INITIAL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-09: INITIAL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-10: AG 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-11: EF 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-12: INITIAL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-13: AG 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-14: AG 0 0 0 0 3 0 0 0
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-15: INITIAL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 95 secs. Pages in use: 1
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I] LAUNCH task # 60 (type SKEL/FNDP) for 39 DLCflexbar-PT-8a-ReachabilityCardinality-2024-13
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 61 (type SKEL/EQUN) for 39 DLCflexbar-PT-8a-ReachabilityCardinality-2024-13
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 62 (type SKEL/SRCH) for 39 DLCflexbar-PT-8a-ReachabilityCardinality-2024-13
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 60 (type SKEL/FNDP) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-13
[lola][I] result : true
[lola][I] tried executions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 0
[lola][W] CANCELED task # 61 (type EQUN) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-13 (obsolete)
[lola][W] CANCELED task # 62 (type SRCH) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-13 (obsolete)
[lola][I] FINISHED task # 61 (type SKEL/EQUN) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-13
[lola][I] result : false
[lola][I] LAUNCH task # 64 (type SKEL/FNDP) for 33 DLCflexbar-PT-8a-ReachabilityCardinality-2024-11
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 65 (type SKEL/EQUN) for 33 DLCflexbar-PT-8a-ReachabilityCardinality-2024-11
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 66 (type SKEL/SRCH) for 33 DLCflexbar-PT-8a-ReachabilityCardinality-2024-11
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 1 (type CNST) for 0 DLCflexbar-PT-8a-ReachabilityCardinality-2024-00
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] LAUNCH task # 22 (type CNST) for 21 DLCflexbar-PT-8a-ReachabilityCardinality-2024-07
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] LAUNCH task # 13 (type CNST) for 12 DLCflexbar-PT-8a-ReachabilityCardinality-2024-04
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] LAUNCH task # 10 (type CNST) for 9 DLCflexbar-PT-8a-ReachabilityCardinality-2024-03
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] LAUNCH task # 28 (type CNST) for 27 DLCflexbar-PT-8a-ReachabilityCardinality-2024-09
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] LAUNCH task # 37 (type CNST) for 36 DLCflexbar-PT-8a-ReachabilityCardinality-2024-12
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] LAUNCH task # 25 (type CNST) for 24 DLCflexbar-PT-8a-ReachabilityCardinality-2024-08
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] LAUNCH task # 46 (type CNST) for 45 DLCflexbar-PT-8a-ReachabilityCardinality-2024-15
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] FINISHED task # 1 (type CNST) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-00
[lola][I] result : true
[lola][I] LAUNCH task # 16 (type CNST) for 15 DLCflexbar-PT-8a-ReachabilityCardinality-2024-05
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] FINISHED task # 22 (type CNST) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-07
[lola][I] result : true
[lola][I] FINISHED task # 46 (type CNST) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-15
[lola][I] result : true
[lola][I] LAUNCH task # 19 (type CNST) for 18 DLCflexbar-PT-8a-ReachabilityCardinality-2024-06
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] FINISHED task # 25 (type CNST) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-08
[lola][I] result : false
[lola][I] FINISHED task # 19 (type CNST) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-06
[lola][I] result : false
[lola][I] FINISHED task # 37 (type CNST) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-12
[lola][I] result : false
[lola][I] FINISHED task # 10 (type CNST) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-03
[lola][I] result : false
[lola][I] FINISHED task # 28 (type CNST) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-09
[lola][I] result : true
[lola][I] FINISHED task # 13 (type CNST) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-04
[lola][I] result : true
[lola][I] FINISHED task # 16 (type CNST) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-05
[lola][I] result : true
[lola][I] LAUNCH task # 69 (type SKEL/FNDP) for 30 DLCflexbar-PT-8a-ReachabilityCardinality-2024-10
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 69 (type SKEL/FNDP) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-10
[lola][I] result : true
[lola][I] tried executions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 0
[lola][I] FINISHED task # 66 (type SKEL/SRCH) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-11
[lola][I] result : false
[lola][I] markings : 10
[lola][I] fired transitions : 183
[lola][I] time used : 1
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 64 (type FNDP) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-11 (obsolete)
[lola][W] CANCELED task # 65 (type EQUN) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-11 (obsolete)
[lola][I] FINISHED task # 64 (type SKEL/FNDP) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-11
[lola][I] result : unknown
[lola][I] tried executions : 196
[lola][I] time used : 1
[lola][I] memory pages used : 0
[lola][I] FINISHED task # 65 (type SKEL/EQUN) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-11
[lola][I] result : false
[lola][I] LAUNCH task # 73 (type SKEL/FNDP) for 6 DLCflexbar-PT-8a-ReachabilityCardinality-2024-02
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 74 (type SKEL/EQUN) for 6 DLCflexbar-PT-8a-ReachabilityCardinality-2024-02
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 75 (type SKEL/SRCH) for 6 DLCflexbar-PT-8a-ReachabilityCardinality-2024-02
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 73 (type SKEL/FNDP) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-02
[lola][I] result : true
[lola][I] tried executions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 0
[lola][W] CANCELED task # 74 (type EQUN) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-02 (obsolete)
[lola][W] CANCELED task # 75 (type SRCH) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-02 (obsolete)
[lola][I] planning for DLCflexbar-PT-8a-ReachabilityCardinality-2024-11 stopped (result already fixed).
[lola][I] FINISHED task # 74 (type SKEL/EQUN) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-02
[lola][I] result : false
[lola][I] LAUNCH task # 79 (type EXCL) for 3 DLCflexbar-PT-8a-ReachabilityCardinality-2024-01
[lola][I] time limit : 700 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 77 (type FNDP) for 3 DLCflexbar-PT-8a-ReachabilityCardinality-2024-01
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 78 (type EQUN) for 3 DLCflexbar-PT-8a-ReachabilityCardinality-2024-01
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 79 (type EXCL) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-01
[lola][I] result : true
[lola][I] markings : 2
[lola][I] fired transitions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 77 (type FNDP) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-01 (obsolete)
[lola][W] CANCELED task # 78 (type EQUN) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-01 (obsolete)
[lola][I] FINISHED task # 77 (type FNDP) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-01
[lola][I] result : true
[lola][I] tried executions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 0
[lola][I] FINISHED task # 78 (type EQUN) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-01
[lola][I] result : true
[lola][I] LAUNCH task # 83 (type EXCL) for 30 DLCflexbar-PT-8a-ReachabilityCardinality-2024-10
[lola][I] time limit : 875 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 81 (type FNDP) for 30 DLCflexbar-PT-8a-ReachabilityCardinality-2024-10
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 82 (type EQUN) for 30 DLCflexbar-PT-8a-ReachabilityCardinality-2024-10
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 83 (type EXCL) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-10
[lola][I] result : true
[lola][I] markings : 2
[lola][I] fired transitions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 81 (type FNDP) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-10 (obsolete)
[lola][W] CANCELED task # 82 (type EQUN) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-10 (obsolete)
[lola][I] FINISHED task # 81 (type FNDP) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-10
[lola][I] result : true
[lola][I] tried executions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 0
[lola][I] FINISHED task # 82 (type EQUN) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-10
[lola][I] result : true
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-00: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-01: AG false state space
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-03: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-04: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-05: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-06: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-07: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-08: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-09: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-10: AG false state space
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-11: EF false skeleton: state space
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-12: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-15: INITIAL true preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-02: EF 0 0 0 0 2 0 0 1
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-13: AG 0 0 0 0 2 0 0 1
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-14: AG 0 0 0 0 3 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 100 secs. Pages in use: 1
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I] LAUNCH task # 87 (type EXCL) for 39 DLCflexbar-PT-8a-ReachabilityCardinality-2024-13
[lola][I] time limit : 1166 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 85 (type FNDP) for 39 DLCflexbar-PT-8a-ReachabilityCardinality-2024-13
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 86 (type EQUN) for 39 DLCflexbar-PT-8a-ReachabilityCardinality-2024-13
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 87 (type EXCL) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-13
[lola][I] result : true
[lola][I] markings : 2
[lola][I] fired transitions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 85 (type FNDP) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-13 (obsolete)
[lola][W] CANCELED task # 86 (type EQUN) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-13 (obsolete)
[lola][I] FINISHED task # 85 (type FNDP) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-13
[lola][I] result : true
[lola][I] tried executions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 0
[lola][I] FINISHED task # 86 (type EQUN) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-13
[lola][I] result : true
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-00: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-01: AG false state space
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-03: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-04: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-05: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-06: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-07: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-08: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-09: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-10: AG false state space
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-11: EF false skeleton: state space
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-12: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-13: AG false state space
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-15: INITIAL true preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-02: EF 0 0 0 0 2 0 0 1
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-14: AG 0 0 0 0 3 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 105 secs. Pages in use: 1
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I] LAUNCH task # 90 (type EXCL) for 6 DLCflexbar-PT-8a-ReachabilityCardinality-2024-02
[lola][I] time limit : 1745 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 88 (type FNDP) for 6 DLCflexbar-PT-8a-ReachabilityCardinality-2024-02
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 89 (type EQUN) for 6 DLCflexbar-PT-8a-ReachabilityCardinality-2024-02
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 90 (type EXCL) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-02
[lola][I] result : true
[lola][I] markings : 4
[lola][I] fired transitions : 3
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 88 (type FNDP) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-02 (obsolete)
[lola][W] CANCELED task # 89 (type EQUN) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-02 (obsolete)
[lola][I] FINISHED task # 88 (type FNDP) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-02
[lola][I] result : true
[lola][I] tried executions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 0
[lola][I] FINISHED task # 89 (type EQUN) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-02
[lola][I] result : true
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-00: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-01: AG false state space
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-02: EF true state space
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-03: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-04: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-05: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-06: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-07: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-08: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-09: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-10: AG false state space
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-11: EF false skeleton: state space
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-12: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-13: AG false state space
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-15: INITIAL true preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-14: AG 0 0 0 0 3 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 110 secs. Pages in use: 1
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-00: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-01: AG false state space
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-02: EF true state space
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-03: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-04: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-05: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-06: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-07: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-08: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-09: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-10: AG false state space
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-11: EF false skeleton: state space
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-12: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-13: AG false state space
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-15: INITIAL true preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-8a-ReachabilityCardinality-2024-14: AG 0 0 0 0 3 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 115 secs. Pages in use: 1
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I] LAUNCH task # 94 (type EXCL) for 42 DLCflexbar-PT-8a-ReachabilityCardinality-2024-14
[lola][I] time limit : 3482 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 92 (type FNDP) for 42 DLCflexbar-PT-8a-ReachabilityCardinality-2024-14
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 93 (type EQUN) for 42 DLCflexbar-PT-8a-ReachabilityCardinality-2024-14
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 94 (type EXCL) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-14
[lola][I] result : true
[lola][I] markings : 6
[lola][I] fired transitions : 5
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 92 (type FNDP) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-14 (obsolete)
[lola][W] CANCELED task # 93 (type EQUN) for DLCflexbar-PT-8a-ReachabilityCardinality-2024-14 (obsolete)
[lola][I] Portfolio finished: no open formulas

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-8a"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is DLCflexbar-PT-8a, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r115-smll-171624276400102"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-8a.tgz
mv DLCflexbar-PT-8a execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;