About the Execution of LoLA for DLCflexbar-PT-8a
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
16209.312 | 739981.00 | 1089644.00 | 2463.60 | T??T?T???FF????? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r115-smll-171624276400097.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is DLCflexbar-PT-8a, examination is CTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r115-smll-171624276400097
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 9.2M
-rw-r--r-- 1 mcc users 7.9K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 86K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.5K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 48K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K Apr 22 14:37 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Apr 22 14:37 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Apr 22 14:37 LTLFireability.txt
-rw-r--r-- 1 mcc users 15K Apr 22 14:37 LTLFireability.xml
-rw-r--r-- 1 mcc users 15K Apr 14 12:51 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 157K Apr 14 12:51 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Apr 14 01:51 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 91K Apr 14 01:51 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 22 14:37 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Apr 22 14:37 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 3 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 8.7M May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCflexbar-PT-8a-CTLCardinality-2024-00
FORMULA_NAME DLCflexbar-PT-8a-CTLCardinality-2024-01
FORMULA_NAME DLCflexbar-PT-8a-CTLCardinality-2024-02
FORMULA_NAME DLCflexbar-PT-8a-CTLCardinality-2024-03
FORMULA_NAME DLCflexbar-PT-8a-CTLCardinality-2024-04
FORMULA_NAME DLCflexbar-PT-8a-CTLCardinality-2024-05
FORMULA_NAME DLCflexbar-PT-8a-CTLCardinality-2024-06
FORMULA_NAME DLCflexbar-PT-8a-CTLCardinality-2024-07
FORMULA_NAME DLCflexbar-PT-8a-CTLCardinality-2024-08
FORMULA_NAME DLCflexbar-PT-8a-CTLCardinality-2024-09
FORMULA_NAME DLCflexbar-PT-8a-CTLCardinality-2024-10
FORMULA_NAME DLCflexbar-PT-8a-CTLCardinality-2024-11
FORMULA_NAME DLCflexbar-PT-8a-CTLCardinality-2023-12
FORMULA_NAME DLCflexbar-PT-8a-CTLCardinality-2023-13
FORMULA_NAME DLCflexbar-PT-8a-CTLCardinality-2023-14
FORMULA_NAME DLCflexbar-PT-8a-CTLCardinality-2023-15
=== Now, execution of the tool begins
BK_START 1717041474432
FORMULA DLCflexbar-PT-8a-CTLCardinality-2024-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-8a-CTLCardinality-2024-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-8a-CTLCardinality-2024-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-8a-CTLCardinality-2024-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-8a-CTLCardinality-2024-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717042214413
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLCardinality.xml[0m
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 66 (type SKEL/FNDP) for 6 DLCflexbar-PT-8a-CTLCardinality-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 67 (type SKEL/EQUN) for 6 DLCflexbar-PT-8a-CTLCardinality-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 68 (type SKEL/SRCH) for 6 DLCflexbar-PT-8a-CTLCardinality-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 68 (type SKEL/SRCH) for DLCflexbar-PT-8a-CTLCardinality-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 4
[[35mlola[0m][I] fired transitions : 3
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 66 (type FNDP) for DLCflexbar-PT-8a-CTLCardinality-2024-02 (obsolete)
[[35mlola[0m][W] CANCELED task # 67 (type EQUN) for DLCflexbar-PT-8a-CTLCardinality-2024-02 (obsolete)
[[35mlola[0m][I] FINISHED task # 67 (type SKEL/EQUN) for DLCflexbar-PT-8a-CTLCardinality-2024-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 66 (type SKEL/FNDP) for DLCflexbar-PT-8a-CTLCardinality-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] LAUNCH task # 1 (type CNST) for 0 DLCflexbar-PT-8a-CTLCardinality-2024-00
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 1 (type CNST) for DLCflexbar-PT-8a-CTLCardinality-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 32 (type CNST) for 31 DLCflexbar-PT-8a-CTLCardinality-2024-05
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 32 (type CNST) for DLCflexbar-PT-8a-CTLCardinality-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 69 (type SKEL/SRCH) for 24 DLCflexbar-PT-8a-CTLCardinality-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 69 (type SKEL/SRCH) for DLCflexbar-PT-8a-CTLCardinality-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 44 (type CNST) for 43 DLCflexbar-PT-8a-CTLCardinality-2024-09
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 47 (type CNST) for 46 DLCflexbar-PT-8a-CTLCardinality-2024-10
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 44 (type CNST) for DLCflexbar-PT-8a-CTLCardinality-2024-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 47 (type CNST) for DLCflexbar-PT-8a-CTLCardinality-2024-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 22 (type CNST) for 21 DLCflexbar-PT-8a-CTLCardinality-2024-03
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 22 (type CNST) for DLCflexbar-PT-8a-CTLCardinality-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 70 (type SKEL/SRCH) for 58 DLCflexbar-PT-8a-CTLCardinality-2023-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 70 (type SKEL/SRCH) for DLCflexbar-PT-8a-CTLCardinality-2023-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ 0 0 0 0 6 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ 0 0 0 0 6 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ 0 0 0 0 6 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ 0 0 0 0 6 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ 0 0 0 0 6 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 96 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 74 (type EXCL) for 6 DLCflexbar-PT-8a-CTLCardinality-2024-02
[[35mlola[0m][I] time limit : 233 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 72 (type FNDP) for 6 DLCflexbar-PT-8a-CTLCardinality-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 73 (type EQUN) for 6 DLCflexbar-PT-8a-CTLCardinality-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 74 (type EXCL) for DLCflexbar-PT-8a-CTLCardinality-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 72 (type FNDP) for DLCflexbar-PT-8a-CTLCardinality-2024-02 (obsolete)
[[35mlola[0m][W] CANCELED task # 73 (type EQUN) for DLCflexbar-PT-8a-CTLCardinality-2024-02 (obsolete)
[[35mlola[0m][I] FINISHED task # 73 (type EQUN) for DLCflexbar-PT-8a-CTLCardinality-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 72 (type FNDP) for DLCflexbar-PT-8a-CTLCardinality-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 101 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 106 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 111 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 116 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 121 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 126 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 131 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[*** LOG ERROR #0001 ***] [2024-05-30 04:00:05] [status_logger] string pointer is null
[*** LOG ERROR #0002 ***] [2024-05-30 04:00:07] [status_logger] string pointer is null
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 136 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 141 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 146 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 151 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 156 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[*** LOG ERROR #0003 ***] [2024-05-30 04:00:32] [status_logger] string pointer is null
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 161 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 166 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 171 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 176 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 181 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 186 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 191 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 1 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 196 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 DLCflexbar-PT-8a-CTLCardinality-2024-01
[[35mlola[0m][I] time limit : 309 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 1 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 5/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 106 m, 21 m/sec, 4530 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 201 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 1 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 10/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 455 m, 69 m/sec, 25359 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 206 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 1 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 1 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 15/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 876 m, 84 m/sec, 50668 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 211 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 20/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 1652 m, 155 m/sec, 98211 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 216 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 25/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 2467 m, 163 m/sec, 147457 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 221 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 30/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 3284 m, 163 m/sec, 195981 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 226 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 35/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 4081 m, 159 m/sec, 243027 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 231 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 40/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 4893 m, 162 m/sec, 290922 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 236 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 45/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 5719 m, 165 m/sec, 339618 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 241 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 50/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 6556 m, 167 m/sec, 389203 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 246 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 55/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 7394 m, 167 m/sec, 437813 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 251 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 60/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 8236 m, 168 m/sec, 486854 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 256 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 65/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 9084 m, 169 m/sec, 535614 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 261 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 70/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 9879 m, 159 m/sec, 581005 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 266 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 75/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 10322 m, 88 m/sec, 606276 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 271 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 80/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 11665 m, 268 m/sec, 683330 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 276 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 85/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 14122 m, 491 m/sec, 823264 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 281 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 90/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 16659 m, 507 m/sec, 958004 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 286 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 95/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 19253 m, 518 m/sec, 1085249 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 291 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 100/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 22174 m, 584 m/sec, 1223071 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 296 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 105/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 25412 m, 647 m/sec, 1373739 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 301 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 110/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 28846 m, 686 m/sec, 1524582 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 306 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 115/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 32512 m, 733 m/sec, 1677447 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 311 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 120/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 36398 m, 777 m/sec, 1837849 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 316 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 125/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 40445 m, 809 m/sec, 2006109 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 321 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 130/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 44545 m, 820 m/sec, 2176240 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 326 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 135/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 48717 m, 834 m/sec, 2349765 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 331 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 140/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 52962 m, 849 m/sec, 2525742 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 336 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 145/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 57223 m, 852 m/sec, 2700841 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 341 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 150/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 61483 m, 852 m/sec, 2876933 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 346 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 155/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 65790 m, 861 m/sec, 3055259 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 351 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 160/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 70070 m, 856 m/sec, 3233733 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 356 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 165/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 74332 m, 852 m/sec, 3409712 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 361 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 170/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 78634 m, 860 m/sec, 3587015 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 366 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 175/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 82953 m, 863 m/sec, 3766722 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 371 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 180/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 87280 m, 865 m/sec, 3948302 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 376 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 185/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 91568 m, 857 m/sec, 4126639 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 381 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 190/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 95898 m, 866 m/sec, 4306875 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 386 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 195/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 100249 m, 870 m/sec, 4486984 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 391 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 200/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 104576 m, 865 m/sec, 4670262 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 396 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 205/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 108925 m, 869 m/sec, 4851675 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 401 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 210/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 113311 m, 877 m/sec, 5034446 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 406 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 215/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 117727 m, 883 m/sec, 5217200 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 411 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 220/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 122121 m, 878 m/sec, 5401076 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 416 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 225/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 126474 m, 870 m/sec, 5585706 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 421 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 230/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 130817 m, 868 m/sec, 5766780 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 426 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 235/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 135193 m, 875 m/sec, 5948223 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 431 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 240/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 139694 m, 900 m/sec, 6133426 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 436 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 245/309 1/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 144149 m, 891 m/sec, 6319868 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 441 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 250/309 2/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 148252 m, 820 m/sec, 6491348 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 446 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 255/309 2/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 152553 m, 860 m/sec, 6671269 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 451 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 260/309 2/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 156845 m, 858 m/sec, 6847385 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 456 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 265/309 2/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 161113 m, 853 m/sec, 7027291 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 461 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 270/309 2/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 164997 m, 776 m/sec, 7188813 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 466 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 275/309 2/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 167842 m, 569 m/sec, 7309096 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 471 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 280/309 2/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 170709 m, 573 m/sec, 7427060 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 476 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 285/309 2/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 174085 m, 675 m/sec, 7567800 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 481 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 290/309 2/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 178312 m, 845 m/sec, 7743447 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 486 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 295/309 2/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 182604 m, 858 m/sec, 7920861 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 491 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 300/309 2/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 186614 m, 802 m/sec, 8086331 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 496 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 305/309 2/2000 DLCflexbar-PT-8a-CTLCardinality-2024-01 190118 m, 700 m/sec, 8231466 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 501 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 4 (type EXCL) for DLCflexbar-PT-8a-CTLCardinality-2024-01 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 506 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 62 (type EXCL) for 61 DLCflexbar-PT-8a-CTLCardinality-2023-15
[[35mlola[0m][I] time limit : 309 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 DLCflexbar-PT-8a-CTLCardinality-2024-01
[[35mlola[0m][I] time limit : 3094 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 62 (type EXCL) for DLCflexbar-PT-8a-CTLCardinality-2023-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 4
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 5/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 493 m, -37925 m/sec, 27595 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 511 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 10/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 1342 m, 169 m/sec, 79661 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 516 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 15/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 2198 m, 171 m/sec, 131073 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 521 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 20/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 3046 m, 169 m/sec, 181674 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 526 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 25/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 3874 m, 165 m/sec, 230796 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 531 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 30/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 4720 m, 169 m/sec, 280890 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 536 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 35/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 5587 m, 173 m/sec, 331732 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 541 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 40/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 6500 m, 182 m/sec, 385669 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 546 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 45/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 7431 m, 186 m/sec, 440150 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 551 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 50/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 8368 m, 187 m/sec, 494250 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 556 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 55/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 9311 m, 188 m/sec, 548554 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 561 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 60/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 10043 m, 146 m/sec, 590408 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 566 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 65/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 10536 m, 98 m/sec, 618717 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 571 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 70/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 12979 m, 488 m/sec, 759943 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 576 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 75/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 15646 m, 533 m/sec, 905018 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 581 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 80/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 18452 m, 561 m/sec, 1046931 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 586 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 85/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 21407 m, 591 m/sec, 1187218 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 591 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 90/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 24545 m, 627 m/sec, 1333217 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 596 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 95/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 27860 m, 663 m/sec, 1482225 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 601 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 100/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 31354 m, 698 m/sec, 1629915 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 606 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 105/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 35054 m, 740 m/sec, 1782444 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 611 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 110/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 38948 m, 778 m/sec, 1943582 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 616 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 115/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 42908 m, 792 m/sec, 2107019 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 621 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 120/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 46914 m, 801 m/sec, 2274179 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 626 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 125/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 50902 m, 797 m/sec, 2440436 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 631 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 130/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 54974 m, 814 m/sec, 2608124 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 636 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 135/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 59058 m, 816 m/sec, 2776743 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 641 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 140/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 63278 m, 844 m/sec, 2950993 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 646 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 145/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 67533 m, 851 m/sec, 3127623 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 651 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 150/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 71671 m, 827 m/sec, 3300152 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 656 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 155/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 75879 m, 841 m/sec, 3473683 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 661 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 160/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 80130 m, 850 m/sec, 3649786 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 666 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 165/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 84431 m, 860 m/sec, 3827635 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 671 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 170/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 88701 m, 854 m/sec, 4007571 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 676 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 175/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 92947 m, 849 m/sec, 4184013 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 681 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 180/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 97274 m, 865 m/sec, 4362950 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 686 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 185/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 101581 m, 861 m/sec, 4543593 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 691 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 190/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 105911 m, 866 m/sec, 4725818 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 696 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 195/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 110252 m, 868 m/sec, 4906919 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 701 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 200/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 114616 m, 872 m/sec, 5088639 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 706 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 205/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 118969 m, 870 m/sec, 5269608 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 711 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 210/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 123001 m, 806 m/sec, 5439193 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 716 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 215/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 126897 m, 779 m/sec, 5603711 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 721 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-02: CONJ false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-8a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-8a-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-8a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 220/309 1/5 DLCflexbar-PT-8a-CTLCardinality-2024-01 130539 m, 728 m/sec, 5755519 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 726 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 403 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-8a"
export BK_EXAMINATION="CTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is DLCflexbar-PT-8a, examination is CTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r115-smll-171624276400097"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-8a.tgz
mv DLCflexbar-PT-8a execution
cd execution
if [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "UpperBounds" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] || [ "CTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;