About the Execution of LoLA for DLCflexbar-PT-7b
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 15531.563 | 1830080.00 | 5602600.00 | 1906.00 | ?????F????????F? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r115-smll-171624276300090.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is DLCflexbar-PT-7b, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r115-smll-171624276300090
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 15M
-rw-r--r-- 1 mcc users 6.1K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 61K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.3K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 48K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.9K May 19 07:08 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K May 19 15:43 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K May 19 07:16 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K May 19 18:10 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Apr 12 13:04 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 107K Apr 12 13:04 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 13K Apr 12 13:03 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 110K Apr 12 13:03 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 22 14:37 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Apr 22 14:37 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 3 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 14M May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCflexbar-PT-7b-CTLFireability-2024-00
FORMULA_NAME DLCflexbar-PT-7b-CTLFireability-2024-01
FORMULA_NAME DLCflexbar-PT-7b-CTLFireability-2024-02
FORMULA_NAME DLCflexbar-PT-7b-CTLFireability-2024-03
FORMULA_NAME DLCflexbar-PT-7b-CTLFireability-2024-04
FORMULA_NAME DLCflexbar-PT-7b-CTLFireability-2024-05
FORMULA_NAME DLCflexbar-PT-7b-CTLFireability-2024-06
FORMULA_NAME DLCflexbar-PT-7b-CTLFireability-2024-07
FORMULA_NAME DLCflexbar-PT-7b-CTLFireability-2024-08
FORMULA_NAME DLCflexbar-PT-7b-CTLFireability-2024-09
FORMULA_NAME DLCflexbar-PT-7b-CTLFireability-2024-10
FORMULA_NAME DLCflexbar-PT-7b-CTLFireability-2024-11
FORMULA_NAME DLCflexbar-PT-7b-CTLFireability-2023-12
FORMULA_NAME DLCflexbar-PT-7b-CTLFireability-2023-13
FORMULA_NAME DLCflexbar-PT-7b-CTLFireability-2023-14
FORMULA_NAME DLCflexbar-PT-7b-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717034946121
FORMULA DLCflexbar-PT-7b-CTLFireability-2024-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-7b-CTLFireability-2023-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717036776201
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
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[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2023-15: EFAG 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
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[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-05: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
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[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
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[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2023-14: AG 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2023-15: EFAG 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-05: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2023-14: AG 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2023-15: EFAG 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][I] time limit : 106 sec
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[[35mlola[0m][I] LAUNCH task # 53 (type EQUN) for 15 DLCflexbar-PT-7b-CTLFireability-2024-05
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[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 58 (type EQUN) for 45 DLCflexbar-PT-7b-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 60 (type EQUN) for 45 DLCflexbar-PT-7b-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
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[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-05: F 0 0 2 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2023-13: CTL 1 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2023-14: AG 1 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2023-15: EFAG 0 1 2 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 EG EXCL 0/112 0/2000 DLCflexbar-PT-7b-CTLFireability-2024-05 --
[[35mlola[0m][.] 53 EF STEQ 0/958 0/5 DLCflexbar-PT-7b-CTLFireability-2024-05 sara not yet started (preprocessing).
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[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2053
[[35mlola[0m][I] fired transitions : 2053
[[35mlola[0m][I] time used : 5
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 53 (type EQUN) for DLCflexbar-PT-7b-CTLFireability-2024-05 (obsolete)
[[35mlola[0m][I] LAUNCH task # 63 (type EXCL) for 42 DLCflexbar-PT-7b-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 112 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 61 (type FNDP) for 42 DLCflexbar-PT-7b-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7b-CTLFireability-2024-05: F false state space / EG[0m
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[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2023-14: AG 0 1 2 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2023-15: EFAG 0 1 2 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 58 EF STEQ 5/1912 0/5 DLCflexbar-PT-7b-CTLFireability-2023-15 sara not yet started (preprocessing).
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[[35mlola[0m][.] 61 EF FNDP 0/956 0/5 DLCflexbar-PT-7b-CTLFireability-2023-14 --
[[35mlola[0m][.] 63 EF EXCL 0/112 1/2000 DLCflexbar-PT-7b-CTLFireability-2023-14 --
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[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 9
[[35mlola[0m][I] fired transitions : 8
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 61 (type FNDP) for DLCflexbar-PT-7b-CTLFireability-2023-14 (obsolete)
[[35mlola[0m][I] LAUNCH task # 54 (type EXCL) for 45 DLCflexbar-PT-7b-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 127 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 61 (type FNDP) for DLCflexbar-PT-7b-CTLFireability-2023-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 2
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7b-CTLFireability-2024-05: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7b-CTLFireability-2023-14: AG false state space[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2023-15: EFAG 0 0 3 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 AGEF EXCL 4/127 1/2000 DLCflexbar-PT-7b-CTLFireability-2023-15 1698 m, 339 m/sec, 39452 t fired, .
[[35mlola[0m][.] 58 EF STEQ 10/1917 0/5 DLCflexbar-PT-7b-CTLFireability-2023-15 sara not yet started (preprocessing).
[[35mlola[0m][.] 60 EF STEQ 10/1917 0/5 DLCflexbar-PT-7b-CTLFireability-2023-15 sara not yet started (preprocessing).
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[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7b-CTLFireability-2023-14: AG false state space[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2023-15: EFAG 0 0 3 0 0 0 0 0
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[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 AGEF EXCL 9/127 1/2000 DLCflexbar-PT-7b-CTLFireability-2023-15 3855 m, 431 m/sec, 91497 t fired, .
[[35mlola[0m][.] 58 EF STEQ 15/1917 0/5 DLCflexbar-PT-7b-CTLFireability-2023-15 sara not yet started (preprocessing).
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[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7b-CTLFireability-2023-14: AG false state space[0m
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[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2023-15: EFAG 0 0 3 0 0 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 54 AGEF EXCL 14/127 1/2000 DLCflexbar-PT-7b-CTLFireability-2023-15 6016 m, 432 m/sec, 143613 t fired, .
[[35mlola[0m][.] 58 EF STEQ 20/1917 0/5 DLCflexbar-PT-7b-CTLFireability-2023-15 sara not yet started (preprocessing).
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[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7b-CTLFireability-2023-14: AG false state space[0m
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[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2023-15: EFAG 0 0 3 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 AGEF EXCL 19/127 1/2000 DLCflexbar-PT-7b-CTLFireability-2023-15 8157 m, 428 m/sec, 195437 t fired, .
[[35mlola[0m][.] 58 EF STEQ 25/1917 0/5 DLCflexbar-PT-7b-CTLFireability-2023-15 sara not yet started (preprocessing).
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[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7b-CTLFireability-2023-14: AG false state space[0m
[[35mlola[0m][.]
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[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2023-15: EFAG 0 0 3 0 0 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 54 AGEF EXCL 24/127 1/2000 DLCflexbar-PT-7b-CTLFireability-2023-15 10352 m, 439 m/sec, 248648 t fired, .
[[35mlola[0m][.] 58 EF STEQ 30/1917 0/5 DLCflexbar-PT-7b-CTLFireability-2023-15 sara not yet started (preprocessing).
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[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
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[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
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[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 0 0
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[[35mlola[0m][.] 54 AGEF EXCL 29/127 1/2000 DLCflexbar-PT-7b-CTLFireability-2023-15 12454 m, 420 m/sec, 299731 t fired, .
[[35mlola[0m][.] 58 EF STEQ 35/1917 0/5 DLCflexbar-PT-7b-CTLFireability-2023-15 sara not yet started (preprocessing).
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[[35mlola[0m][.] 54 AGEF EXCL 34/127 1/2000 DLCflexbar-PT-7b-CTLFireability-2023-15 14958 m, 500 m/sec, 360063 t fired, .
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[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7b-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
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[[35mlola[0m][.] 54 AGEF EXCL 39/127 1/2000 DLCflexbar-PT-7b-CTLFireability-2023-15 17405 m, 489 m/sec, 418753 t fired, .
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[[35mlola[0m][.] 54 AGEF EXCL 104/136 5/2000 DLCflexbar-PT-7b-CTLFireability-2023-15 121617 m, 2029 m/sec, 2878331 t fired, .
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[[35mlola[0m][.] 54 AGEF EXCL 109/136 5/2000 DLCflexbar-PT-7b-CTLFireability-2023-15 131709 m, 2018 m/sec, 3109761 t fired, .
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[[35mlola[0m][.] 54 AGEF EXCL 114/136 6/2000 DLCflexbar-PT-7b-CTLFireability-2023-15 141736 m, 2005 m/sec, 3341314 t fired, .
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/home/mcc/BenchKit/BenchKit_head.sh: line 23: 409 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-7b"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is DLCflexbar-PT-7b, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r115-smll-171624276300090"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-7b.tgz
mv DLCflexbar-PT-7b execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;