About the Execution of LoLA for DLCflexbar-PT-7a
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 6378.695 | 62922.00 | 71153.00 | 334.20 | FFFTFTFTTTTTTFFT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r115-smll-171624276300086.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is DLCflexbar-PT-7a, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r115-smll-171624276300086
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 6.7M
-rw-r--r-- 1 mcc users 8.0K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 89K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.1K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 57K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K May 19 07:08 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K May 19 15:42 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Apr 22 14:37 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Apr 22 14:37 LTLFireability.xml
-rw-r--r-- 1 mcc users 15K Apr 13 13:49 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 158K Apr 13 13:49 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.9K Apr 13 04:24 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 74K Apr 13 04:24 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 22 14:37 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Apr 22 14:37 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 3 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 6.2M May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCflexbar-PT-7a-ReachabilityCardinality-2024-00
FORMULA_NAME DLCflexbar-PT-7a-ReachabilityCardinality-2024-01
FORMULA_NAME DLCflexbar-PT-7a-ReachabilityCardinality-2024-02
FORMULA_NAME DLCflexbar-PT-7a-ReachabilityCardinality-2024-03
FORMULA_NAME DLCflexbar-PT-7a-ReachabilityCardinality-2024-04
FORMULA_NAME DLCflexbar-PT-7a-ReachabilityCardinality-2024-05
FORMULA_NAME DLCflexbar-PT-7a-ReachabilityCardinality-2024-06
FORMULA_NAME DLCflexbar-PT-7a-ReachabilityCardinality-2024-07
FORMULA_NAME DLCflexbar-PT-7a-ReachabilityCardinality-2024-08
FORMULA_NAME DLCflexbar-PT-7a-ReachabilityCardinality-2024-09
FORMULA_NAME DLCflexbar-PT-7a-ReachabilityCardinality-2024-10
FORMULA_NAME DLCflexbar-PT-7a-ReachabilityCardinality-2024-11
FORMULA_NAME DLCflexbar-PT-7a-ReachabilityCardinality-2024-12
FORMULA_NAME DLCflexbar-PT-7a-ReachabilityCardinality-2024-13
FORMULA_NAME DLCflexbar-PT-7a-ReachabilityCardinality-2024-14
FORMULA_NAME DLCflexbar-PT-7a-ReachabilityCardinality-2024-15
=== Now, execution of the tool begins
BK_START 1717034791330
FORMULA DLCflexbar-PT-7a-ReachabilityCardinality-2024-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-7a-ReachabilityCardinality-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-7a-ReachabilityCardinality-2024-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-7a-ReachabilityCardinality-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-7a-ReachabilityCardinality-2024-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-7a-ReachabilityCardinality-2024-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-7a-ReachabilityCardinality-2024-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-7a-ReachabilityCardinality-2024-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-7a-ReachabilityCardinality-2024-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-7a-ReachabilityCardinality-2024-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-7a-ReachabilityCardinality-2024-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-7a-ReachabilityCardinality-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-7a-ReachabilityCardinality-2024-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-7a-ReachabilityCardinality-2024-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-7a-ReachabilityCardinality-2024-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-7a-ReachabilityCardinality-2024-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[31mDLCflexbar-PT-7a-ReachabilityCardinality-2024-00: AG false state space[0m
[[35mlola[0m] [1m[31mDLCflexbar-PT-7a-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m] [1m[31mDLCflexbar-PT-7a-ReachabilityCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m] [1m[32mDLCflexbar-PT-7a-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m] [1m[31mDLCflexbar-PT-7a-ReachabilityCardinality-2024-04: EF false skeleton: state space[0m
[[35mlola[0m] [1m[32mDLCflexbar-PT-7a-ReachabilityCardinality-2024-05: AG true skeleton: state space[0m
[[35mlola[0m] [1m[31mDLCflexbar-PT-7a-ReachabilityCardinality-2024-06: AG false findpath[0m
[[35mlola[0m] [1m[32mDLCflexbar-PT-7a-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m] [1m[32mDLCflexbar-PT-7a-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m] [1m[32mDLCflexbar-PT-7a-ReachabilityCardinality-2024-09: INITIAL true preprocessing[0m
[[35mlola[0m] [1m[32mDLCflexbar-PT-7a-ReachabilityCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m] [1m[32mDLCflexbar-PT-7a-ReachabilityCardinality-2024-11: EF true state space[0m
[[35mlola[0m] [1m[32mDLCflexbar-PT-7a-ReachabilityCardinality-2024-12: INITIAL true preprocessing[0m
[[35mlola[0m] [1m[31mDLCflexbar-PT-7a-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m] [1m[31mDLCflexbar-PT-7a-ReachabilityCardinality-2024-14: INITIAL false preprocessing[0m
[[35mlola[0m] [1m[32mDLCflexbar-PT-7a-ReachabilityCardinality-2024-15: INITIAL true preprocessing[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 62 secs. Pages in use: 2
BK_STOP 1717034854252
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mReachabilityCardinality.xml[0m
[[35mlola[0m][I] LAUNCH task # 50 (type SKEL/FNDP) for 18 DLCflexbar-PT-7a-ReachabilityCardinality-2024-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 51 (type SKEL/EQUN) for 18 DLCflexbar-PT-7a-ReachabilityCardinality-2024-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 52 (type SKEL/SRCH) for 18 DLCflexbar-PT-7a-ReachabilityCardinality-2024-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 54 (type SKEL/FNDP) for 12 DLCflexbar-PT-7a-ReachabilityCardinality-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 50 (type SKEL/FNDP) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 51 (type EQUN) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-06 (obsolete)
[[35mlola[0m][W] CANCELED task # 52 (type SRCH) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-06 (obsolete)
[[35mlola[0m][I] LAUNCH task # 55 (type SKEL/EQUN) for 12 DLCflexbar-PT-7a-ReachabilityCardinality-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 56 (type SKEL/SRCH) for 12 DLCflexbar-PT-7a-ReachabilityCardinality-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 56 (type SKEL/SRCH) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 54 (type FNDP) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-04 (obsolete)
[[35mlola[0m][W] CANCELED task # 55 (type EQUN) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-04 (obsolete)
[[35mlola[0m][I] FINISHED task # 54 (type SKEL/FNDP) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-04
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] tried executions : 2192
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] FINISHED task # 52 (type SKEL/SRCH) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 5
[[35mlola[0m][I] fired transitions : 4
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] FINISHED task # 55 (type SKEL/EQUN) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 51 (type SKEL/EQUN) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 59 (type SKEL/FNDP) for 0 DLCflexbar-PT-7a-ReachabilityCardinality-2024-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 60 (type SKEL/EQUN) for 0 DLCflexbar-PT-7a-ReachabilityCardinality-2024-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 61 (type SKEL/SRCH) for 0 DLCflexbar-PT-7a-ReachabilityCardinality-2024-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 61 (type SKEL/SRCH) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 4
[[35mlola[0m][I] fired transitions : 3
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 59 (type FNDP) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-00 (obsolete)
[[35mlola[0m][W] CANCELED task # 60 (type EQUN) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-00 (obsolete)
[[35mlola[0m][I] FINISHED task # 60 (type SKEL/EQUN) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 59 (type SKEL/FNDP) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-ReachabilityCardinality-2024-04: EF false skeleton: state space[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-ReachabilityCardinality-2024-00: AG 0 0 0 0 3 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-ReachabilityCardinality-2024-01: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-ReachabilityCardinality-2024-02: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-ReachabilityCardinality-2024-03: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-ReachabilityCardinality-2024-05: AG 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-ReachabilityCardinality-2024-06: AG 0 0 0 0 3 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-ReachabilityCardinality-2024-07: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-ReachabilityCardinality-2024-08: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-ReachabilityCardinality-2024-09: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-ReachabilityCardinality-2024-10: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-ReachabilityCardinality-2024-11: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-ReachabilityCardinality-2024-12: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-ReachabilityCardinality-2024-13: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-ReachabilityCardinality-2024-14: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-ReachabilityCardinality-2024-15: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 53 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 25 (type CNST) for 24 DLCflexbar-PT-7a-ReachabilityCardinality-2024-08
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 37 (type CNST) for 36 DLCflexbar-PT-7a-ReachabilityCardinality-2024-12
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 4 (type CNST) for 3 DLCflexbar-PT-7a-ReachabilityCardinality-2024-01
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 22 (type CNST) for 21 DLCflexbar-PT-7a-ReachabilityCardinality-2024-07
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 7 (type CNST) for 6 DLCflexbar-PT-7a-ReachabilityCardinality-2024-02
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 40 (type CNST) for 39 DLCflexbar-PT-7a-ReachabilityCardinality-2024-13
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 25 (type CNST) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 37 (type CNST) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 22 (type CNST) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 63 (type SKEL/FNDP) for 33 DLCflexbar-PT-7a-ReachabilityCardinality-2024-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 7 (type CNST) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 4 (type CNST) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 64 (type SKEL/EQUN) for 33 DLCflexbar-PT-7a-ReachabilityCardinality-2024-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 65 (type SKEL/SRCH) for 33 DLCflexbar-PT-7a-ReachabilityCardinality-2024-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 40 (type CNST) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 46 (type CNST) for 45 DLCflexbar-PT-7a-ReachabilityCardinality-2024-15
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 46 (type CNST) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 68 (type SKEL/FNDP) for 15 DLCflexbar-PT-7a-ReachabilityCardinality-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 63 (type SKEL/FNDP) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 64 (type EQUN) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-11 (obsolete)
[[35mlola[0m][W] CANCELED task # 65 (type SRCH) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-11 (obsolete)
[[35mlola[0m][I] LAUNCH task # 69 (type SKEL/EQUN) for 15 DLCflexbar-PT-7a-ReachabilityCardinality-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 70 (type SKEL/SRCH) for 15 DLCflexbar-PT-7a-ReachabilityCardinality-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 10 (type CNST) for 9 DLCflexbar-PT-7a-ReachabilityCardinality-2024-03
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 10 (type CNST) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 28 (type CNST) for 27 DLCflexbar-PT-7a-ReachabilityCardinality-2024-09
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 64 (type SKEL/EQUN) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 28 (type CNST) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 70 (type SKEL/SRCH) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-05
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 7
[[35mlola[0m][I] fired transitions : 31
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 68 (type FNDP) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-05 (obsolete)
[[35mlola[0m][W] CANCELED task # 69 (type EQUN) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-05 (obsolete)
[[35mlola[0m][I] FINISHED task # 68 (type SKEL/FNDP) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-05
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] tried executions : 510
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] LAUNCH task # 31 (type CNST) for 30 DLCflexbar-PT-7a-ReachabilityCardinality-2024-10
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 31 (type CNST) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 69 (type SKEL/EQUN) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-05
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 43 (type CNST) for 42 DLCflexbar-PT-7a-ReachabilityCardinality-2024-14
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 43 (type CNST) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] planning for DLCflexbar-PT-7a-ReachabilityCardinality-2024-04 stopped (result already fixed).
[[35mlola[0m][I] planning for DLCflexbar-PT-7a-ReachabilityCardinality-2024-05 stopped (result already fixed).
[[35mlola[0m][I] LAUNCH task # 73 (type EXCL) for 33 DLCflexbar-PT-7a-ReachabilityCardinality-2024-11
[[35mlola[0m][I] time limit : 1181 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 71 (type FNDP) for 33 DLCflexbar-PT-7a-ReachabilityCardinality-2024-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 72 (type EQUN) for 33 DLCflexbar-PT-7a-ReachabilityCardinality-2024-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 73 (type EXCL) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 71 (type FNDP) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-11 (obsolete)
[[35mlola[0m][W] CANCELED task # 72 (type EQUN) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-11 (obsolete)
[[35mlola[0m][I] FINISHED task # 71 (type FNDP) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] FINISHED task # 72 (type EQUN) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-ReachabilityCardinality-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-ReachabilityCardinality-2024-04: EF false skeleton: state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-ReachabilityCardinality-2024-05: AG true skeleton: state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-ReachabilityCardinality-2024-09: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-ReachabilityCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-ReachabilityCardinality-2024-11: EF true state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-ReachabilityCardinality-2024-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-ReachabilityCardinality-2024-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-ReachabilityCardinality-2024-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-ReachabilityCardinality-2024-00: AG 0 0 0 0 3 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-ReachabilityCardinality-2024-06: AG 0 0 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 58 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 77 (type EXCL) for 0 DLCflexbar-PT-7a-ReachabilityCardinality-2024-00
[[35mlola[0m][I] time limit : 1769 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 75 (type FNDP) for 0 DLCflexbar-PT-7a-ReachabilityCardinality-2024-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 76 (type EQUN) for 0 DLCflexbar-PT-7a-ReachabilityCardinality-2024-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 77 (type EXCL) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 4
[[35mlola[0m][I] fired transitions : 3
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 75 (type FNDP) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-00 (obsolete)
[[35mlola[0m][W] CANCELED task # 76 (type EQUN) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-00 (obsolete)
[[35mlola[0m][I] FINISHED task # 75 (type FNDP) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] FINISHED task # 76 (type EQUN) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 81 (type EXCL) for 18 DLCflexbar-PT-7a-ReachabilityCardinality-2024-06
[[35mlola[0m][I] time limit : 3538 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 79 (type FNDP) for 18 DLCflexbar-PT-7a-ReachabilityCardinality-2024-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 80 (type EQUN) for 18 DLCflexbar-PT-7a-ReachabilityCardinality-2024-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 79 (type FNDP) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 80 (type EQUN) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-06 (obsolete)
[[35mlola[0m][W] CANCELED task # 81 (type EXCL) for DLCflexbar-PT-7a-ReachabilityCardinality-2024-06 (obsolete)
[[35mlola[0m][I] Portfolio finished: no open formulas
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-7a"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is DLCflexbar-PT-7a, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r115-smll-171624276300086"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-7a.tgz
mv DLCflexbar-PT-7a execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;