About the Execution of LoLA for DLCflexbar-PT-7a
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16194.052 | 483835.00 | 627616.00 | 1818.00 | T?F??F?????F???? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r115-smll-171624276300084.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is DLCflexbar-PT-7a, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r115-smll-171624276300084
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 6.7M
-rw-r--r-- 1 mcc users 8.0K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 89K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.1K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 57K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K May 19 07:08 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K May 19 15:42 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Apr 22 14:37 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Apr 22 14:37 LTLFireability.xml
-rw-r--r-- 1 mcc users 15K Apr 13 13:49 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 158K Apr 13 13:49 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.9K Apr 13 04:24 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 74K Apr 13 04:24 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 22 14:37 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Apr 22 14:37 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 3 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 6.2M May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCflexbar-PT-7a-LTLFireability-00
FORMULA_NAME DLCflexbar-PT-7a-LTLFireability-01
FORMULA_NAME DLCflexbar-PT-7a-LTLFireability-02
FORMULA_NAME DLCflexbar-PT-7a-LTLFireability-03
FORMULA_NAME DLCflexbar-PT-7a-LTLFireability-04
FORMULA_NAME DLCflexbar-PT-7a-LTLFireability-05
FORMULA_NAME DLCflexbar-PT-7a-LTLFireability-06
FORMULA_NAME DLCflexbar-PT-7a-LTLFireability-07
FORMULA_NAME DLCflexbar-PT-7a-LTLFireability-08
FORMULA_NAME DLCflexbar-PT-7a-LTLFireability-09
FORMULA_NAME DLCflexbar-PT-7a-LTLFireability-10
FORMULA_NAME DLCflexbar-PT-7a-LTLFireability-11
FORMULA_NAME DLCflexbar-PT-7a-LTLFireability-12
FORMULA_NAME DLCflexbar-PT-7a-LTLFireability-13
FORMULA_NAME DLCflexbar-PT-7a-LTLFireability-14
FORMULA_NAME DLCflexbar-PT-7a-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717034434061
FORMULA DLCflexbar-PT-7a-LTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-7a-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-7a-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-7a-LTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717034917896
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 56 (type SKEL/SRCH) for 0 DLCflexbar-PT-7a-LTLFireability-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 56 (type SKEL/SRCH) for DLCflexbar-PT-7a-LTLFireability-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 20
[[35mlola[0m][I] fired transitions : 88
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-01: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-02: AG 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-05: AG 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-09: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-11: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 59 (type SKEL/FNDP) for 6 DLCflexbar-PT-7a-LTLFireability-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 60 (type SKEL/EQUN) for 6 DLCflexbar-PT-7a-LTLFireability-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 61 (type SKEL/SRCH) for 6 DLCflexbar-PT-7a-LTLFireability-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 59 (type SKEL/FNDP) for DLCflexbar-PT-7a-LTLFireability-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 60 (type EQUN) for DLCflexbar-PT-7a-LTLFireability-02 (obsolete)
[[35mlola[0m][W] CANCELED task # 61 (type SRCH) for DLCflexbar-PT-7a-LTLFireability-02 (obsolete)
[[35mlola[0m][I] FINISHED task # 60 (type SKEL/EQUN) for DLCflexbar-PT-7a-LTLFireability-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 40 (type CNST) for 37 DLCflexbar-PT-7a-LTLFireability-11
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 40 (type CNST) for DLCflexbar-PT-7a-LTLFireability-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] planning for DLCflexbar-PT-7a-LTLFireability-00 stopped (result already fixed).
[*** LOG ERROR #0001 ***] [2024-05-30 02:00:41] [status_logger] string pointer is null
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-01: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-02: AG 0 0 0 0 2 0 0 1
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-05: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-09: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 65 (type EXCL) for 6 DLCflexbar-PT-7a-LTLFireability-02
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 63 (type FNDP) for 6 DLCflexbar-PT-7a-LTLFireability-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 64 (type EQUN) for 6 DLCflexbar-PT-7a-LTLFireability-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 65 (type EXCL) for DLCflexbar-PT-7a-LTLFireability-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 63 (type FNDP) for DLCflexbar-PT-7a-LTLFireability-02 (obsolete)
[[35mlola[0m][W] CANCELED task # 64 (type EQUN) for DLCflexbar-PT-7a-LTLFireability-02 (obsolete)
[[35mlola[0m][I] FINISHED task # 63 (type FNDP) for DLCflexbar-PT-7a-LTLFireability-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] FINISHED task # 64 (type EQUN) for DLCflexbar-PT-7a-LTLFireability-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-01: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-05: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-09: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-01: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-05: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-09: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-01: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-05: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-09: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-01: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-05: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-09: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 69 (type EXCL) for 15 DLCflexbar-PT-7a-LTLFireability-05
[[35mlola[0m][I] time limit : 254 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 67 (type FNDP) for 15 DLCflexbar-PT-7a-LTLFireability-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 68 (type EQUN) for 15 DLCflexbar-PT-7a-LTLFireability-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 69 (type EXCL) for DLCflexbar-PT-7a-LTLFireability-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 67 (type FNDP) for DLCflexbar-PT-7a-LTLFireability-05 (obsolete)
[[35mlola[0m][W] CANCELED task # 68 (type EQUN) for DLCflexbar-PT-7a-LTLFireability-05 (obsolete)
[[35mlola[0m][I] FINISHED task # 67 (type FNDP) for DLCflexbar-PT-7a-LTLFireability-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] FINISHED task # 68 (type EQUN) for DLCflexbar-PT-7a-LTLFireability-05
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-01: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-09: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-01: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-09: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-01: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-09: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-01: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-09: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 71 (type EXCL) for 3 DLCflexbar-PT-7a-LTLFireability-01
[[35mlola[0m][I] time limit : 272 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 74 (type EQUN) for 3 DLCflexbar-PT-7a-LTLFireability-01
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 71 (type EXCL) for DLCflexbar-PT-7a-LTLFireability-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 2
[[35mlola[0m][I] time used : 2
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 74 (type EQUN) for DLCflexbar-PT-7a-LTLFireability-01 (obsolete)
[[35mlola[0m][I] LAUNCH task # 51 (type EXCL) for 50 DLCflexbar-PT-7a-LTLFireability-14
[[35mlola[0m][I] time limit : 295 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 51 (type EXCL) for DLCflexbar-PT-7a-LTLFireability-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 4
[[35mlola[0m][I] fired transitions : 5
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 48 (type EXCL) for 47 DLCflexbar-PT-7a-LTLFireability-13
[[35mlola[0m][I] time limit : 322 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 48 (type EXCL) for DLCflexbar-PT-7a-LTLFireability-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 27
[[35mlola[0m][I] fired transitions : 539
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 22 (type EXCL) for 21 DLCflexbar-PT-7a-LTLFireability-07
[[35mlola[0m][I] time limit : 354 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 22 (type EXCL) for DLCflexbar-PT-7a-LTLFireability-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 3
[[35mlola[0m][I] fired transitions : 3
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] FINISHED task # 74 (type EQUN) for DLCflexbar-PT-7a-LTLFireability-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-09: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 35 (type EXCL) for 34 DLCflexbar-PT-7a-LTLFireability-10
[[35mlola[0m][I] time limit : 393 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 35 (type EXCL) for DLCflexbar-PT-7a-LTLFireability-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 2
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 32 (type EXCL) for 27 DLCflexbar-PT-7a-LTLFireability-09
[[35mlola[0m][I] time limit : 442 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 32 (type EXCL) for DLCflexbar-PT-7a-LTLFireability-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 2
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 19 (type EXCL) for 18 DLCflexbar-PT-7a-LTLFireability-06
[[35mlola[0m][I] time limit : 589 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 19 (type EXCL) for DLCflexbar-PT-7a-LTLFireability-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 DLCflexbar-PT-7a-LTLFireability-03
[[35mlola[0m][I] time limit : 707 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 10 (type EXCL) for DLCflexbar-PT-7a-LTLFireability-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 45 (type EXCL) for 44 DLCflexbar-PT-7a-LTLFireability-12
[[35mlola[0m][I] time limit : 884 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 45 (type EXCL) for DLCflexbar-PT-7a-LTLFireability-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 4
[[35mlola[0m][I] fired transitions : 4
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 54 (type EXCL) for 53 DLCflexbar-PT-7a-LTLFireability-15
[[35mlola[0m][I] time limit : 1178 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 1/1178 1/2000 DLCflexbar-PT-7a-LTLFireability-15 3521 m, 704 m/sec, 239405 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 6/1178 1/2000 DLCflexbar-PT-7a-LTLFireability-15 22926 m, 3881 m/sec, 1581819 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 11/1178 1/2000 DLCflexbar-PT-7a-LTLFireability-15 43710 m, 4156 m/sec, 3034126 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 16/1178 1/2000 DLCflexbar-PT-7a-LTLFireability-15 63577 m, 3973 m/sec, 4422005 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 21/1178 1/2000 DLCflexbar-PT-7a-LTLFireability-15 84193 m, 4123 m/sec, 5866466 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 26/1178 1/2000 DLCflexbar-PT-7a-LTLFireability-15 104761 m, 4113 m/sec, 7318123 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 31/1178 1/2000 DLCflexbar-PT-7a-LTLFireability-15 125214 m, 4090 m/sec, 8764611 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 36/1178 1/2000 DLCflexbar-PT-7a-LTLFireability-15 145542 m, 4065 m/sec, 10212003 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 41/1178 2/2000 DLCflexbar-PT-7a-LTLFireability-15 165731 m, 4037 m/sec, 11647305 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 46/1178 2/2000 DLCflexbar-PT-7a-LTLFireability-15 185803 m, 4014 m/sec, 13084332 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 51/1178 2/2000 DLCflexbar-PT-7a-LTLFireability-15 205963 m, 4032 m/sec, 14526135 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 56/1178 2/2000 DLCflexbar-PT-7a-LTLFireability-15 226017 m, 4010 m/sec, 15966958 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 61/1178 2/2000 DLCflexbar-PT-7a-LTLFireability-15 245844 m, 3965 m/sec, 17399085 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 66/1178 2/2000 DLCflexbar-PT-7a-LTLFireability-15 265878 m, 4006 m/sec, 18843952 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 71/1178 2/2000 DLCflexbar-PT-7a-LTLFireability-15 286141 m, 4052 m/sec, 20282199 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 76/1178 3/2000 DLCflexbar-PT-7a-LTLFireability-15 306625 m, 4096 m/sec, 21729394 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 140 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 81/1178 3/2000 DLCflexbar-PT-7a-LTLFireability-15 326913 m, 4057 m/sec, 23167632 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 145 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 86/1178 3/2000 DLCflexbar-PT-7a-LTLFireability-15 347018 m, 4021 m/sec, 24598865 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 91/1178 3/2000 DLCflexbar-PT-7a-LTLFireability-15 366986 m, 3993 m/sec, 26033193 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 155 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 96/1178 3/2000 DLCflexbar-PT-7a-LTLFireability-15 386985 m, 3999 m/sec, 27468909 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 160 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 101/1178 3/2000 DLCflexbar-PT-7a-LTLFireability-15 406789 m, 3960 m/sec, 28906462 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 165 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 106/1178 3/2000 DLCflexbar-PT-7a-LTLFireability-15 426541 m, 3950 m/sec, 30340214 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 170 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 111/1178 3/2000 DLCflexbar-PT-7a-LTLFireability-15 446367 m, 3965 m/sec, 31766089 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 175 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 116/1178 4/2000 DLCflexbar-PT-7a-LTLFireability-15 466127 m, 3952 m/sec, 33204389 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 180 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 121/1178 4/2000 DLCflexbar-PT-7a-LTLFireability-15 485980 m, 3970 m/sec, 34642535 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 185 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 126/1178 4/2000 DLCflexbar-PT-7a-LTLFireability-15 505564 m, 3916 m/sec, 36078338 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 190 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 131/1178 4/2000 DLCflexbar-PT-7a-LTLFireability-15 525851 m, 4057 m/sec, 37538372 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 195 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 136/1178 4/2000 DLCflexbar-PT-7a-LTLFireability-15 545841 m, 3998 m/sec, 38995774 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 200 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 141/1178 4/2000 DLCflexbar-PT-7a-LTLFireability-15 565852 m, 4002 m/sec, 40449991 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 205 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 146/1178 4/2000 DLCflexbar-PT-7a-LTLFireability-15 585658 m, 3961 m/sec, 41897778 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 210 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 151/1178 4/2000 DLCflexbar-PT-7a-LTLFireability-15 605405 m, 3949 m/sec, 43349713 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 215 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 156/1178 5/2000 DLCflexbar-PT-7a-LTLFireability-15 625030 m, 3925 m/sec, 44793539 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 220 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 161/1178 5/2000 DLCflexbar-PT-7a-LTLFireability-15 644412 m, 3876 m/sec, 46236925 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 225 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 166/1178 5/2000 DLCflexbar-PT-7a-LTLFireability-15 663982 m, 3914 m/sec, 47675197 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 230 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 171/1178 5/2000 DLCflexbar-PT-7a-LTLFireability-15 683233 m, 3850 m/sec, 49120109 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 235 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 176/1178 5/2000 DLCflexbar-PT-7a-LTLFireability-15 702632 m, 3879 m/sec, 50556358 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 240 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 181/1178 5/2000 DLCflexbar-PT-7a-LTLFireability-15 722572 m, 3988 m/sec, 52029796 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 245 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 186/1178 5/2000 DLCflexbar-PT-7a-LTLFireability-15 742346 m, 3954 m/sec, 53495122 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 250 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 191/1178 5/2000 DLCflexbar-PT-7a-LTLFireability-15 761993 m, 3929 m/sec, 54954599 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 255 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 196/1178 6/2000 DLCflexbar-PT-7a-LTLFireability-15 781534 m, 3908 m/sec, 56416647 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 260 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 201/1178 6/2000 DLCflexbar-PT-7a-LTLFireability-15 800930 m, 3879 m/sec, 57881792 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 265 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 206/1178 6/2000 DLCflexbar-PT-7a-LTLFireability-15 820173 m, 3848 m/sec, 59344660 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 270 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 211/1178 6/2000 DLCflexbar-PT-7a-LTLFireability-15 839356 m, 3836 m/sec, 60798864 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 275 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 216/1178 6/2000 DLCflexbar-PT-7a-LTLFireability-15 858592 m, 3847 m/sec, 62247785 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 280 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 221/1178 6/2000 DLCflexbar-PT-7a-LTLFireability-15 877923 m, 3866 m/sec, 63698409 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 285 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 226/1178 6/2000 DLCflexbar-PT-7a-LTLFireability-15 897887 m, 3992 m/sec, 65174134 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 290 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 231/1178 6/2000 DLCflexbar-PT-7a-LTLFireability-15 917600 m, 3942 m/sec, 66648412 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 295 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 236/1178 7/2000 DLCflexbar-PT-7a-LTLFireability-15 937353 m, 3950 m/sec, 68109930 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 300 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 241/1178 7/2000 DLCflexbar-PT-7a-LTLFireability-15 956861 m, 3901 m/sec, 69571013 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 305 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 246/1178 7/2000 DLCflexbar-PT-7a-LTLFireability-15 976370 m, 3901 m/sec, 71023817 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 310 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 251/1178 7/2000 DLCflexbar-PT-7a-LTLFireability-15 995712 m, 3868 m/sec, 72474584 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 315 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 256/1178 7/2000 DLCflexbar-PT-7a-LTLFireability-15 1015013 m, 3860 m/sec, 73935996 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 320 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 261/1178 7/2000 DLCflexbar-PT-7a-LTLFireability-15 1034185 m, 3834 m/sec, 75389135 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 325 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 266/1178 7/2000 DLCflexbar-PT-7a-LTLFireability-15 1054035 m, 3970 m/sec, 76867274 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 330 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 271/1178 8/2000 DLCflexbar-PT-7a-LTLFireability-15 1073984 m, 3989 m/sec, 78348463 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 335 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 276/1178 8/2000 DLCflexbar-PT-7a-LTLFireability-15 1093902 m, 3983 m/sec, 79823592 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 340 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 281/1178 8/2000 DLCflexbar-PT-7a-LTLFireability-15 1113571 m, 3933 m/sec, 81297695 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 345 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 286/1178 8/2000 DLCflexbar-PT-7a-LTLFireability-15 1133311 m, 3948 m/sec, 82765713 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 350 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 291/1178 8/2000 DLCflexbar-PT-7a-LTLFireability-15 1152803 m, 3898 m/sec, 84236459 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 355 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 296/1178 8/2000 DLCflexbar-PT-7a-LTLFireability-15 1172351 m, 3909 m/sec, 85708915 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 360 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 301/1178 8/2000 DLCflexbar-PT-7a-LTLFireability-15 1191725 m, 3874 m/sec, 87186548 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 365 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 306/1178 8/2000 DLCflexbar-PT-7a-LTLFireability-15 1211308 m, 3916 m/sec, 88653605 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 370 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 311/1178 9/2000 DLCflexbar-PT-7a-LTLFireability-15 1230762 m, 3890 m/sec, 90123866 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 375 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 316/1178 9/2000 DLCflexbar-PT-7a-LTLFireability-15 1250211 m, 3889 m/sec, 91598003 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 380 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 321/1178 9/2000 DLCflexbar-PT-7a-LTLFireability-15 1269892 m, 3936 m/sec, 93080541 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 385 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 326/1178 9/2000 DLCflexbar-PT-7a-LTLFireability-15 1289404 m, 3902 m/sec, 94567708 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 390 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 331/1178 9/2000 DLCflexbar-PT-7a-LTLFireability-15 1308871 m, 3893 m/sec, 96048163 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 395 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 336/1178 9/2000 DLCflexbar-PT-7a-LTLFireability-15 1328148 m, 3855 m/sec, 97520866 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 400 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 341/1178 9/2000 DLCflexbar-PT-7a-LTLFireability-15 1347369 m, 3844 m/sec, 98994470 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 405 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 346/1178 9/2000 DLCflexbar-PT-7a-LTLFireability-15 1366337 m, 3793 m/sec, 100470489 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 410 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 351/1178 10/2000 DLCflexbar-PT-7a-LTLFireability-15 1385124 m, 3757 m/sec, 101907440 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 415 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 356/1178 10/2000 DLCflexbar-PT-7a-LTLFireability-15 1403397 m, 3654 m/sec, 103331831 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 420 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 361/1178 10/2000 DLCflexbar-PT-7a-LTLFireability-15 1422284 m, 3777 m/sec, 104798201 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 425 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 366/1178 10/2000 DLCflexbar-PT-7a-LTLFireability-15 1441086 m, 3760 m/sec, 106262874 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 430 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 371/1178 10/2000 DLCflexbar-PT-7a-LTLFireability-15 1459866 m, 3756 m/sec, 107724085 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 435 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 376/1178 10/2000 DLCflexbar-PT-7a-LTLFireability-15 1479036 m, 3834 m/sec, 109189646 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 440 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 381/1178 10/2000 DLCflexbar-PT-7a-LTLFireability-15 1497573 m, 3707 m/sec, 110654922 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 445 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 386/1178 10/2000 DLCflexbar-PT-7a-LTLFireability-15 1516846 m, 3854 m/sec, 112140524 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 450 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 391/1178 11/2000 DLCflexbar-PT-7a-LTLFireability-15 1535866 m, 3804 m/sec, 113622444 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 455 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 396/1178 11/2000 DLCflexbar-PT-7a-LTLFireability-15 1554666 m, 3760 m/sec, 115090667 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 460 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 401/1178 11/2000 DLCflexbar-PT-7a-LTLFireability-15 1573350 m, 3736 m/sec, 116549834 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 465 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 406/1178 11/2000 DLCflexbar-PT-7a-LTLFireability-15 1591758 m, 3681 m/sec, 118008820 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 470 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 411/1178 11/2000 DLCflexbar-PT-7a-LTLFireability-15 1610236 m, 3695 m/sec, 119470626 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 475 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-01: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-7a-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-7a-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-7a-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 416/1178 11/2000 DLCflexbar-PT-7a-LTLFireability-15 1627999 m, 3552 m/sec, 120878696 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 480 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 410 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-7a"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is DLCflexbar-PT-7a, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r115-smll-171624276300084"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-7a.tgz
mv DLCflexbar-PT-7a execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;