About the Execution of LoLA for DLCflexbar-PT-6b
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 15156.483 | 3600000.00 | 5569730.00 | 10482.80 | [undef] | Time out reached |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r115-smll-171624276300075.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is DLCflexbar-PT-6b, examination is LTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r115-smll-171624276300075
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 11M
-rw-r--r-- 1 mcc users 6.4K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 65K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.5K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 51K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K May 19 07:08 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K May 19 15:42 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K May 19 07:15 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 19 18:10 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Apr 12 13:03 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 104K Apr 12 13:03 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Apr 12 13:02 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 88K Apr 12 13:02 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 22 14:37 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Apr 22 14:37 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 3 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 9.6M May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCflexbar-PT-6b-LTLCardinality-00
FORMULA_NAME DLCflexbar-PT-6b-LTLCardinality-01
FORMULA_NAME DLCflexbar-PT-6b-LTLCardinality-02
FORMULA_NAME DLCflexbar-PT-6b-LTLCardinality-03
FORMULA_NAME DLCflexbar-PT-6b-LTLCardinality-04
FORMULA_NAME DLCflexbar-PT-6b-LTLCardinality-05
FORMULA_NAME DLCflexbar-PT-6b-LTLCardinality-06
FORMULA_NAME DLCflexbar-PT-6b-LTLCardinality-07
FORMULA_NAME DLCflexbar-PT-6b-LTLCardinality-08
FORMULA_NAME DLCflexbar-PT-6b-LTLCardinality-09
FORMULA_NAME DLCflexbar-PT-6b-LTLCardinality-10
FORMULA_NAME DLCflexbar-PT-6b-LTLCardinality-11
FORMULA_NAME DLCflexbar-PT-6b-LTLCardinality-12
FORMULA_NAME DLCflexbar-PT-6b-LTLCardinality-13
FORMULA_NAME DLCflexbar-PT-6b-LTLCardinality-14
FORMULA_NAME DLCflexbar-PT-6b-LTLCardinality-15
=== Now, execution of the tool begins
BK_START 1717029177192
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLCardinality.xml[0m
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-05: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-08: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-10: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 192 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-05: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-08: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-10: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 197 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-05: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-08: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-10: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 202 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-05: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-08: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-10: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 207 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-05: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-08: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-10: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 212 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-05: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-08: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-10: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 217 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-05: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-08: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-10: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 222 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-05: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-08: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-10: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 227 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-05: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-08: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-10: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 232 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-05: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-08: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-10: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 237 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-05: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-08: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-10: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 242 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-05: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-08: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-10: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 247 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-05: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-08: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-10: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 252 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-05: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-08: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-10: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 257 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-05: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-08: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-10: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 262 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-05: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-08: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-10: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 267 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-05: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-08: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-10: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 272 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-05: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-08: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-10: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 277 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-05: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-08: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-10: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 282 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-05: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-08: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-10: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 287 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-05: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-08: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-10: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 292 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-05: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-08: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-10: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 297 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-05: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-08: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-10: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 302 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-05: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-08: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-10: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 307 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-05: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-08: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-10: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 312 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-05: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-08: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-10: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 317 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-05: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-08: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-10: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 322 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-05: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-08: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-10: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 327 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-05: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-08: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-10: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 332 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-05: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-08: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-10: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 337 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-05: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-08: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-10: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 342 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-05: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-08: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-10: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 347 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-05: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-08: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-10: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 352 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-05: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-08: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-10: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 357 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-05: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-08: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-10: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 362 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 29 (type CNST) for 28 DLCflexbar-PT-6b-LTLCardinality-08
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 29 (type CNST) for DLCflexbar-PT-6b-LTLCardinality-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 20 (type CNST) for 19 DLCflexbar-PT-6b-LTLCardinality-05
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 35 (type CNST) for 34 DLCflexbar-PT-6b-LTLCardinality-10
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 35 (type CNST) for DLCflexbar-PT-6b-LTLCardinality-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 20 (type CNST) for DLCflexbar-PT-6b-LTLCardinality-05
[[35mlola[0m][I] result : false
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 367 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 372 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 377 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 382 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 387 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 392 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 397 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 402 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 407 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 412 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 417 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 422 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 427 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 432 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 437 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 442 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 447 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 452 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 457 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 462 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 467 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 472 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 477 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 482 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 487 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 492 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 497 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 502 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 507 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 512 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 517 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 522 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 527 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 532 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 537 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 542 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 547 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 552 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 557 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 562 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 567 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 572 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 577 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 582 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 587 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 592 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 597 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 602 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 607 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 612 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 617 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 622 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 627 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 632 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 637 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 642 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 647 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 652 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 657 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 662 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 667 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 672 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 677 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 682 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 687 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 692 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 697 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 702 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 707 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 712 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 717 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 722 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 727 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 732 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 737 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 742 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 747 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 752 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 757 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 762 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 767 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 772 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 777 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 782 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 787 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 792 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 797 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 802 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 807 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 812 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 817 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 822 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 827 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 6 (type EXCL) for 3 DLCflexbar-PT-6b-LTLCardinality-01
[[35mlola[0m][I] time limit : 198 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 6 (type EXCL) for DLCflexbar-PT-6b-LTLCardinality-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1403
[[35mlola[0m][I] fired transitions : 1404
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 41 (type EXCL) for 40 DLCflexbar-PT-6b-LTLCardinality-12
[[35mlola[0m][I] time limit : 231 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 41 (type EXCL) for DLCflexbar-PT-6b-LTLCardinality-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 832 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 837 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 842 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 847 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 852 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 857 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 862 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 867 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 872 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 877 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 882 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 887 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 892 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 897 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 902 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 907 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 912 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 917 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 922 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 927 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 932 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 937 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 942 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 947 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 952 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 957 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 962 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 967 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 972 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 977 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 982 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 987 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 992 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 997 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1002 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1007 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1012 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 23 (type EXCL) for 22 DLCflexbar-PT-6b-LTLCardinality-06
[[35mlola[0m][I] time limit : 235 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 23 (type EXCL) for DLCflexbar-PT-6b-LTLCardinality-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 154
[[35mlola[0m][I] fired transitions : 154
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 11 (type EXCL) for 10 DLCflexbar-PT-6b-LTLCardinality-02
[[35mlola[0m][I] time limit : 258 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 1/258 1/2000 DLCflexbar-PT-6b-LTLCardinality-02 1865 m, 373 m/sec, 1963 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1017 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 6/258 4/2000 DLCflexbar-PT-6b-LTLCardinality-02 21658 m, 3958 m/sec, 23603 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1022 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 11/258 8/2000 DLCflexbar-PT-6b-LTLCardinality-02 59749 m, 7618 m/sec, 64861 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1027 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 16/258 11/2000 DLCflexbar-PT-6b-LTLCardinality-02 97614 m, 7573 m/sec, 106131 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1032 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 21/258 15/2000 DLCflexbar-PT-6b-LTLCardinality-02 135728 m, 7622 m/sec, 147668 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1037 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 26/258 18/2000 DLCflexbar-PT-6b-LTLCardinality-02 173523 m, 7559 m/sec, 188931 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1042 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 31/258 22/2000 DLCflexbar-PT-6b-LTLCardinality-02 211565 m, 7608 m/sec, 230444 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1047 secs. Pages in use: 22
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 36/258 25/2000 DLCflexbar-PT-6b-LTLCardinality-02 249720 m, 7631 m/sec, 272047 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1052 secs. Pages in use: 25
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 41/258 29/2000 DLCflexbar-PT-6b-LTLCardinality-02 287693 m, 7594 m/sec, 313558 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1057 secs. Pages in use: 29
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 46/258 32/2000 DLCflexbar-PT-6b-LTLCardinality-02 325709 m, 7603 m/sec, 355084 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1062 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 51/258 36/2000 DLCflexbar-PT-6b-LTLCardinality-02 363521 m, 7562 m/sec, 396294 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1067 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 56/258 39/2000 DLCflexbar-PT-6b-LTLCardinality-02 401152 m, 7526 m/sec, 437345 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1072 secs. Pages in use: 39
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 61/258 42/2000 DLCflexbar-PT-6b-LTLCardinality-02 438570 m, 7483 m/sec, 478489 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1077 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 66/258 45/2000 DLCflexbar-PT-6b-LTLCardinality-02 475971 m, 7480 m/sec, 519491 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1082 secs. Pages in use: 45
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 71/258 48/2000 DLCflexbar-PT-6b-LTLCardinality-02 513172 m, 7440 m/sec, 560942 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1087 secs. Pages in use: 48
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 76/258 51/2000 DLCflexbar-PT-6b-LTLCardinality-02 550566 m, 7478 m/sec, 602476 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1092 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 81/258 53/2000 DLCflexbar-PT-6b-LTLCardinality-02 587438 m, 7374 m/sec, 644320 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1097 secs. Pages in use: 53
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 86/258 55/2000 DLCflexbar-PT-6b-LTLCardinality-02 624494 m, 7411 m/sec, 685994 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1102 secs. Pages in use: 55
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 91/258 58/2000 DLCflexbar-PT-6b-LTLCardinality-02 660912 m, 7283 m/sec, 727702 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1107 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 96/258 60/2000 DLCflexbar-PT-6b-LTLCardinality-02 696875 m, 7192 m/sec, 769691 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1112 secs. Pages in use: 60
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 101/258 62/2000 DLCflexbar-PT-6b-LTLCardinality-02 732680 m, 7161 m/sec, 812045 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1117 secs. Pages in use: 62
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 106/258 64/2000 DLCflexbar-PT-6b-LTLCardinality-02 769019 m, 7267 m/sec, 854033 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1122 secs. Pages in use: 64
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 111/258 67/2000 DLCflexbar-PT-6b-LTLCardinality-02 805089 m, 7214 m/sec, 896345 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1127 secs. Pages in use: 67
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 116/258 68/2000 DLCflexbar-PT-6b-LTLCardinality-02 840134 m, 7009 m/sec, 939034 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1132 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 121/258 70/2000 DLCflexbar-PT-6b-LTLCardinality-02 876072 m, 7187 m/sec, 981636 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1137 secs. Pages in use: 70
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 126/258 72/2000 DLCflexbar-PT-6b-LTLCardinality-02 912181 m, 7221 m/sec, 1024202 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1142 secs. Pages in use: 72
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 131/258 75/2000 DLCflexbar-PT-6b-LTLCardinality-02 947767 m, 7117 m/sec, 1067118 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1147 secs. Pages in use: 75
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 136/258 76/2000 DLCflexbar-PT-6b-LTLCardinality-02 982572 m, 6961 m/sec, 1110262 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1152 secs. Pages in use: 76
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 141/258 78/2000 DLCflexbar-PT-6b-LTLCardinality-02 1017532 m, 6992 m/sec, 1153615 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1157 secs. Pages in use: 78
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 146/258 80/2000 DLCflexbar-PT-6b-LTLCardinality-02 1054464 m, 7386 m/sec, 1195798 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1162 secs. Pages in use: 80
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 151/258 82/2000 DLCflexbar-PT-6b-LTLCardinality-02 1090702 m, 7247 m/sec, 1237671 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1167 secs. Pages in use: 82
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 156/258 84/2000 DLCflexbar-PT-6b-LTLCardinality-02 1126468 m, 7153 m/sec, 1279722 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1172 secs. Pages in use: 84
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 161/258 86/2000 DLCflexbar-PT-6b-LTLCardinality-02 1161381 m, 6982 m/sec, 1322626 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1177 secs. Pages in use: 86
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 166/258 88/2000 DLCflexbar-PT-6b-LTLCardinality-02 1197246 m, 7173 m/sec, 1365212 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1182 secs. Pages in use: 88
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 171/258 90/2000 DLCflexbar-PT-6b-LTLCardinality-02 1233594 m, 7269 m/sec, 1407664 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1187 secs. Pages in use: 90
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 176/258 92/2000 DLCflexbar-PT-6b-LTLCardinality-02 1269498 m, 7180 m/sec, 1450422 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1192 secs. Pages in use: 92
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 181/258 94/2000 DLCflexbar-PT-6b-LTLCardinality-02 1306511 m, 7402 m/sec, 1492929 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1197 secs. Pages in use: 94
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 186/258 96/2000 DLCflexbar-PT-6b-LTLCardinality-02 1342919 m, 7281 m/sec, 1535791 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1202 secs. Pages in use: 96
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 191/258 98/2000 DLCflexbar-PT-6b-LTLCardinality-02 1378945 m, 7205 m/sec, 1578541 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1207 secs. Pages in use: 98
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 196/258 100/2000 DLCflexbar-PT-6b-LTLCardinality-02 1414538 m, 7118 m/sec, 1621534 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1212 secs. Pages in use: 100
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 201/258 102/2000 DLCflexbar-PT-6b-LTLCardinality-02 1450457 m, 7183 m/sec, 1664471 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1217 secs. Pages in use: 102
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 206/258 105/2000 DLCflexbar-PT-6b-LTLCardinality-02 1487275 m, 7363 m/sec, 1706988 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1222 secs. Pages in use: 105
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 211/258 107/2000 DLCflexbar-PT-6b-LTLCardinality-02 1525019 m, 7548 m/sec, 1749223 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1227 secs. Pages in use: 107
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 216/258 109/2000 DLCflexbar-PT-6b-LTLCardinality-02 1562481 m, 7492 m/sec, 1791473 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1232 secs. Pages in use: 109
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 221/258 111/2000 DLCflexbar-PT-6b-LTLCardinality-02 1599115 m, 7326 m/sec, 1834096 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1237 secs. Pages in use: 111
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 226/258 113/2000 DLCflexbar-PT-6b-LTLCardinality-02 1635836 m, 7344 m/sec, 1876785 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1242 secs. Pages in use: 113
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 231/258 116/2000 DLCflexbar-PT-6b-LTLCardinality-02 1673480 m, 7528 m/sec, 1920354 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1247 secs. Pages in use: 116
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 236/258 118/2000 DLCflexbar-PT-6b-LTLCardinality-02 1712966 m, 7897 m/sec, 1964201 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1252 secs. Pages in use: 118
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 241/258 120/2000 DLCflexbar-PT-6b-LTLCardinality-02 1750852 m, 7577 m/sec, 2008630 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1257 secs. Pages in use: 120
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 246/258 122/2000 DLCflexbar-PT-6b-LTLCardinality-02 1788753 m, 7580 m/sec, 2053546 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1262 secs. Pages in use: 122
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 251/258 124/2000 DLCflexbar-PT-6b-LTLCardinality-02 1827280 m, 7705 m/sec, 2098211 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1267 secs. Pages in use: 124
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 256/258 126/2000 DLCflexbar-PT-6b-LTLCardinality-02 1865507 m, 7645 m/sec, 2142999 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1272 secs. Pages in use: 126
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 11 (type EXCL) for DLCflexbar-PT-6b-LTLCardinality-02 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1277 secs. Pages in use: 128
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 50 (type EXCL) for 49 DLCflexbar-PT-6b-LTLCardinality-15
[[35mlola[0m][I] time limit : 258 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 11 (type EXCL) for 10 DLCflexbar-PT-6b-LTLCardinality-02
[[35mlola[0m][I] time limit : 2323 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] CANCELED task # 11 (type EXCL) for DLCflexbar-PT-6b-LTLCardinality-02 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 5/258 6/2000 DLCflexbar-PT-6b-LTLCardinality-15 38822 m, 7764 m/sec, 42393 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1282 secs. Pages in use: 138
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 10/258 10/2000 DLCflexbar-PT-6b-LTLCardinality-15 79671 m, 8169 m/sec, 86590 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1287 secs. Pages in use: 138
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 15/258 13/2000 DLCflexbar-PT-6b-LTLCardinality-15 119922 m, 8050 m/sec, 130348 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1292 secs. Pages in use: 141
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 20/258 17/2000 DLCflexbar-PT-6b-LTLCardinality-15 159468 m, 7909 m/sec, 173650 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1297 secs. Pages in use: 145
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 25/258 20/2000 DLCflexbar-PT-6b-LTLCardinality-15 198881 m, 7882 m/sec, 216562 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1302 secs. Pages in use: 148
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 30/258 24/2000 DLCflexbar-PT-6b-LTLCardinality-15 238244 m, 7872 m/sec, 259539 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1307 secs. Pages in use: 152
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 35/258 28/2000 DLCflexbar-PT-6b-LTLCardinality-15 278637 m, 8078 m/sec, 303664 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1312 secs. Pages in use: 156
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 40/258 32/2000 DLCflexbar-PT-6b-LTLCardinality-15 318895 m, 8051 m/sec, 347635 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1317 secs. Pages in use: 160
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 45/258 35/2000 DLCflexbar-PT-6b-LTLCardinality-15 359146 m, 8050 m/sec, 391402 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1322 secs. Pages in use: 163
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 50/258 39/2000 DLCflexbar-PT-6b-LTLCardinality-15 399384 m, 8047 m/sec, 435444 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1327 secs. Pages in use: 167
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 55/258 43/2000 DLCflexbar-PT-6b-LTLCardinality-15 439236 m, 7970 m/sec, 479217 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1332 secs. Pages in use: 171
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 60/258 46/2000 DLCflexbar-PT-6b-LTLCardinality-15 478266 m, 7806 m/sec, 522079 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1337 secs. Pages in use: 174
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 65/258 48/2000 DLCflexbar-PT-6b-LTLCardinality-15 518318 m, 8010 m/sec, 566801 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1342 secs. Pages in use: 176
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 70/258 51/2000 DLCflexbar-PT-6b-LTLCardinality-15 558355 m, 8007 m/sec, 611492 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1347 secs. Pages in use: 179
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 75/258 54/2000 DLCflexbar-PT-6b-LTLCardinality-15 598051 m, 7939 m/sec, 656318 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1352 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 80/258 56/2000 DLCflexbar-PT-6b-LTLCardinality-15 637459 m, 7881 m/sec, 701195 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1357 secs. Pages in use: 184
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 85/258 59/2000 DLCflexbar-PT-6b-LTLCardinality-15 676532 m, 7814 m/sec, 746236 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1362 secs. Pages in use: 187
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 90/258 61/2000 DLCflexbar-PT-6b-LTLCardinality-15 714737 m, 7641 m/sec, 791552 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1367 secs. Pages in use: 189
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 95/258 63/2000 DLCflexbar-PT-6b-LTLCardinality-15 753735 m, 7799 m/sec, 836665 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1372 secs. Pages in use: 191
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 100/258 66/2000 DLCflexbar-PT-6b-LTLCardinality-15 792530 m, 7759 m/sec, 881854 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1377 secs. Pages in use: 194
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 105/258 68/2000 DLCflexbar-PT-6b-LTLCardinality-15 830601 m, 7614 m/sec, 927379 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1382 secs. Pages in use: 196
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 110/258 70/2000 DLCflexbar-PT-6b-LTLCardinality-15 868666 m, 7613 m/sec, 972953 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1387 secs. Pages in use: 198
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 115/258 72/2000 DLCflexbar-PT-6b-LTLCardinality-15 907047 m, 7676 m/sec, 1018424 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1392 secs. Pages in use: 200
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 120/258 74/2000 DLCflexbar-PT-6b-LTLCardinality-15 945302 m, 7651 m/sec, 1063972 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1397 secs. Pages in use: 202
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 125/258 76/2000 DLCflexbar-PT-6b-LTLCardinality-15 982331 m, 7405 m/sec, 1109951 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1402 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 130/258 78/2000 DLCflexbar-PT-6b-LTLCardinality-15 1019602 m, 7454 m/sec, 1156009 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1407 secs. Pages in use: 206
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 135/258 81/2000 DLCflexbar-PT-6b-LTLCardinality-15 1058878 m, 7855 m/sec, 1200721 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1412 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 140/258 83/2000 DLCflexbar-PT-6b-LTLCardinality-15 1097425 m, 7709 m/sec, 1245587 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1417 secs. Pages in use: 211
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 145/258 84/2000 DLCflexbar-PT-6b-LTLCardinality-15 1135772 m, 7669 m/sec, 1290616 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1422 secs. Pages in use: 212
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 150/258 87/2000 DLCflexbar-PT-6b-LTLCardinality-15 1172956 m, 7436 m/sec, 1336465 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1427 secs. Pages in use: 215
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 155/258 89/2000 DLCflexbar-PT-6b-LTLCardinality-15 1211565 m, 7721 m/sec, 1381397 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1432 secs. Pages in use: 217
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 160/258 91/2000 DLCflexbar-PT-6b-LTLCardinality-15 1248614 m, 7409 m/sec, 1425972 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1437 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 165/258 93/2000 DLCflexbar-PT-6b-LTLCardinality-15 1286886 m, 7654 m/sec, 1470634 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1442 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 170/258 96/2000 DLCflexbar-PT-6b-LTLCardinality-15 1326456 m, 7914 m/sec, 1515400 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1447 secs. Pages in use: 224
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 175/258 98/2000 DLCflexbar-PT-6b-LTLCardinality-15 1364157 m, 7540 m/sec, 1560614 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1452 secs. Pages in use: 226
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 180/258 100/2000 DLCflexbar-PT-6b-LTLCardinality-15 1401702 m, 7509 m/sec, 1606145 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1457 secs. Pages in use: 228
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 185/258 102/2000 DLCflexbar-PT-6b-LTLCardinality-15 1439399 m, 7539 m/sec, 1651513 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1462 secs. Pages in use: 230
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 190/258 104/2000 DLCflexbar-PT-6b-LTLCardinality-15 1476938 m, 7507 m/sec, 1695463 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1467 secs. Pages in use: 232
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 195/258 106/2000 DLCflexbar-PT-6b-LTLCardinality-15 1514715 m, 7555 m/sec, 1737981 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1472 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 200/258 109/2000 DLCflexbar-PT-6b-LTLCardinality-15 1552483 m, 7553 m/sec, 1780272 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1477 secs. Pages in use: 237
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 205/258 111/2000 DLCflexbar-PT-6b-LTLCardinality-15 1589837 m, 7470 m/sec, 1823022 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1482 secs. Pages in use: 239
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 210/258 113/2000 DLCflexbar-PT-6b-LTLCardinality-15 1626780 m, 7388 m/sec, 1866140 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1487 secs. Pages in use: 241
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 215/258 115/2000 DLCflexbar-PT-6b-LTLCardinality-15 1663712 m, 7386 m/sec, 1908641 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1492 secs. Pages in use: 243
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 220/258 117/2000 DLCflexbar-PT-6b-LTLCardinality-15 1701054 m, 7468 m/sec, 1950897 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1497 secs. Pages in use: 245
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 225/258 119/2000 DLCflexbar-PT-6b-LTLCardinality-15 1737819 m, 7353 m/sec, 1993396 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1502 secs. Pages in use: 247
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 230/258 121/2000 DLCflexbar-PT-6b-LTLCardinality-15 1774318 m, 7299 m/sec, 2036299 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1507 secs. Pages in use: 249
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 235/258 123/2000 DLCflexbar-PT-6b-LTLCardinality-15 1811201 m, 7376 m/sec, 2078936 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1512 secs. Pages in use: 251
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 240/258 125/2000 DLCflexbar-PT-6b-LTLCardinality-15 1847627 m, 7285 m/sec, 2121844 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1517 secs. Pages in use: 253
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 245/258 127/2000 DLCflexbar-PT-6b-LTLCardinality-15 1883888 m, 7252 m/sec, 2164878 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1522 secs. Pages in use: 255
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 250/258 129/2000 DLCflexbar-PT-6b-LTLCardinality-15 1919804 m, 7183 m/sec, 2208067 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1527 secs. Pages in use: 257
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 255/258 131/2000 DLCflexbar-PT-6b-LTLCardinality-15 1956371 m, 7313 m/sec, 2250334 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1532 secs. Pages in use: 259
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 50 (type EXCL) for DLCflexbar-PT-6b-LTLCardinality-15 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1537 secs. Pages in use: 261
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 47 (type EXCL) for 46 DLCflexbar-PT-6b-LTLCardinality-14
[[35mlola[0m][I] time limit : 257 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 50 (type EXCL) for 49 DLCflexbar-PT-6b-LTLCardinality-15
[[35mlola[0m][I] time limit : 2063 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 47 (type EXCL) for DLCflexbar-PT-6b-LTLCardinality-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] CANCELED task # 50 (type EXCL) for DLCflexbar-PT-6b-LTLCardinality-15 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1542 secs. Pages in use: 266
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 44 (type EXCL) for 43 DLCflexbar-PT-6b-LTLCardinality-13
[[35mlola[0m][I] time limit : 294 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 44 (type EXCL) for DLCflexbar-PT-6b-LTLCardinality-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 154
[[35mlola[0m][I] fired transitions : 154
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 38 (type EXCL) for 37 DLCflexbar-PT-6b-LTLCardinality-11
[[35mlola[0m][I] time limit : 343 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 38 (type EXCL) for DLCflexbar-PT-6b-LTLCardinality-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 307
[[35mlola[0m][I] fired transitions : 308
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 32 (type EXCL) for 31 DLCflexbar-PT-6b-LTLCardinality-09
[[35mlola[0m][I] time limit : 411 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 32 (type EXCL) for DLCflexbar-PT-6b-LTLCardinality-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 154
[[35mlola[0m][I] fired transitions : 154
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 26 (type EXCL) for 25 DLCflexbar-PT-6b-LTLCardinality-07
[[35mlola[0m][I] time limit : 514 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 26 (type EXCL) for DLCflexbar-PT-6b-LTLCardinality-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 3
[[35mlola[0m][I] fired transitions : 2
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 17 (type EXCL) for 16 DLCflexbar-PT-6b-LTLCardinality-04
[[35mlola[0m][I] time limit : 686 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 17 (type EXCL) for DLCflexbar-PT-6b-LTLCardinality-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 154
[[35mlola[0m][I] fired transitions : 154
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 14 (type EXCL) for 13 DLCflexbar-PT-6b-LTLCardinality-03
[[35mlola[0m][I] time limit : 1029 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 14 (type EXCL) for DLCflexbar-PT-6b-LTLCardinality-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 154
[[35mlola[0m][I] fired transitions : 154
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 DLCflexbar-PT-6b-LTLCardinality-00
[[35mlola[0m][I] time limit : 2058 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 5/2058 2/2000 DLCflexbar-PT-6b-LTLCardinality-00 37957 m, 7591 m/sec, 41071 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1547 secs. Pages in use: 266
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 10/2058 5/2000 DLCflexbar-PT-6b-LTLCardinality-00 76666 m, 7741 m/sec, 83673 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1552 secs. Pages in use: 266
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 15/2058 7/2000 DLCflexbar-PT-6b-LTLCardinality-00 115507 m, 7768 m/sec, 126150 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1557 secs. Pages in use: 268
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 20/2058 8/2000 DLCflexbar-PT-6b-LTLCardinality-00 154738 m, 7846 m/sec, 168351 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1562 secs. Pages in use: 269
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 25/2058 9/2000 DLCflexbar-PT-6b-LTLCardinality-00 194054 m, 7863 m/sec, 210659 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1567 secs. Pages in use: 270
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 30/2058 10/2000 DLCflexbar-PT-6b-LTLCardinality-00 232810 m, 7751 m/sec, 253006 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1572 secs. Pages in use: 271
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 35/2058 12/2000 DLCflexbar-PT-6b-LTLCardinality-00 271544 m, 7746 m/sec, 295192 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1577 secs. Pages in use: 273
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 40/2058 13/2000 DLCflexbar-PT-6b-LTLCardinality-00 310174 m, 7726 m/sec, 337506 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1582 secs. Pages in use: 274
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 45/2058 15/2000 DLCflexbar-PT-6b-LTLCardinality-00 349264 m, 7818 m/sec, 379534 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1587 secs. Pages in use: 276
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 50/2058 16/2000 DLCflexbar-PT-6b-LTLCardinality-00 387832 m, 7713 m/sec, 421731 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1592 secs. Pages in use: 277
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 55/2058 17/2000 DLCflexbar-PT-6b-LTLCardinality-00 426460 m, 7725 m/sec, 464065 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1597 secs. Pages in use: 278
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 60/2058 18/2000 DLCflexbar-PT-6b-LTLCardinality-00 465111 m, 7730 m/sec, 506247 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1602 secs. Pages in use: 279
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 65/2058 20/2000 DLCflexbar-PT-6b-LTLCardinality-00 503673 m, 7712 m/sec, 548613 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1607 secs. Pages in use: 281
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 70/2058 21/2000 DLCflexbar-PT-6b-LTLCardinality-00 542749 m, 7815 m/sec, 591078 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1612 secs. Pages in use: 282
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 75/2058 23/2000 DLCflexbar-PT-6b-LTLCardinality-00 581817 m, 7813 m/sec, 633726 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1617 secs. Pages in use: 284
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 80/2058 24/2000 DLCflexbar-PT-6b-LTLCardinality-00 620810 m, 7798 m/sec, 676391 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1622 secs. Pages in use: 285
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 85/2058 25/2000 DLCflexbar-PT-6b-LTLCardinality-00 659953 m, 7828 m/sec, 718906 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1627 secs. Pages in use: 286
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 90/2058 27/2000 DLCflexbar-PT-6b-LTLCardinality-00 699196 m, 7848 m/sec, 761374 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1632 secs. Pages in use: 288
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 95/2058 28/2000 DLCflexbar-PT-6b-LTLCardinality-00 738211 m, 7803 m/sec, 803998 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1637 secs. Pages in use: 289
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 100/2058 29/2000 DLCflexbar-PT-6b-LTLCardinality-00 777134 m, 7784 m/sec, 846764 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1642 secs. Pages in use: 290
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 105/2058 31/2000 DLCflexbar-PT-6b-LTLCardinality-00 816141 m, 7801 m/sec, 889487 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1647 secs. Pages in use: 292
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 110/2058 32/2000 DLCflexbar-PT-6b-LTLCardinality-00 855239 m, 7819 m/sec, 932215 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1652 secs. Pages in use: 293
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 115/2058 34/2000 DLCflexbar-PT-6b-LTLCardinality-00 894490 m, 7850 m/sec, 974704 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1657 secs. Pages in use: 295
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 120/2058 35/2000 DLCflexbar-PT-6b-LTLCardinality-00 933488 m, 7799 m/sec, 1017368 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1662 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 125/2058 36/2000 DLCflexbar-PT-6b-LTLCardinality-00 972406 m, 7783 m/sec, 1059982 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1667 secs. Pages in use: 297
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 130/2058 38/2000 DLCflexbar-PT-6b-LTLCardinality-00 1011658 m, 7850 m/sec, 1102488 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1672 secs. Pages in use: 299
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 135/2058 39/2000 DLCflexbar-PT-6b-LTLCardinality-00 1050597 m, 7787 m/sec, 1145115 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1677 secs. Pages in use: 300
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 140/2058 40/2000 DLCflexbar-PT-6b-LTLCardinality-00 1089540 m, 7788 m/sec, 1187795 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1682 secs. Pages in use: 301
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 145/2058 42/2000 DLCflexbar-PT-6b-LTLCardinality-00 1128559 m, 7803 m/sec, 1230304 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1687 secs. Pages in use: 303
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 150/2058 43/2000 DLCflexbar-PT-6b-LTLCardinality-00 1167473 m, 7782 m/sec, 1272884 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1692 secs. Pages in use: 304
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 155/2058 45/2000 DLCflexbar-PT-6b-LTLCardinality-00 1206665 m, 7838 m/sec, 1315486 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1697 secs. Pages in use: 306
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 160/2058 46/2000 DLCflexbar-PT-6b-LTLCardinality-00 1245901 m, 7847 m/sec, 1357945 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1702 secs. Pages in use: 307
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 165/2058 47/2000 DLCflexbar-PT-6b-LTLCardinality-00 1284737 m, 7767 m/sec, 1400435 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1707 secs. Pages in use: 308
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 170/2058 48/2000 DLCflexbar-PT-6b-LTLCardinality-00 1322750 m, 7602 m/sec, 1443299 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1712 secs. Pages in use: 309
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 175/2058 49/2000 DLCflexbar-PT-6b-LTLCardinality-00 1361894 m, 7828 m/sec, 1485572 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1717 secs. Pages in use: 310
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 180/2058 51/2000 DLCflexbar-PT-6b-LTLCardinality-00 1400584 m, 7738 m/sec, 1528195 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1722 secs. Pages in use: 312
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 185/2058 52/2000 DLCflexbar-PT-6b-LTLCardinality-00 1439014 m, 7686 m/sec, 1570976 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1727 secs. Pages in use: 313
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 190/2058 53/2000 DLCflexbar-PT-6b-LTLCardinality-00 1477467 m, 7690 m/sec, 1613813 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1732 secs. Pages in use: 314
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 195/2058 54/2000 DLCflexbar-PT-6b-LTLCardinality-00 1515783 m, 7663 m/sec, 1656876 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1737 secs. Pages in use: 315
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 200/2058 55/2000 DLCflexbar-PT-6b-LTLCardinality-00 1554297 m, 7702 m/sec, 1699547 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1742 secs. Pages in use: 316
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 205/2058 56/2000 DLCflexbar-PT-6b-LTLCardinality-00 1592680 m, 7676 m/sec, 1742530 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1747 secs. Pages in use: 317
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 210/2058 58/2000 DLCflexbar-PT-6b-LTLCardinality-00 1631375 m, 7739 m/sec, 1785202 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1752 secs. Pages in use: 319
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 215/2058 58/2000 DLCflexbar-PT-6b-LTLCardinality-00 1669368 m, 7598 m/sec, 1828094 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1757 secs. Pages in use: 319
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 220/2058 60/2000 DLCflexbar-PT-6b-LTLCardinality-00 1707773 m, 7681 m/sec, 1870766 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1762 secs. Pages in use: 321
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 225/2058 61/2000 DLCflexbar-PT-6b-LTLCardinality-00 1745141 m, 7473 m/sec, 1913908 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1767 secs. Pages in use: 322
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 230/2058 61/2000 DLCflexbar-PT-6b-LTLCardinality-00 1783322 m, 7636 m/sec, 1956734 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1772 secs. Pages in use: 322
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 235/2058 62/2000 DLCflexbar-PT-6b-LTLCardinality-00 1821791 m, 7693 m/sec, 1999409 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1777 secs. Pages in use: 323
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 240/2058 63/2000 DLCflexbar-PT-6b-LTLCardinality-00 1859602 m, 7562 m/sec, 2042511 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1782 secs. Pages in use: 324
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 245/2058 64/2000 DLCflexbar-PT-6b-LTLCardinality-00 1896933 m, 7466 m/sec, 2085882 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1787 secs. Pages in use: 325
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 250/2058 65/2000 DLCflexbar-PT-6b-LTLCardinality-00 1935586 m, 7730 m/sec, 2128590 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1792 secs. Pages in use: 326
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 255/2058 66/2000 DLCflexbar-PT-6b-LTLCardinality-00 1973232 m, 7529 m/sec, 2171640 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1797 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 260/2058 67/2000 DLCflexbar-PT-6b-LTLCardinality-00 2010102 m, 7374 m/sec, 2215467 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1802 secs. Pages in use: 328
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 265/2058 68/2000 DLCflexbar-PT-6b-LTLCardinality-00 2047488 m, 7477 m/sec, 2258765 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1807 secs. Pages in use: 329
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 270/2058 69/2000 DLCflexbar-PT-6b-LTLCardinality-00 2084789 m, 7460 m/sec, 2301995 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1812 secs. Pages in use: 330
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 275/2058 70/2000 DLCflexbar-PT-6b-LTLCardinality-00 2120788 m, 7199 m/sec, 2346119 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1817 secs. Pages in use: 331
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 280/2058 71/2000 DLCflexbar-PT-6b-LTLCardinality-00 2157595 m, 7361 m/sec, 2389855 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1822 secs. Pages in use: 332
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 285/2058 71/2000 DLCflexbar-PT-6b-LTLCardinality-00 2195140 m, 7509 m/sec, 2432977 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1827 secs. Pages in use: 332
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 290/2058 72/2000 DLCflexbar-PT-6b-LTLCardinality-00 2232253 m, 7422 m/sec, 2476338 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1832 secs. Pages in use: 333
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 295/2058 73/2000 DLCflexbar-PT-6b-LTLCardinality-00 2269363 m, 7422 m/sec, 2519791 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1837 secs. Pages in use: 334
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 300/2058 74/2000 DLCflexbar-PT-6b-LTLCardinality-00 2307467 m, 7620 m/sec, 2562550 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1842 secs. Pages in use: 335
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 305/2058 75/2000 DLCflexbar-PT-6b-LTLCardinality-00 2343556 m, 7217 m/sec, 2606656 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1847 secs. Pages in use: 336
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 310/2058 76/2000 DLCflexbar-PT-6b-LTLCardinality-00 2381292 m, 7547 m/sec, 2649800 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1852 secs. Pages in use: 337
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 315/2058 77/2000 DLCflexbar-PT-6b-LTLCardinality-00 2418565 m, 7454 m/sec, 2692953 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1857 secs. Pages in use: 338
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 320/2058 78/2000 DLCflexbar-PT-6b-LTLCardinality-00 2454443 m, 7175 m/sec, 2737040 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1862 secs. Pages in use: 339
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 325/2058 79/2000 DLCflexbar-PT-6b-LTLCardinality-00 2490550 m, 7221 m/sec, 2780788 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1867 secs. Pages in use: 340
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 330/2058 79/2000 DLCflexbar-PT-6b-LTLCardinality-00 2526561 m, 7202 m/sec, 2824752 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1872 secs. Pages in use: 340
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 335/2058 80/2000 DLCflexbar-PT-6b-LTLCardinality-00 2562705 m, 7228 m/sec, 2868812 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1877 secs. Pages in use: 341
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 340/2058 81/2000 DLCflexbar-PT-6b-LTLCardinality-00 2600125 m, 7484 m/sec, 2912143 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1882 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 345/2058 82/2000 DLCflexbar-PT-6b-LTLCardinality-00 2636585 m, 7292 m/sec, 2955716 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1887 secs. Pages in use: 343
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 350/2058 83/2000 DLCflexbar-PT-6b-LTLCardinality-00 2674236 m, 7530 m/sec, 2998884 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1892 secs. Pages in use: 344
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 355/2058 84/2000 DLCflexbar-PT-6b-LTLCardinality-00 2710442 m, 7241 m/sec, 3042776 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1897 secs. Pages in use: 345
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 360/2058 85/2000 DLCflexbar-PT-6b-LTLCardinality-00 2747787 m, 7469 m/sec, 3085835 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1902 secs. Pages in use: 346
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 365/2058 85/2000 DLCflexbar-PT-6b-LTLCardinality-00 2783885 m, 7219 m/sec, 3129697 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1907 secs. Pages in use: 346
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 370/2058 86/2000 DLCflexbar-PT-6b-LTLCardinality-00 2820091 m, 7241 m/sec, 3173629 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1912 secs. Pages in use: 347
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 375/2058 87/2000 DLCflexbar-PT-6b-LTLCardinality-00 2856016 m, 7185 m/sec, 3217428 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1917 secs. Pages in use: 348
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 380/2058 88/2000 DLCflexbar-PT-6b-LTLCardinality-00 2891605 m, 7117 m/sec, 3261346 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1922 secs. Pages in use: 349
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 385/2058 89/2000 DLCflexbar-PT-6b-LTLCardinality-00 2927511 m, 7181 m/sec, 3305103 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1927 secs. Pages in use: 350
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 390/2058 89/2000 DLCflexbar-PT-6b-LTLCardinality-00 2962936 m, 7085 m/sec, 3349555 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1932 secs. Pages in use: 350
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 395/2058 90/2000 DLCflexbar-PT-6b-LTLCardinality-00 2998689 m, 7150 m/sec, 3393972 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1937 secs. Pages in use: 351
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 400/2058 91/2000 DLCflexbar-PT-6b-LTLCardinality-00 3034280 m, 7118 m/sec, 3438388 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1942 secs. Pages in use: 352
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 405/2058 92/2000 DLCflexbar-PT-6b-LTLCardinality-00 3070476 m, 7239 m/sec, 3482201 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1947 secs. Pages in use: 353
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 410/2058 93/2000 DLCflexbar-PT-6b-LTLCardinality-00 3107626 m, 7430 m/sec, 3525808 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1952 secs. Pages in use: 354
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 415/2058 94/2000 DLCflexbar-PT-6b-LTLCardinality-00 3145950 m, 7664 m/sec, 3568293 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1957 secs. Pages in use: 355
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 420/2058 95/2000 DLCflexbar-PT-6b-LTLCardinality-00 3184153 m, 7640 m/sec, 3610505 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1962 secs. Pages in use: 356
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-03: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-08: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-6b-LTLCardinality-13: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-6b-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-6b-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-6b"
export BK_EXAMINATION="LTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is DLCflexbar-PT-6b, examination is LTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r115-smll-171624276300075"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-6b.tgz
mv DLCflexbar-PT-6b execution
cd execution
if [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "UpperBounds" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] || [ "LTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;