Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r115-smll-171624276300074.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is DLCflexbar-PT-6b, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r115-smll-171624276300074
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 11M
-rw-r--r-- 1 mcc users 6.4K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 65K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.5K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 51K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K May 19 07:08 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K May 19 15:42 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K May 19 07:15 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 19 18:10 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Apr 12 13:03 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 104K Apr 12 13:03 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Apr 12 13:02 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 88K Apr 12 13:02 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 22 14:37 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Apr 22 14:37 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 3 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 9.6M May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCflexbar-PT-6b-CTLFireability-2024-00
FORMULA_NAME DLCflexbar-PT-6b-CTLFireability-2024-01
FORMULA_NAME DLCflexbar-PT-6b-CTLFireability-2024-02
FORMULA_NAME DLCflexbar-PT-6b-CTLFireability-2024-03
FORMULA_NAME DLCflexbar-PT-6b-CTLFireability-2024-04
FORMULA_NAME DLCflexbar-PT-6b-CTLFireability-2024-05
FORMULA_NAME DLCflexbar-PT-6b-CTLFireability-2024-06
FORMULA_NAME DLCflexbar-PT-6b-CTLFireability-2024-07
FORMULA_NAME DLCflexbar-PT-6b-CTLFireability-2024-08
FORMULA_NAME DLCflexbar-PT-6b-CTLFireability-2024-09
FORMULA_NAME DLCflexbar-PT-6b-CTLFireability-2024-10
FORMULA_NAME DLCflexbar-PT-6b-CTLFireability-2024-11
FORMULA_NAME DLCflexbar-PT-6b-CTLFireability-2023-12
FORMULA_NAME DLCflexbar-PT-6b-CTLFireability-2023-13
FORMULA_NAME DLCflexbar-PT-6b-CTLFireability-2023-14
FORMULA_NAME DLCflexbar-PT-6b-CTLFireability-2023-15

=== Now, execution of the tool begins

BK_START 1717028233877

FORMULA DLCflexbar-PT-6b-CTLFireability-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-6b-CTLFireability-2024-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1717029352995

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains place/transition net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading formula.
[lola][I] Using XML format (--xmlformula)
[lola][I] reading XML formula
[lola][I] reading formula from CTLFireability.xml
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-01: EF 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-02: SP ACTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-06: DISJ 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-07: EF 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-09: EFAG 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2023-12: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 53 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-01: EF 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-02: SP ACTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-06: DISJ 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-07: EF 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-09: EFAG 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2023-12: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 58 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-01: EF 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-02: SP ACTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-06: DISJ 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-07: EF 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-09: EFAG 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2023-12: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 63 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-01: EF 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-02: SP ACTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-06: DISJ 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-07: EF 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-09: EFAG 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2023-12: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 68 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-01: EF 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-02: SP ACTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-06: DISJ 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-07: EF 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-09: EFAG 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2023-12: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 73 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-01: EF 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-02: SP ACTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-06: DISJ 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-07: EF 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-09: EFAG 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2023-12: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[lola][.] DLCflexbar-PT-6b-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 78 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
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[lola][I] FINISHED task # 63 (type FNDP) for DLCflexbar-PT-6b-CTLFireability-2024-01
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[lola][.] 23 CTL EXCL 184/2702 5/5 DLCflexbar-PT-6b-CTLFireability-2024-06 170047 m, 1099 m/sec, 1075593 t fired, .
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[lola][.] 23 CTL EXCL 189/192 5/5 DLCflexbar-PT-6b-CTLFireability-2024-06 176626 m, 1315 m/sec, 1117247 t fired, .
[lola][.] 53 AGEF EXCL 5/2517 1/5 DLCflexbar-PT-6b-CTLFireability-2024-09 10232 m, -53898 m/sec, 32602 t fired, .
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[lola][.] 53 AGEF EXCL 10/167 1/5 DLCflexbar-PT-6b-CTLFireability-2024-09 20692 m, 2092 m/sec, 67436 t fired, .
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[lola][.] 23 CTL EXCL 4/2507 1/5 DLCflexbar-PT-6b-CTLFireability-2024-06 3557 m, -34613 m/sec, 20996 t fired, .
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[lola][.] 23 CTL EXCL 14/2507 1/5 DLCflexbar-PT-6b-CTLFireability-2024-06 13096 m, 1004 m/sec, 81648 t fired, .
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/home/mcc/BenchKit/BenchKit_head.sh: line 23: 408 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-6b"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is DLCflexbar-PT-6b, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r115-smll-171624276300074"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-6b.tgz
mv DLCflexbar-PT-6b execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;