MCC'2024- Execution of r115-smll-171624276300060

About the Execution of LoLA for DLCflexbar-PT-5b

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
16207.359	2422845.00	3535836.00	9492.90	???????FT?F???F?	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r115-smll-171624276300060.qcow2',
Waiting for the VM to be ready (probing ssh)
........................................................
==================================
Generated by BenchKit 2-5568
Executing tool lola
Input is DLCflexbar-PT-5b, examination is LTLFireabi
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r115-smll-171624276300060
========================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 6.9M
-rw-r--r-- 1 mcc users 8.1K May 14 13:22 CTLCardinality.
-rw-r--r-- 1 mcc users 90K May 14 13:22 CTLCardinality.
-rw-r--r-- 1 mcc users 5.7K May 14 13:22 CTLFireability.
-rw-r--r-- 1 mcc users 51K May 14 13:22 CTLFireability.
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericProperti
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericProperti
-rw-r--r-- 1 mcc users 3.5K Apr 22 14:37 LTLCardinality.
-rw-r--r-- 1 mcc users 24K Apr 22 14:37 LTLCardinality.
-rw-r--r-- 1 mcc users 2.1K May 19 07:15 LTLFireability.
-rw-r--r-- 1 mcc users 17K May 19 18:10 LTLFireability.
-rw-r--r-- 1 mcc users 12K Apr 12 12:59 ReachabilityCar
-rw-r--r-- 1 mcc users 118K Apr 12 12:59 ReachabilityCar
-rw-r--r-- 1 mcc users 8.4K Apr 12 12:59 ReachabilityFir
-rw-r--r-- 1 mcc users 69K Apr 12 12:59 ReachabilityFir
-rw-r--r-- 1 mcc users 1.6K Apr 22 14:37 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Apr 22 14:37 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 3 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 6.5M May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from
FORMULA_NAME DLCflexbar-PT-5b-LTLFireability-00
FORMULA_NAME DLCflexbar-PT-5b-LTLFireability-01
FORMULA_NAME DLCflexbar-PT-5b-LTLFireability-02
FORMULA_NAME DLCflexbar-PT-5b-LTLFireability-03
FORMULA_NAME DLCflexbar-PT-5b-LTLFireability-04
FORMULA_NAME DLCflexbar-PT-5b-LTLFireability-05
FORMULA_NAME DLCflexbar-PT-5b-LTLFireability-06
FORMULA_NAME DLCflexbar-PT-5b-LTLFireability-07
FORMULA_NAME DLCflexbar-PT-5b-LTLFireability-08
FORMULA_NAME DLCflexbar-PT-5b-LTLFireability-09
FORMULA_NAME DLCflexbar-PT-5b-LTLFireability-10
FORMULA_NAME DLCflexbar-PT-5b-LTLFireability-11
FORMULA_NAME DLCflexbar-PT-5b-LTLFireability-12
FORMULA_NAME DLCflexbar-PT-5b-LTLFireability-13
FORMULA_NAME DLCflexbar-PT-5b-LTLFireability-14
FORMULA_NAME DLCflexbar-PT-5b-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1717023315297

FORMULA DLCflexbar-PT-5b-LTLFireability-10
FORMULA DLCflexbar-PT-5b-LTLFireability-08
FORMULA DLCflexbar-PT-5b-LTLFireability-14
FORMULA DLCflexbar-PT-5b-LTLFireability-07

BK_STOP 1717025738142

--------------------
content from stderr:

[[35mlola[0m][I] LoLA will run for 3600 seconds
[[35mlola[0m][W] [1m[33munknown unit in memory
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlne
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition
[[35mlola[0m][I] closed [1m[34mnet[0m file
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlfor
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-03:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-07:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-10:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-11:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-12:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-14:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 11 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-03:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-07:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-10:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-11:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-12:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-14:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 16 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-03:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-07:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-10:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-11:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-12:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-14:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 21 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-03:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-07:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-10:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-11:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-12:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-14:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 26 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-03:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-07:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-10:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-11:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-12:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-14:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 31 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-03:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-07:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-10:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-11:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-12:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-14:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 36 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-03:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-07:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-10:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-11:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-12:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-14:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 41 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-03:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-07:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-10:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-11:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-12:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-14:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 46 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-03:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-07:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-10:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-11:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-12:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-14:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 51 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-03:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-07:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-10:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-11:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-12:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-14:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 56 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-03:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-07:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-10:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-11:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-12:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-14:
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 61 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible:
[[35mlola[0m][I] Rule S: 0 transitions removed,0
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
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[[35mlola[0m][I] time limit : 212 sec
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[[35mlola[0m][I] LAUNCH task # 64 (type EQUN)
[[35mlola[0m][I] time limit : 32000000 sec
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[[35mlola[0m][I] time limit : 261 sec
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[[35mlola[0m][I] result : false
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................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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=================================== lity ============= txt xml txt xml esDefinition.xml esVerdict.xml txt xml txt xml dinality.txt dinality.xml eability.txt eability.xml (invocation template) text file) FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT at most ([1m[36m--timelimit[0m) specification: using default[0m [4m[34mmodel.pnml[0m t[0m) net [4m[34mmodel.pnml[0m mula[0m) from [4m[34mLTLFireability.xml[0m CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 places removed CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 for 24 DLCflexbar-PT-5b-LTLFireability-08 for 34 DLCflexbar-PT-5b-LTLFireability-10 for DLCflexbar-PT-5b-LTLFireability-10 for DLCflexbar-PT-5b-LTLFireability-08 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 for 24 DLCflexbar-PT-5b-LTLFireability-08 for 50 DLCflexbar-PT-5b-LTLFireability-14 for DLCflexbar-PT-5b-LTLFireability-08 1 0 1 for 50 DLCflexbar-PT-5b-LTLFireability-14 for DLCflexbar-PT-5b-LTLFireability-14 912 912 1 1 for DLCflexbar-PT-5b-LTLFireability-14 (obsolete) for 21 DLCflexbar-PT-5b-LTLFireability-07 for DLCflexbar-PT-5b-LTLFireability-07 911 911 0 1 for 18 DLCflexbar-PT-5b-LTLFireability-06 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 1179 m, 235 m/sec, 1447 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 4078 m, 579 m/sec, 10018 t fired, . Pages in use: 1 16 for DLCflexbar-PT-5b-LTLFireability-14 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 6867 m, 557 m/sec, 18027 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 10114 m, 649 m/sec, 27492 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 13326 m, 642 m/sec, 37176 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 16203 m, 575 m/sec, 45401 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 19451 m, 649 m/sec, 54950 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 22335 m, 576 m/sec, 63325 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 25405 m, 614 m/sec, 72080 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 27258 m, 370 m/sec, 77329 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 27720 m, 92 m/sec, 78299 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 28107 m, 77 m/sec, 79121 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 28464 m, 71 m/sec, 79871 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 28811 m, 69 m/sec, 80605 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 29222 m, 82 m/sec, 81505 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 29583 m, 72 m/sec, 82273 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 29995 m, 82 m/sec, 83173 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 30400 m, 81 m/sec, 84054 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 30789 m, 77 m/sec, 84898 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 31186 m, 79 m/sec, 85773 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 31549 m, 72 m/sec, 86542 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 31926 m, 75 m/sec, 87339 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 32254 m, 65 m/sec, 88022 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 32617 m, 72 m/sec, 88808 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 32962 m, 69 m/sec, 89546 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 33308 m, 69 m/sec, 90284 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 33647 m, 67 m/sec, 90992 t fired, . Pages in use: 1 16 [status_logger] string pointer is null CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 34003 m, 71 m/sec, 91749 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 34425 m, 84 m/sec, 92653 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 34882 m, 91 m/sec, 93649 t fired, . Pages in use: 1 16 [status_logger] string pointer is null CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 35322 m, 88 m/sec, 94571 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 35891 m, 113 m/sec, 95798 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 36424 m, 106 m/sec, 96912 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 36979 m, 111 m/sec, 98111 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 37628 m, 129 m/sec, 99508 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 38215 m, 117 m/sec, 100762 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 38735 m, 104 m/sec, 101884 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 39251 m, 103 m/sec, 102975 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 39774 m, 104 m/sec, 104096 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 40314 m, 108 m/sec, 105236 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 40879 m, 113 m/sec, 106461 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 41384 m, 101 m/sec, 107543 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 41887 m, 100 m/sec, 108622 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 42337 m, 90 m/sec, 109570 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 42827 m, 98 m/sec, 110604 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 43351 m, 104 m/sec, 111738 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 43816 m, 93 m/sec, 112710 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 44319 m, 100 m/sec, 113769 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 45138 m, 163 m/sec, 115545 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 46270 m, 226 m/sec, 117989 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-5b-LTLFireability-06 47392 m, 224 m/sec, 120372 t fired, . Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 2/2000 DLCflexbar-PT-5b-LTLFireability-06 48533 m, 228 m/sec, 122808 t fired, . Pages in use: 2 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 2/2000 DLCflexbar-PT-5b-LTLFireability-06 49699 m, 233 m/sec, 125285 t fired, . Pages in use: 2 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 2/2000 DLCflexbar-PT-5b-LTLFireability-06 50922 m, 244 m/sec, 127920 t fired, . Pages in use: 2 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 2/2000 DLCflexbar-PT-5b-LTLFireability-06 52058 m, 227 m/sec, 130318 t fired, . Pages in use: 2 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 2/2000 DLCflexbar-PT-5b-LTLFireability-06 53216 m, 231 m/sec, 132799 t fired, . Pages in use: 2 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 2/2000 DLCflexbar-PT-5b-LTLFireability-06 54427 m, 242 m/sec, 135413 t fired, . Pages in use: 2 16 for DLCflexbar-PT-5b-LTLFireability-06 (local timeout) CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 1 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 2 16 for 47 DLCflexbar-PT-5b-LTLFireability-13 for 18 DLCflexbar-PT-5b-LTLFireability-06 for DLCflexbar-PT-5b-LTLFireability-13 54 54 0 1 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/5 DLCflexbar-PT-5b-LTLFireability-06 14051 m, -8075 m/sec, 39331 t fired, . Pages in use: 5 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/5 DLCflexbar-PT-5b-LTLFireability-06 27040 m, 2597 m/sec, 76945 t fired, . Pages in use: 5 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/5 DLCflexbar-PT-5b-LTLFireability-06 28415 m, 275 m/sec, 79769 t fired, . Pages in use: 5 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/5 DLCflexbar-PT-5b-LTLFireability-06 29679 m, 252 m/sec, 82481 t fired, . Pages in use: 5 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/5 DLCflexbar-PT-5b-LTLFireability-06 30978 m, 259 m/sec, 85310 t fired, . Pages in use: 5 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/5 DLCflexbar-PT-5b-LTLFireability-06 32178 m, 240 m/sec, 87869 t fired, . Pages in use: 5 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/5 DLCflexbar-PT-5b-LTLFireability-06 33377 m, 239 m/sec, 90423 t fired, . Pages in use: 5 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/5 DLCflexbar-PT-5b-LTLFireability-06 34562 m, 237 m/sec, 92946 t fired, . Pages in use: 5 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/5 DLCflexbar-PT-5b-LTLFireability-06 35778 m, 243 m/sec, 95555 t fired, . Pages in use: 5 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/5 DLCflexbar-PT-5b-LTLFireability-06 36938 m, 232 m/sec, 98019 t fired, . Pages in use: 5 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/5 DLCflexbar-PT-5b-LTLFireability-06 38120 m, 236 m/sec, 100562 t fired, . Pages in use: 5 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/5 DLCflexbar-PT-5b-LTLFireability-06 39269 m, 229 m/sec, 103018 t fired, . Pages in use: 5 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/5 DLCflexbar-PT-5b-LTLFireability-06 40428 m, 231 m/sec, 105496 t fired, . Pages in use: 5 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/5 DLCflexbar-PT-5b-LTLFireability-06 41569 m, 228 m/sec, 107929 t fired, . Pages in use: 5 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/5 DLCflexbar-PT-5b-LTLFireability-06 42719 m, 230 m/sec, 110375 t fired, . Pages in use: 5 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/5 DLCflexbar-PT-5b-LTLFireability-06 43888 m, 233 m/sec, 112861 t fired, . Pages in use: 5 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/5 DLCflexbar-PT-5b-LTLFireability-06 45069 m, 236 m/sec, 115403 t fired, . Pages in use: 5 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/5 DLCflexbar-PT-5b-LTLFireability-06 46264 m, 239 m/sec, 117983 t fired, . Pages in use: 5 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/5 DLCflexbar-PT-5b-LTLFireability-06 47405 m, 228 m/sec, 120396 t fired, . Pages in use: 5 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 2/5 DLCflexbar-PT-5b-LTLFireability-06 48559 m, 230 m/sec, 122861 t fired, . Pages in use: 6 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 2/5 DLCflexbar-PT-5b-LTLFireability-06 49730 m, 234 m/sec, 125345 t fired, . Pages in use: 6 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 2/5 DLCflexbar-PT-5b-LTLFireability-06 50954 m, 244 m/sec, 127989 t fired, . Pages in use: 7 16 for DLCflexbar-PT-5b-LTLFireability-06 51015 128115 110 2 for 44 DLCflexbar-PT-5b-LTLFireability-12 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 2/2000 DLCflexbar-PT-5b-LTLFireability-12 53307 m, 10661 m/sec, 57964 t fired, . Pages in use: 7 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 3/2000 DLCflexbar-PT-5b-LTLFireability-12 107992 m, 10937 m/sec, 117495 t fired, . Pages in use: 8 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 4/2000 DLCflexbar-PT-5b-LTLFireability-12 162808 m, 10963 m/sec, 177056 t fired, . Pages in use: 9 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 6/2000 DLCflexbar-PT-5b-LTLFireability-12 217315 m, 10901 m/sec, 236263 t fired, . Pages in use: 11 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 7/2000 DLCflexbar-PT-5b-LTLFireability-12 272502 m, 11037 m/sec, 296206 t fired, . Pages in use: 12 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 8/2000 DLCflexbar-PT-5b-LTLFireability-12 327734 m, 11046 m/sec, 356189 t fired, . Pages in use: 13 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 9/2000 DLCflexbar-PT-5b-LTLFireability-12 383105 m, 11074 m/sec, 416322 t fired, . Pages in use: 14 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 10/2000 DLCflexbar-PT-5b-LTLFireability-12 438668 m, 11112 m/sec, 476660 t fired, . Pages in use: 15 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 12/2000 DLCflexbar-PT-5b-LTLFireability-12 494154 m, 11097 m/sec, 536916 t fired, . Pages in use: 17 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 13/2000 DLCflexbar-PT-5b-LTLFireability-12 549267 m, 11022 m/sec, 596763 t fired, . Pages in use: 18 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 14/2000 DLCflexbar-PT-5b-LTLFireability-12 604253 m, 10997 m/sec, 656525 t fired, . Pages in use: 19 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 15/2000 DLCflexbar-PT-5b-LTLFireability-12 659051 m, 10959 m/sec, 716059 t fired, . Pages in use: 20 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 17/2000 DLCflexbar-PT-5b-LTLFireability-12 713572 m, 10904 m/sec, 775278 t fired, . Pages in use: 22 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 18/2000 DLCflexbar-PT-5b-LTLFireability-12 768560 m, 10997 m/sec, 834995 t fired, . Pages in use: 23 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 19/2000 DLCflexbar-PT-5b-LTLFireability-12 824009 m, 11089 m/sec, 895230 t fired, . Pages in use: 24 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 20/2000 DLCflexbar-PT-5b-LTLFireability-12 879527 m, 11103 m/sec, 955543 t fired, . Pages in use: 25 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 22/2000 DLCflexbar-PT-5b-LTLFireability-12 935075 m, 11109 m/sec, 1015873 t fired, . Pages in use: 27 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 23/2000 DLCflexbar-PT-5b-LTLFireability-12 990111 m, 11007 m/sec, 1075693 t fired, . Pages in use: 28 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 25/2000 DLCflexbar-PT-5b-LTLFireability-12 1044749 m, 10927 m/sec, 1134685 t fired, . Pages in use: 30 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 29/2000 DLCflexbar-PT-5b-LTLFireability-12 1099322 m, 10914 m/sec, 1193553 t fired, . Pages in use: 34 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 32/2000 DLCflexbar-PT-5b-LTLFireability-12 1150479 m, 10231 m/sec, 1254535 t fired, . Pages in use: 37 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 35/2000 DLCflexbar-PT-5b-LTLFireability-12 1201534 m, 10211 m/sec, 1315132 t fired, . Pages in use: 40 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 38/2000 DLCflexbar-PT-5b-LTLFireability-12 1250745 m, 9842 m/sec, 1376762 t fired, . Pages in use: 43 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 42/2000 DLCflexbar-PT-5b-LTLFireability-12 1299991 m, 9849 m/sec, 1438641 t fired, . Pages in use: 47 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 46/2000 DLCflexbar-PT-5b-LTLFireability-12 1350809 m, 10163 m/sec, 1499660 t fired, . Pages in use: 51 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 50/2000 DLCflexbar-PT-5b-LTLFireability-12 1399832 m, 9804 m/sec, 1561640 t fired, . Pages in use: 55 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 53/2000 DLCflexbar-PT-5b-LTLFireability-12 1449992 m, 10032 m/sec, 1623394 t fired, . Pages in use: 58 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 57/2000 DLCflexbar-PT-5b-LTLFireability-12 1500635 m, 10128 m/sec, 1685024 t fired, . Pages in use: 62 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 61/2000 DLCflexbar-PT-5b-LTLFireability-12 1549756 m, 9824 m/sec, 1747711 t fired, . Pages in use: 66 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 65/2000 DLCflexbar-PT-5b-LTLFireability-12 1601073 m, 10263 m/sec, 1809000 t fired, . Pages in use: 70 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 69/2000 DLCflexbar-PT-5b-LTLFireability-12 1650876 m, 9960 m/sec, 1870822 t fired, . Pages in use: 74 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 72/2000 DLCflexbar-PT-5b-LTLFireability-12 1700231 m, 9871 m/sec, 1932872 t fired, . Pages in use: 77 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 76/2000 DLCflexbar-PT-5b-LTLFireability-12 1751398 m, 10233 m/sec, 1993923 t fired, . Pages in use: 81 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 80/2000 DLCflexbar-PT-5b-LTLFireability-12 1800750 m, 9870 m/sec, 2055911 t fired, . Pages in use: 85 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 84/2000 DLCflexbar-PT-5b-LTLFireability-12 1850579 m, 9965 m/sec, 2117302 t fired, . Pages in use: 89 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 88/2000 DLCflexbar-PT-5b-LTLFireability-12 1901045 m, 10093 m/sec, 2178203 t fired, . Pages in use: 93 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 91/2000 DLCflexbar-PT-5b-LTLFireability-12 1951179 m, 10026 m/sec, 2239144 t fired, . Pages in use: 96 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 94/2000 DLCflexbar-PT-5b-LTLFireability-12 2001307 m, 10025 m/sec, 2300210 t fired, . Pages in use: 99 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 98/2000 DLCflexbar-PT-5b-LTLFireability-12 2050091 m, 9756 m/sec, 2362065 t fired, . Pages in use: 103 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 102/2000 DLCflexbar-PT-5b-LTLFireability-12 2100622 m, 10106 m/sec, 2422597 t fired, . Pages in use: 107 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 105/2000 DLCflexbar-PT-5b-LTLFireability-12 2149129 m, 9701 m/sec, 2484023 t fired, . Pages in use: 110 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 109/2000 DLCflexbar-PT-5b-LTLFireability-12 2198368 m, 9847 m/sec, 2544796 t fired, . Pages in use: 114 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 112/2000 DLCflexbar-PT-5b-LTLFireability-12 2248097 m, 9945 m/sec, 2605350 t fired, . Pages in use: 117 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 116/2000 DLCflexbar-PT-5b-LTLFireability-12 2297045 m, 9789 m/sec, 2666504 t fired, . Pages in use: 121 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 120/2000 DLCflexbar-PT-5b-LTLFireability-12 2347078 m, 10006 m/sec, 2728070 t fired, . Pages in use: 125 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 124/2000 DLCflexbar-PT-5b-LTLFireability-12 2397381 m, 10060 m/sec, 2788975 t fired, . Pages in use: 129 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 127/2000 DLCflexbar-PT-5b-LTLFireability-12 2445950 m, 9713 m/sec, 2849549 t fired, . Pages in use: 132 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 131/2000 DLCflexbar-PT-5b-LTLFireability-12 2494916 m, 9793 m/sec, 2909744 t fired, . Pages in use: 136 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 134/2000 DLCflexbar-PT-5b-LTLFireability-12 2543743 m, 9765 m/sec, 2969850 t fired, . Pages in use: 139 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 136/2000 DLCflexbar-PT-5b-LTLFireability-12 2591272 m, 9505 m/sec, 3030198 t fired, . Pages in use: 141 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 138/2000 DLCflexbar-PT-5b-LTLFireability-12 2641047 m, 9955 m/sec, 3089640 t fired, . Pages in use: 143 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 142/2000 DLCflexbar-PT-5b-LTLFireability-12 2690698 m, 9930 m/sec, 3149952 t fired, . Pages in use: 147 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 146/2000 DLCflexbar-PT-5b-LTLFireability-12 2740674 m, 9995 m/sec, 3210460 t fired, . Pages in use: 151 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 150/2000 DLCflexbar-PT-5b-LTLFireability-12 2789703 m, 9805 m/sec, 3271433 t fired, . Pages in use: 155 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 154/2000 DLCflexbar-PT-5b-LTLFireability-12 2839664 m, 9992 m/sec, 3331846 t fired, . Pages in use: 159 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 156/2000 DLCflexbar-PT-5b-LTLFireability-12 2889134 m, 9894 m/sec, 3392234 t fired, . Pages in use: 161 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 159/2000 DLCflexbar-PT-5b-LTLFireability-12 2937186 m, 9610 m/sec, 3453327 t fired, . Pages in use: 164 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 163/2000 DLCflexbar-PT-5b-LTLFireability-12 2987264 m, 10015 m/sec, 3513325 t fired, . Pages in use: 168 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 167/2000 DLCflexbar-PT-5b-LTLFireability-12 3035479 m, 9643 m/sec, 3574369 t fired, . Pages in use: 172 16 for DLCflexbar-PT-5b-LTLFireability-12 (local timeout) CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 1 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 175 16 for 41 DLCflexbar-PT-5b-LTLFireability-11 for 44 DLCflexbar-PT-5b-LTLFireability-12 for DLCflexbar-PT-5b-LTLFireability-11 1 0 1 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 2/5 DLCflexbar-PT-5b-LTLFireability-12 55384 m, -596019 m/sec, 60223 t fired, . Pages in use: 177 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 3/5 DLCflexbar-PT-5b-LTLFireability-12 110695 m, 11062 m/sec, 120431 t fired, . Pages in use: 178 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 4/5 DLCflexbar-PT-5b-LTLFireability-12 165603 m, 10981 m/sec, 180087 t fired, . Pages in use: 179 16 for DLCflexbar-PT-5b-LTLFireability-12 (memory limit exceeded) CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 180 16 for 31 DLCflexbar-PT-5b-LTLFireability-09 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 2/2000 DLCflexbar-PT-5b-LTLFireability-09 55593 m, 11118 m/sec, 60453 t fired, . Pages in use: 180 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 3/2000 DLCflexbar-PT-5b-LTLFireability-09 111162 m, 11113 m/sec, 120942 t fired, . Pages in use: 180 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 4/2000 DLCflexbar-PT-5b-LTLFireability-09 166545 m, 11076 m/sec, 181235 t fired, . Pages in use: 180 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 6/2000 DLCflexbar-PT-5b-LTLFireability-09 221579 m, 11006 m/sec, 241167 t fired, . Pages in use: 181 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 7/2000 DLCflexbar-PT-5b-LTLFireability-09 277260 m, 11136 m/sec, 301793 t fired, . Pages in use: 182 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 8/2000 DLCflexbar-PT-5b-LTLFireability-09 333088 m, 11165 m/sec, 362559 t fired, . Pages in use: 183 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 9/2000 DLCflexbar-PT-5b-LTLFireability-09 389018 m, 11186 m/sec, 423454 t fired, . Pages in use: 184 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 10/2000 DLCflexbar-PT-5b-LTLFireability-09 445279 m, 11252 m/sec, 484704 t fired, . Pages in use: 185 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 12/2000 DLCflexbar-PT-5b-LTLFireability-09 501120 m, 11168 m/sec, 545488 t fired, . Pages in use: 187 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 13/2000 DLCflexbar-PT-5b-LTLFireability-09 556887 m, 11153 m/sec, 606240 t fired, . Pages in use: 188 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 14/2000 DLCflexbar-PT-5b-LTLFireability-09 612509 m, 11124 m/sec, 666807 t fired, . Pages in use: 189 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 15/2000 DLCflexbar-PT-5b-LTLFireability-09 667479 m, 10994 m/sec, 726661 t fired, . Pages in use: 190 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 16/2000 DLCflexbar-PT-5b-LTLFireability-09 722711 m, 11046 m/sec, 786802 t fired, . Pages in use: 191 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 17/2000 DLCflexbar-PT-5b-LTLFireability-09 778790 m, 11215 m/sec, 847862 t fired, . Pages in use: 192 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 19/2000 DLCflexbar-PT-5b-LTLFireability-09 834926 m, 11227 m/sec, 908996 t fired, . Pages in use: 194 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 20/2000 DLCflexbar-PT-5b-LTLFireability-09 891328 m, 11280 m/sec, 970408 t fired, . Pages in use: 195 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 21/2000 DLCflexbar-PT-5b-LTLFireability-09 947401 m, 11214 m/sec, 1031500 t fired, . Pages in use: 196 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 23/2000 DLCflexbar-PT-5b-LTLFireability-09 1002545 m, 11028 m/sec, 1091861 t fired, . Pages in use: 198 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 27/2000 DLCflexbar-PT-5b-LTLFireability-09 1056221 m, 10735 m/sec, 1152077 t fired, . Pages in use: 202 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 30/2000 DLCflexbar-PT-5b-LTLFireability-09 1109442 m, 10644 m/sec, 1212406 t fired, . Pages in use: 205 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 34/2000 DLCflexbar-PT-5b-LTLFireability-09 1162558 m, 10623 m/sec, 1272626 t fired, . Pages in use: 209 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 37/2000 DLCflexbar-PT-5b-LTLFireability-09 1214455 m, 10379 m/sec, 1333781 t fired, . Pages in use: 212 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 39/2000 DLCflexbar-PT-5b-LTLFireability-09 1267590 m, 10627 m/sec, 1393666 t fired, . Pages in use: 214 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 41/2000 DLCflexbar-PT-5b-LTLFireability-09 1321047 m, 10691 m/sec, 1453565 t fired, . Pages in use: 216 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 45/2000 DLCflexbar-PT-5b-LTLFireability-09 1374647 m, 10720 m/sec, 1513703 t fired, . Pages in use: 220 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 49/2000 DLCflexbar-PT-5b-LTLFireability-09 1424515 m, 9973 m/sec, 1576350 t fired, . Pages in use: 224 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 53/2000 DLCflexbar-PT-5b-LTLFireability-09 1475434 m, 10183 m/sec, 1637730 t fired, . Pages in use: 228 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 57/2000 DLCflexbar-PT-5b-LTLFireability-09 1523617 m, 9636 m/sec, 1700722 t fired, . Pages in use: 232 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 59/2000 DLCflexbar-PT-5b-LTLFireability-09 1575863 m, 10449 m/sec, 1761834 t fired, . Pages in use: 234 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 61/2000 DLCflexbar-PT-5b-LTLFireability-09 1629152 m, 10657 m/sec, 1822127 t fired, . Pages in use: 236 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 63/2000 DLCflexbar-PT-5b-LTLFireability-09 1682144 m, 10598 m/sec, 1882217 t fired, . Pages in use: 238 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 65/2000 DLCflexbar-PT-5b-LTLFireability-09 1734835 m, 10538 m/sec, 1941790 t fired, . Pages in use: 240 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 67/2000 DLCflexbar-PT-5b-LTLFireability-09 1787263 m, 10485 m/sec, 2001122 t fired, . Pages in use: 242 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 68/2000 DLCflexbar-PT-5b-LTLFireability-09 1839677 m, 10482 m/sec, 2060453 t fired, . Pages in use: 243 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 70/2000 DLCflexbar-PT-5b-LTLFireability-09 1892657 m, 10596 m/sec, 2120318 t fired, . Pages in use: 245 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 72/2000 DLCflexbar-PT-5b-LTLFireability-09 1945793 m, 10627 m/sec, 2180389 t fired, . Pages in use: 247 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 74/2000 DLCflexbar-PT-5b-LTLFireability-09 1998958 m, 10633 m/sec, 2240454 t fired, . Pages in use: 249 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 76/2000 DLCflexbar-PT-5b-LTLFireability-09 2051778 m, 10564 m/sec, 2300225 t fired, . Pages in use: 251 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 78/2000 DLCflexbar-PT-5b-LTLFireability-09 2104715 m, 10587 m/sec, 2360112 t fired, . Pages in use: 253 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 79/2000 DLCflexbar-PT-5b-LTLFireability-09 2158012 m, 10659 m/sec, 2420295 t fired, . Pages in use: 254 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 81/2000 DLCflexbar-PT-5b-LTLFireability-09 2211412 m, 10680 m/sec, 2480743 t fired, . Pages in use: 256 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 83/2000 DLCflexbar-PT-5b-LTLFireability-09 2264066 m, 10530 m/sec, 2540376 t fired, . Pages in use: 258 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 84/2000 DLCflexbar-PT-5b-LTLFireability-09 2316796 m, 10546 m/sec, 2600133 t fired, . Pages in use: 259 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 86/2000 DLCflexbar-PT-5b-LTLFireability-09 2369641 m, 10569 m/sec, 2659760 t fired, . Pages in use: 261 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 88/2000 DLCflexbar-PT-5b-LTLFireability-09 2422148 m, 10501 m/sec, 2719250 t fired, . Pages in use: 263 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 90/2000 DLCflexbar-PT-5b-LTLFireability-09 2474933 m, 10557 m/sec, 2778814 t fired, . Pages in use: 265 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 92/2000 DLCflexbar-PT-5b-LTLFireability-09 2527319 m, 10477 m/sec, 2838140 t fired, . Pages in use: 267 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 94/2000 DLCflexbar-PT-5b-LTLFireability-09 2579627 m, 10461 m/sec, 2897267 t fired, . Pages in use: 269 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 96/2000 DLCflexbar-PT-5b-LTLFireability-09 2631877 m, 10450 m/sec, 2956372 t fired, . Pages in use: 271 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 98/2000 DLCflexbar-PT-5b-LTLFireability-09 2684083 m, 10441 m/sec, 3015540 t fired, . Pages in use: 273 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 99/2000 DLCflexbar-PT-5b-LTLFireability-09 2736439 m, 10471 m/sec, 3074736 t fired, . Pages in use: 274 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 101/2000 DLCflexbar-PT-5b-LTLFireability-09 2788616 m, 10435 m/sec, 3133800 t fired, . Pages in use: 276 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 102/2000 DLCflexbar-PT-5b-LTLFireability-09 2840634 m, 10403 m/sec, 3192738 t fired, . Pages in use: 277 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 104/2000 DLCflexbar-PT-5b-LTLFireability-09 2892461 m, 10365 m/sec, 3251297 t fired, . Pages in use: 279 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 105/2000 DLCflexbar-PT-5b-LTLFireability-09 2944324 m, 10372 m/sec, 3310113 t fired, . Pages in use: 280 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 107/2000 DLCflexbar-PT-5b-LTLFireability-09 2996150 m, 10365 m/sec, 3368720 t fired, . Pages in use: 282 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 108/2000 DLCflexbar-PT-5b-LTLFireability-09 3047923 m, 10354 m/sec, 3427280 t fired, . Pages in use: 283 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 109/2000 DLCflexbar-PT-5b-LTLFireability-09 3099561 m, 10327 m/sec, 3485823 t fired, . Pages in use: 284 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 111/2000 DLCflexbar-PT-5b-LTLFireability-09 3151082 m, 10304 m/sec, 3544071 t fired, . Pages in use: 286 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 112/2000 DLCflexbar-PT-5b-LTLFireability-09 3203830 m, 10549 m/sec, 3603764 t fired, . Pages in use: 287 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 114/2000 DLCflexbar-PT-5b-LTLFireability-09 3257258 m, 10685 m/sec, 3664246 t fired, . Pages in use: 289 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 115/2000 DLCflexbar-PT-5b-LTLFireability-09 3310802 m, 10708 m/sec, 3724748 t fired, . Pages in use: 290 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 117/2000 DLCflexbar-PT-5b-LTLFireability-09 3364128 m, 10665 m/sec, 3785154 t fired, . Pages in use: 292 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 118/2000 DLCflexbar-PT-5b-LTLFireability-09 3417192 m, 10612 m/sec, 3845224 t fired, . Pages in use: 293 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 119/2000 DLCflexbar-PT-5b-LTLFireability-09 3470140 m, 10589 m/sec, 3905149 t fired, . Pages in use: 294 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 121/2000 DLCflexbar-PT-5b-LTLFireability-09 3522769 m, 10525 m/sec, 3964785 t fired, . Pages in use: 296 16 for DLCflexbar-PT-5b-LTLFireability-09 (local timeout) CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 1 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 297 16 for 15 DLCflexbar-PT-5b-LTLFireability-05 for 31 DLCflexbar-PT-5b-LTLFireability-09 for DLCflexbar-PT-5b-LTLFireability-05 4 3 0 1 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 2/5 DLCflexbar-PT-5b-LTLFireability-09 54967 m, -693560 m/sec, 59769 t fired, . Pages in use: 299 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 3/5 DLCflexbar-PT-5b-LTLFireability-09 109942 m, 10995 m/sec, 119619 t fired, . Pages in use: 300 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 4/5 DLCflexbar-PT-5b-LTLFireability-09 164837 m, 10979 m/sec, 179374 t fired, . Pages in use: 301 16 for DLCflexbar-PT-5b-LTLFireability-09 (memory limit exceeded) CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 302 16 for 12 DLCflexbar-PT-5b-LTLFireability-04 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 2/2000 DLCflexbar-PT-5b-LTLFireability-04 55526 m, 11105 m/sec, 60229 t fired, . Pages in use: 302 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 2/2000 DLCflexbar-PT-5b-LTLFireability-04 110729 m, 11040 m/sec, 120405 t fired, . Pages in use: 302 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 3/2000 DLCflexbar-PT-5b-LTLFireability-04 166062 m, 11066 m/sec, 180632 t fired, . Pages in use: 302 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 4/2000 DLCflexbar-PT-5b-LTLFireability-04 221716 m, 11130 m/sec, 241214 t fired, . Pages in use: 302 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 5/2000 DLCflexbar-PT-5b-LTLFireability-04 277231 m, 11103 m/sec, 301667 t fired, . Pages in use: 302 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 6/2000 DLCflexbar-PT-5b-LTLFireability-04 332358 m, 11025 m/sec, 361669 t fired, . Pages in use: 303 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 6/2000 DLCflexbar-PT-5b-LTLFireability-04 387392 m, 11006 m/sec, 421608 t fired, . Pages in use: 303 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 7/2000 DLCflexbar-PT-5b-LTLFireability-04 442621 m, 11045 m/sec, 481746 t fired, . Pages in use: 304 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 8/2000 DLCflexbar-PT-5b-LTLFireability-04 498598 m, 11195 m/sec, 542689 t fired, . Pages in use: 305 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 9/2000 DLCflexbar-PT-5b-LTLFireability-04 554650 m, 11210 m/sec, 603726 t fired, . Pages in use: 306 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 9/2000 DLCflexbar-PT-5b-LTLFireability-04 610680 m, 11206 m/sec, 664716 t fired, . Pages in use: 306 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 10/2000 DLCflexbar-PT-5b-LTLFireability-04 666343 m, 11132 m/sec, 725303 t fired, . Pages in use: 307 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 11/2000 DLCflexbar-PT-5b-LTLFireability-04 722441 m, 11219 m/sec, 786385 t fired, . Pages in use: 308 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 12/2000 DLCflexbar-PT-5b-LTLFireability-04 778654 m, 11242 m/sec, 847588 t fired, . Pages in use: 309 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 12/2000 DLCflexbar-PT-5b-LTLFireability-04 834870 m, 11243 m/sec, 908795 t fired, . Pages in use: 309 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 13/2000 DLCflexbar-PT-5b-LTLFireability-04 891143 m, 11254 m/sec, 970045 t fired, . Pages in use: 310 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 14/2000 DLCflexbar-PT-5b-LTLFireability-04 947338 m, 11239 m/sec, 1031218 t fired, . Pages in use: 311 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 15/2000 DLCflexbar-PT-5b-LTLFireability-04 1003321 m, 11196 m/sec, 1092169 t fired, . Pages in use: 312 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 16/2000 DLCflexbar-PT-5b-LTLFireability-04 1058977 m, 11131 m/sec, 1152735 t fired, . Pages in use: 313 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 16/2000 DLCflexbar-PT-5b-LTLFireability-04 1114649 m, 11134 m/sec, 1213433 t fired, . Pages in use: 313 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 17/2000 DLCflexbar-PT-5b-LTLFireability-04 1170345 m, 11139 m/sec, 1274063 t fired, . Pages in use: 314 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 18/2000 DLCflexbar-PT-5b-LTLFireability-04 1225859 m, 11102 m/sec, 1334527 t fired, . Pages in use: 315 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 19/2000 DLCflexbar-PT-5b-LTLFireability-04 1281169 m, 11062 m/sec, 1394766 t fired, . Pages in use: 316 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 19/2000 DLCflexbar-PT-5b-LTLFireability-04 1336303 m, 11026 m/sec, 1454788 t fired, . Pages in use: 316 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 20/2000 DLCflexbar-PT-5b-LTLFireability-04 1391319 m, 11003 m/sec, 1514689 t fired, . Pages in use: 317 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 21/2000 DLCflexbar-PT-5b-LTLFireability-04 1446594 m, 11055 m/sec, 1574892 t fired, . Pages in use: 318 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 22/2000 DLCflexbar-PT-5b-LTLFireability-04 1502212 m, 11123 m/sec, 1635450 t fired, . Pages in use: 319 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 22/2000 DLCflexbar-PT-5b-LTLFireability-04 1557919 m, 11141 m/sec, 1696091 t fired, . Pages in use: 319 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 23/2000 DLCflexbar-PT-5b-LTLFireability-04 1613551 m, 11126 m/sec, 1756687 t fired, . Pages in use: 320 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 24/2000 DLCflexbar-PT-5b-LTLFireability-04 1669415 m, 11172 m/sec, 1817505 t fired, . Pages in use: 321 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 25/2000 DLCflexbar-PT-5b-LTLFireability-04 1725524 m, 11221 m/sec, 1878607 t fired, . Pages in use: 322 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 26/2000 DLCflexbar-PT-5b-LTLFireability-04 1781586 m, 11212 m/sec, 1939661 t fired, . Pages in use: 323 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 27/2000 DLCflexbar-PT-5b-LTLFireability-04 1837572 m, 11197 m/sec, 2000624 t fired, . Pages in use: 324 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 28/2000 DLCflexbar-PT-5b-LTLFireability-04 1893200 m, 11125 m/sec, 2061275 t fired, . Pages in use: 325 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 28/2000 DLCflexbar-PT-5b-LTLFireability-04 1948544 m, 11068 m/sec, 2121548 t fired, . Pages in use: 325 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 30/2000 DLCflexbar-PT-5b-LTLFireability-04 2003109 m, 10913 m/sec, 2181337 t fired, . Pages in use: 327 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 32/2000 DLCflexbar-PT-5b-LTLFireability-04 2056409 m, 10660 m/sec, 2241201 t fired, . Pages in use: 329 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 33/2000 DLCflexbar-PT-5b-LTLFireability-04 2109733 m, 10664 m/sec, 2301136 t fired, . Pages in use: 330 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 36/2000 DLCflexbar-PT-5b-LTLFireability-04 2162591 m, 10571 m/sec, 2361424 t fired, . Pages in use: 333 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 37/2000 DLCflexbar-PT-5b-LTLFireability-04 2215652 m, 10612 m/sec, 2421311 t fired, . Pages in use: 334 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 39/2000 DLCflexbar-PT-5b-LTLFireability-04 2268823 m, 10634 m/sec, 2481069 t fired, . Pages in use: 336 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 41/2000 DLCflexbar-PT-5b-LTLFireability-04 2321429 m, 10521 m/sec, 2541071 t fired, . Pages in use: 338 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 43/2000 DLCflexbar-PT-5b-LTLFireability-04 2374601 m, 10634 m/sec, 2600824 t fired, . Pages in use: 340 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 45/2000 DLCflexbar-PT-5b-LTLFireability-04 2424511 m, 9982 m/sec, 2662678 t fired, . Pages in use: 342 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 46/2000 DLCflexbar-PT-5b-LTLFireability-04 2477224 m, 10542 m/sec, 2722332 t fired, . Pages in use: 343 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 47/2000 DLCflexbar-PT-5b-LTLFireability-04 2530133 m, 10581 m/sec, 2781691 t fired, . Pages in use: 344 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 48/2000 DLCflexbar-PT-5b-LTLFireability-04 2583050 m, 10583 m/sec, 2841026 t fired, . Pages in use: 345 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 50/2000 DLCflexbar-PT-5b-LTLFireability-04 2636245 m, 10639 m/sec, 2900620 t fired, . Pages in use: 347 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 52/2000 DLCflexbar-PT-5b-LTLFireability-04 2689605 m, 10672 m/sec, 2960396 t fired, . Pages in use: 349 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 54/2000 DLCflexbar-PT-5b-LTLFireability-04 2743216 m, 10722 m/sec, 3020470 t fired, . Pages in use: 351 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 56/2000 DLCflexbar-PT-5b-LTLFireability-04 2791115 m, 9579 m/sec, 3084346 t fired, . Pages in use: 353 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 58/2000 DLCflexbar-PT-5b-LTLFireability-04 2843201 m, 10417 m/sec, 3145452 t fired, . Pages in use: 355 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 61/2000 DLCflexbar-PT-5b-LTLFireability-04 2893213 m, 10002 m/sec, 3207453 t fired, . Pages in use: 358 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 63/2000 DLCflexbar-PT-5b-LTLFireability-04 2944645 m, 10286 m/sec, 3268407 t fired, . Pages in use: 360 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 65/2000 DLCflexbar-PT-5b-LTLFireability-04 2993595 m, 9790 m/sec, 3330805 t fired, . Pages in use: 362 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 67/2000 DLCflexbar-PT-5b-LTLFireability-04 3042034 m, 9687 m/sec, 3393311 t fired, . Pages in use: 364 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 68/2000 DLCflexbar-PT-5b-LTLFireability-04 3091465 m, 9886 m/sec, 3455485 t fired, . Pages in use: 365 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 69/2000 DLCflexbar-PT-5b-LTLFireability-04 3144555 m, 10618 m/sec, 3515554 t fired, . Pages in use: 366 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 70/2000 DLCflexbar-PT-5b-LTLFireability-04 3197621 m, 10613 m/sec, 3575648 t fired, . Pages in use: 367 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 71/2000 DLCflexbar-PT-5b-LTLFireability-04 3250465 m, 10568 m/sec, 3635517 t fired, . Pages in use: 368 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 73/2000 DLCflexbar-PT-5b-LTLFireability-04 3303149 m, 10536 m/sec, 3695085 t fired, . Pages in use: 370 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 74/2000 DLCflexbar-PT-5b-LTLFireability-04 3355622 m, 10494 m/sec, 3754568 t fired, . Pages in use: 371 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 75/2000 DLCflexbar-PT-5b-LTLFireability-04 3407863 m, 10448 m/sec, 3813583 t fired, . Pages in use: 372 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 76/2000 DLCflexbar-PT-5b-LTLFireability-04 3460146 m, 10456 m/sec, 3872798 t fired, . Pages in use: 373 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 77/2000 DLCflexbar-PT-5b-LTLFireability-04 3512338 m, 10438 m/sec, 3931919 t fired, . Pages in use: 374 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 78/2000 DLCflexbar-PT-5b-LTLFireability-04 3564207 m, 10373 m/sec, 3990698 t fired, . Pages in use: 375 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 79/2000 DLCflexbar-PT-5b-LTLFireability-04 3615795 m, 10317 m/sec, 4049060 t fired, . Pages in use: 376 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 80/2000 DLCflexbar-PT-5b-LTLFireability-04 3667643 m, 10369 m/sec, 4107613 t fired, . Pages in use: 377 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 81/2000 DLCflexbar-PT-5b-LTLFireability-04 3719751 m, 10421 m/sec, 4166616 t fired, . Pages in use: 378 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 82/2000 DLCflexbar-PT-5b-LTLFireability-04 3772301 m, 10510 m/sec, 4225880 t fired, . Pages in use: 379 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 83/2000 DLCflexbar-PT-5b-LTLFireability-04 3824805 m, 10500 m/sec, 4285221 t fired, . Pages in use: 380 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 85/2000 DLCflexbar-PT-5b-LTLFireability-04 3877074 m, 10453 m/sec, 4344384 t fired, . Pages in use: 382 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 86/2000 DLCflexbar-PT-5b-LTLFireability-04 3929488 m, 10482 m/sec, 4403622 t fired, . Pages in use: 383 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 87/2000 DLCflexbar-PT-5b-LTLFireability-04 3982312 m, 10564 m/sec, 4463366 t fired, . Pages in use: 384 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 88/2000 DLCflexbar-PT-5b-LTLFireability-04 4035188 m, 10575 m/sec, 4523057 t fired, . Pages in use: 385 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 89/2000 DLCflexbar-PT-5b-LTLFireability-04 4087681 m, 10498 m/sec, 4582643 t fired, . Pages in use: 386 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 90/2000 DLCflexbar-PT-5b-LTLFireability-04 4140281 m, 10520 m/sec, 4642050 t fired, . Pages in use: 387 16 for DLCflexbar-PT-5b-LTLFireability-04 (local timeout) CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 1 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 388 16 for 6 DLCflexbar-PT-5b-LTLFireability-02 for 12 DLCflexbar-PT-5b-LTLFireability-04 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 2/2000 DLCflexbar-PT-5b-LTLFireability-02 55210 m, 11042 m/sec, 60037 t fired, . 2/5 DLCflexbar-PT-5b-LTLFireability-04 55288 m, -816998 m/sec, 59978 t fired, . Pages in use: 392 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 3/2000 DLCflexbar-PT-5b-LTLFireability-02 110581 m, 11074 m/sec, 120309 t fired, . 2/5 DLCflexbar-PT-5b-LTLFireability-04 110441 m, 11030 m/sec, 120095 t fired, . Pages in use: 393 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 4/2000 DLCflexbar-PT-5b-LTLFireability-02 165768 m, 11037 m/sec, 180398 t fired, . 3/5 DLCflexbar-PT-5b-LTLFireability-04 165444 m, 11000 m/sec, 179954 t fired, . Pages in use: 395 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 6/2000 DLCflexbar-PT-5b-LTLFireability-02 220738 m, 10994 m/sec, 240245 t fired, . 4/5 DLCflexbar-PT-5b-LTLFireability-04 220660 m, 11043 m/sec, 240067 t fired, . Pages in use: 398 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 7/2000 DLCflexbar-PT-5b-LTLFireability-02 276419 m, 11136 m/sec, 300881 t fired, . 5/5 DLCflexbar-PT-5b-LTLFireability-04 275834 m, 11034 m/sec, 300148 t fired, . Pages in use: 400 16 for DLCflexbar-PT-5b-LTLFireability-04 (memory limit exceeded) CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 8/2000 DLCflexbar-PT-5b-LTLFireability-02 331989 m, 11114 m/sec, 361372 t fired, . Pages in use: 401 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 9/2000 DLCflexbar-PT-5b-LTLFireability-02 388090 m, 11220 m/sec, 422439 t fired, . Pages in use: 401 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 10/2000 DLCflexbar-PT-5b-LTLFireability-02 444424 m, 11266 m/sec, 483774 t fired, . Pages in use: 401 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 12/2000 DLCflexbar-PT-5b-LTLFireability-02 500635 m, 11242 m/sec, 544962 t fired, . Pages in use: 401 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 13/2000 DLCflexbar-PT-5b-LTLFireability-02 556535 m, 11180 m/sec, 605852 t fired, . Pages in use: 401 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 14/2000 DLCflexbar-PT-5b-LTLFireability-02 612347 m, 11162 m/sec, 666633 t fired, . Pages in use: 402 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 15/2000 DLCflexbar-PT-5b-LTLFireability-02 667694 m, 11069 m/sec, 726897 t fired, . Pages in use: 403 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 16/2000 DLCflexbar-PT-5b-LTLFireability-02 722973 m, 11055 m/sec, 787091 t fired, . Pages in use: 404 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 17/2000 DLCflexbar-PT-5b-LTLFireability-02 778954 m, 11196 m/sec, 848039 t fired, . Pages in use: 405 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 19/2000 DLCflexbar-PT-5b-LTLFireability-02 834800 m, 11169 m/sec, 908861 t fired, . Pages in use: 407 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 20/2000 DLCflexbar-PT-5b-LTLFireability-02 890968 m, 11233 m/sec, 970018 t fired, . Pages in use: 408 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 21/2000 DLCflexbar-PT-5b-LTLFireability-02 946875 m, 11181 m/sec, 1030930 t fired, . Pages in use: 409 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 23/2000 DLCflexbar-PT-5b-LTLFireability-02 1002092 m, 11043 m/sec, 1091336 t fired, . Pages in use: 411 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 27/2000 DLCflexbar-PT-5b-LTLFireability-02 1055881 m, 10757 m/sec, 1151716 t fired, . Pages in use: 415 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 30/2000 DLCflexbar-PT-5b-LTLFireability-02 1109236 m, 10671 m/sec, 1212191 t fired, . Pages in use: 418 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 34/2000 DLCflexbar-PT-5b-LTLFireability-02 1162470 m, 10646 m/sec, 1272524 t fired, . Pages in use: 422 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 37/2000 DLCflexbar-PT-5b-LTLFireability-02 1214406 m, 10387 m/sec, 1333731 t fired, . Pages in use: 425 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 39/2000 DLCflexbar-PT-5b-LTLFireability-02 1267620 m, 10642 m/sec, 1393696 t fired, . Pages in use: 427 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 41/2000 DLCflexbar-PT-5b-LTLFireability-02 1321270 m, 10730 m/sec, 1453813 t fired, . Pages in use: 429 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 45/2000 DLCflexbar-PT-5b-LTLFireability-02 1375010 m, 10748 m/sec, 1514111 t fired, . Pages in use: 433 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 49/2000 DLCflexbar-PT-5b-LTLFireability-02 1424812 m, 9960 m/sec, 1576729 t fired, . Pages in use: 437 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 53/2000 DLCflexbar-PT-5b-LTLFireability-02 1475940 m, 10225 m/sec, 1638335 t fired, . Pages in use: 441 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 57/2000 DLCflexbar-PT-5b-LTLFireability-02 1524052 m, 9622 m/sec, 1701506 t fired, . Pages in use: 445 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 59/2000 DLCflexbar-PT-5b-LTLFireability-02 1576449 m, 10479 m/sec, 1762475 t fired, . Pages in use: 447 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 61/2000 DLCflexbar-PT-5b-LTLFireability-02 1629842 m, 10678 m/sec, 1822982 t fired, . Pages in use: 449 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 63/2000 DLCflexbar-PT-5b-LTLFireability-02 1682757 m, 10583 m/sec, 1882856 t fired, . Pages in use: 451 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 65/2000 DLCflexbar-PT-5b-LTLFireability-02 1735348 m, 10518 m/sec, 1942394 t fired, . Pages in use: 453 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 67/2000 DLCflexbar-PT-5b-LTLFireability-02 1787808 m, 10492 m/sec, 2001765 t fired, . Pages in use: 455 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 68/2000 DLCflexbar-PT-5b-LTLFireability-02 1840433 m, 10525 m/sec, 2061289 t fired, . Pages in use: 456 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 70/2000 DLCflexbar-PT-5b-LTLFireability-02 1893737 m, 10660 m/sec, 2121474 t fired, . Pages in use: 458 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 72/2000 DLCflexbar-PT-5b-LTLFireability-02 1947058 m, 10664 m/sec, 2181843 t fired, . Pages in use: 460 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 74/2000 DLCflexbar-PT-5b-LTLFireability-02 2000151 m, 10618 m/sec, 2241852 t fired, . Pages in use: 462 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 76/2000 DLCflexbar-PT-5b-LTLFireability-02 2053113 m, 10592 m/sec, 2301768 t fired, . Pages in use: 464 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 78/2000 DLCflexbar-PT-5b-LTLFireability-02 2105999 m, 10577 m/sec, 2361558 t fired, . Pages in use: 466 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 79/2000 DLCflexbar-PT-5b-LTLFireability-02 2159019 m, 10604 m/sec, 2421479 t fired, . Pages in use: 467 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 81/2000 DLCflexbar-PT-5b-LTLFireability-02 2211981 m, 10592 m/sec, 2481467 t fired, . Pages in use: 469 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 83/2000 DLCflexbar-PT-5b-LTLFireability-02 2265003 m, 10604 m/sec, 2541441 t fired, . Pages in use: 471 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 84/2000 DLCflexbar-PT-5b-LTLFireability-02 2318039 m, 10607 m/sec, 2601466 t fired, . Pages in use: 472 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 86/2000 DLCflexbar-PT-5b-LTLFireability-02 2371111 m, 10614 m/sec, 2661428 t fired, . Pages in use: 474 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 88/2000 DLCflexbar-PT-5b-LTLFireability-02 2423573 m, 10492 m/sec, 2720905 t fired, . Pages in use: 476 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 90/2000 DLCflexbar-PT-5b-LTLFireability-02 2475982 m, 10481 m/sec, 2780099 t fired, . Pages in use: 478 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 92/2000 DLCflexbar-PT-5b-LTLFireability-02 2528269 m, 10457 m/sec, 2839252 t fired, . Pages in use: 480 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 94/2000 DLCflexbar-PT-5b-LTLFireability-02 2580382 m, 10422 m/sec, 2898153 t fired, . Pages in use: 482 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 96/2000 DLCflexbar-PT-5b-LTLFireability-02 2632282 m, 10380 m/sec, 2956865 t fired, . Pages in use: 484 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 98/2000 DLCflexbar-PT-5b-LTLFireability-02 2684033 m, 10350 m/sec, 3015471 t fired, . Pages in use: 486 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 99/2000 DLCflexbar-PT-5b-LTLFireability-02 2736113 m, 10416 m/sec, 3074393 t fired, . Pages in use: 487 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 101/2000 DLCflexbar-PT-5b-LTLFireability-02 2787895 m, 10356 m/sec, 3133009 t fired, . Pages in use: 489 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 102/2000 DLCflexbar-PT-5b-LTLFireability-02 2839610 m, 10343 m/sec, 3191535 t fired, . Pages in use: 490 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ true CONJ[0m CONJ false preprocessing[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 104/2000 DLCflexbar-PT-5b-LTLFireability-02 2891197 m, 10317 m/sec, 3249941 t fired, . Pages in use: 492 16 CATEGORY VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-5b"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is DLCflexbar-PT-5b, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r115-smll-171624276300060"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-5b.tgz
mv DLCflexbar-PT-5b execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;