About the Execution of LoLA for DLCflexbar-PT-5b
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 8979.712 | 3600000.00 | 12905675.00 | 1963.20 | ????F?F???????F? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r115-smll-171624276300059.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is DLCflexbar-PT-5b, examination is LTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r115-smll-171624276300059
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 6.9M
-rw-r--r-- 1 mcc users 8.1K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 90K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.7K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 51K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Apr 22 14:37 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Apr 22 14:37 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K May 19 07:15 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 19 18:10 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Apr 12 12:59 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 118K Apr 12 12:59 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.4K Apr 12 12:59 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 69K Apr 12 12:59 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 22 14:37 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Apr 22 14:37 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 3 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 6.5M May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCflexbar-PT-5b-LTLCardinality-00
FORMULA_NAME DLCflexbar-PT-5b-LTLCardinality-01
FORMULA_NAME DLCflexbar-PT-5b-LTLCardinality-02
FORMULA_NAME DLCflexbar-PT-5b-LTLCardinality-03
FORMULA_NAME DLCflexbar-PT-5b-LTLCardinality-04
FORMULA_NAME DLCflexbar-PT-5b-LTLCardinality-05
FORMULA_NAME DLCflexbar-PT-5b-LTLCardinality-06
FORMULA_NAME DLCflexbar-PT-5b-LTLCardinality-07
FORMULA_NAME DLCflexbar-PT-5b-LTLCardinality-08
FORMULA_NAME DLCflexbar-PT-5b-LTLCardinality-09
FORMULA_NAME DLCflexbar-PT-5b-LTLCardinality-10
FORMULA_NAME DLCflexbar-PT-5b-LTLCardinality-11
FORMULA_NAME DLCflexbar-PT-5b-LTLCardinality-12
FORMULA_NAME DLCflexbar-PT-5b-LTLCardinality-13
FORMULA_NAME DLCflexbar-PT-5b-LTLCardinality-14
FORMULA_NAME DLCflexbar-PT-5b-LTLCardinality-15
=== Now, execution of the tool begins
BK_START 1717022824012
FORMULA DLCflexbar-PT-5b-LTLCardinality-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5b-LTLCardinality-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5b-LTLCardinality-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLCardinality.xml[0m
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-06: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 232 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-06: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 237 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-06: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 242 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-06: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 247 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-06: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 252 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-06: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 257 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-06: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 262 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-06: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 267 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-06: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 272 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-06: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 277 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-06: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 282 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-06: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 287 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-06: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 292 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 45 (type CNST) for 42 DLCflexbar-PT-5b-LTLCardinality-14
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 45 (type CNST) for DLCflexbar-PT-5b-LTLCardinality-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 19 (type CNST) for 18 DLCflexbar-PT-5b-LTLCardinality-06
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 19 (type CNST) for DLCflexbar-PT-5b-LTLCardinality-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 297 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 302 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 307 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 312 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 317 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 322 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 327 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 332 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 337 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 342 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 347 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[*** LOG ERROR #0001 ***] [2024-05-29 22:52:53] [status_logger] string pointer is null
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 352 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 357 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 362 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 367 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 372 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 377 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 382 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 387 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 392 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 397 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 402 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 407 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 412 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 417 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 422 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 427 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-04: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 432 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 DLCflexbar-PT-5b-LTLCardinality-02
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 53 (type FNDP) for 12 DLCflexbar-PT-5b-LTLCardinality-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 54 (type EQUN) for 12 DLCflexbar-PT-5b-LTLCardinality-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 53 (type FNDP) for DLCflexbar-PT-5b-LTLCardinality-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 54 (type EQUN) for DLCflexbar-PT-5b-LTLCardinality-04 (obsolete)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 2/226 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 962 m, 192 m/sec, 983 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 437 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 54 (type EQUN) for DLCflexbar-PT-5b-LTLCardinality-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 7/226 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 1137 m, 35 m/sec, 1348 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 442 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 12/226 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 1324 m, 37 m/sec, 1784 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 447 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 17/226 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 1517 m, 38 m/sec, 2242 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 452 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 22/226 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 1707 m, 38 m/sec, 2688 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 457 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 27/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 1930 m, 44 m/sec, 3228 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 462 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 32/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 2145 m, 43 m/sec, 3747 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 467 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 37/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 2358 m, 42 m/sec, 4259 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 472 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 42/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 2588 m, 46 m/sec, 4827 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 477 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 47/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 2765 m, 35 m/sec, 5232 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 482 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 52/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 2955 m, 38 m/sec, 5669 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 487 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 57/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 3111 m, 31 m/sec, 6036 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 492 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 62/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 3316 m, 41 m/sec, 6521 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 497 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 67/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 3533 m, 43 m/sec, 7053 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 502 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 72/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 3709 m, 35 m/sec, 7476 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 507 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 77/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 3926 m, 43 m/sec, 7999 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 512 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 82/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 4126 m, 40 m/sec, 8496 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 517 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 87/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 4345 m, 43 m/sec, 9030 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 522 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 92/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 4498 m, 30 m/sec, 9385 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 527 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 97/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 4880 m, 76 m/sec, 10280 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 532 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 102/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 5253 m, 74 m/sec, 11174 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 537 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 107/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 5542 m, 57 m/sec, 11862 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 542 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 112/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 5818 m, 55 m/sec, 12536 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 547 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 117/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 6081 m, 52 m/sec, 13160 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 552 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 122/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 6274 m, 38 m/sec, 13608 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 557 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 127/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 6524 m, 50 m/sec, 14195 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 562 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 132/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 6743 m, 43 m/sec, 14713 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 567 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 137/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 6982 m, 47 m/sec, 15303 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 572 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 142/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 7232 m, 50 m/sec, 15898 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 577 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 147/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 7499 m, 53 m/sec, 16555 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 582 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 152/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 7779 m, 56 m/sec, 17243 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 587 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 157/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 8064 m, 57 m/sec, 17973 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 592 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 162/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 8489 m, 85 m/sec, 19466 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 597 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 167/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 8942 m, 90 m/sec, 21019 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 602 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 172/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 9394 m, 90 m/sec, 22578 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 607 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 177/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 9878 m, 96 m/sec, 24234 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 612 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 182/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 10339 m, 92 m/sec, 25797 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 617 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 187/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 10840 m, 100 m/sec, 27508 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 622 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 192/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 11378 m, 107 m/sec, 29313 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 627 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 197/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 11800 m, 84 m/sec, 30777 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 632 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 202/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 12238 m, 87 m/sec, 32254 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 637 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 207/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 12679 m, 88 m/sec, 33735 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 642 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 212/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 13581 m, 180 m/sec, 36783 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 647 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 217/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 14835 m, 250 m/sec, 41063 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 652 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 222/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 16071 m, 247 m/sec, 45235 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 657 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 227/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 17360 m, 257 m/sec, 49600 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 662 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 232/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 18574 m, 242 m/sec, 53755 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 667 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 237/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 19783 m, 241 m/sec, 57856 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 672 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 242/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-02 20957 m, 234 m/sec, 61890 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 677 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 7 (type EXCL) for DLCflexbar-PT-5b-LTLCardinality-02 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 682 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 50 (type EXCL) for 49 DLCflexbar-PT-5b-LTLCardinality-15
[[35mlola[0m][I] time limit : 243 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 DLCflexbar-PT-5b-LTLCardinality-02
[[35mlola[0m][I] time limit : 2918 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 50 (type EXCL) for DLCflexbar-PT-5b-LTLCardinality-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 4
[[35mlola[0m][I] fired transitions : 3
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 5/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 1483 m, -3894 m/sec, 2156 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 687 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 10/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 2083 m, 120 m/sec, 3593 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 692 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 15/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 2677 m, 118 m/sec, 5025 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 697 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 20/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 3201 m, 104 m/sec, 6247 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 702 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 25/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 3746 m, 109 m/sec, 7563 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 707 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 30/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 4374 m, 125 m/sec, 9102 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 712 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 35/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 4899 m, 105 m/sec, 10325 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 717 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 40/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 5461 m, 112 m/sec, 11664 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 722 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 45/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 6047 m, 117 m/sec, 13086 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 727 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 50/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 6546 m, 99 m/sec, 14244 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 732 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 55/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 7091 m, 109 m/sec, 15559 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 737 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 60/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 7689 m, 119 m/sec, 17017 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 742 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 65/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 8534 m, 169 m/sec, 19612 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 747 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 70/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 9762 m, 245 m/sec, 23817 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 752 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 75/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 11078 m, 263 m/sec, 28312 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 757 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 80/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 12391 m, 262 m/sec, 32750 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 762 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 85/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 13817 m, 285 m/sec, 37572 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 767 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 90/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 15059 m, 248 m/sec, 41812 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 772 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 95/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 16384 m, 265 m/sec, 46302 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 777 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 100/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 17759 m, 275 m/sec, 50927 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 782 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 105/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 18919 m, 232 m/sec, 54927 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 787 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 110/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 20208 m, 257 m/sec, 59329 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 792 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 115/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 21485 m, 255 m/sec, 63678 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 797 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 120/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 22966 m, 296 m/sec, 68648 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 802 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 125/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 24425 m, 291 m/sec, 73583 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 807 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 130/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 25738 m, 262 m/sec, 78167 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 812 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 135/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 26958 m, 244 m/sec, 82333 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 817 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 140/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 28266 m, 261 m/sec, 86805 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 822 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 145/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 29618 m, 270 m/sec, 91437 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 827 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 150/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 31067 m, 289 m/sec, 96327 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 832 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 155/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 32237 m, 234 m/sec, 100373 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 837 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 160/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 33538 m, 260 m/sec, 104801 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 842 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 165/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 34837 m, 259 m/sec, 109213 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 847 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 170/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 36239 m, 280 m/sec, 113958 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 852 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 175/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 37422 m, 236 m/sec, 117995 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 857 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 180/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 38742 m, 264 m/sec, 122462 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 862 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 185/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 40071 m, 265 m/sec, 126937 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 867 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 190/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 41570 m, 299 m/sec, 131964 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 872 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 195/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 42922 m, 270 m/sec, 136556 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 877 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 200/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 44101 m, 235 m/sec, 140690 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 882 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 205/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 45328 m, 245 m/sec, 144944 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 887 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 210/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 46595 m, 253 m/sec, 149252 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 892 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 215/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 47940 m, 269 m/sec, 153880 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 897 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 220/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 49129 m, 237 m/sec, 157948 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 902 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 225/243 1/5 DLCflexbar-PT-5b-LTLCardinality-02 50265 m, 227 m/sec, 161891 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 907 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 230/243 2/5 DLCflexbar-PT-5b-LTLCardinality-02 51443 m, 235 m/sec, 165926 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 912 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 235/243 2/5 DLCflexbar-PT-5b-LTLCardinality-02 52683 m, 248 m/sec, 170216 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 917 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 240/243 2/5 DLCflexbar-PT-5b-LTLCardinality-02 53937 m, 250 m/sec, 174545 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 922 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 7 (type EXCL) for DLCflexbar-PT-5b-LTLCardinality-02 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 927 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 40 (type EXCL) for 39 DLCflexbar-PT-5b-LTLCardinality-13
[[35mlola[0m][I] time limit : 243 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 DLCflexbar-PT-5b-LTLCardinality-02
[[35mlola[0m][I] time limit : 2673 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 5/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 1468 m, -10493 m/sec, 2121 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 5/243 1/2000 DLCflexbar-PT-5b-LTLCardinality-13 38310 m, 7662 m/sec, 67827 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 932 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 10/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 2063 m, 119 m/sec, 3546 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 10/222 1/2000 DLCflexbar-PT-5b-LTLCardinality-13 75498 m, 7437 m/sec, 134393 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 937 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 15/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 2654 m, 118 m/sec, 4970 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 15/222 2/2000 DLCflexbar-PT-5b-LTLCardinality-13 114330 m, 7766 m/sec, 203514 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 942 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 20/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 3179 m, 105 m/sec, 6197 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 20/222 2/2000 DLCflexbar-PT-5b-LTLCardinality-13 153325 m, 7799 m/sec, 273687 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 947 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 25/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 3722 m, 108 m/sec, 7502 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 25/222 3/2000 DLCflexbar-PT-5b-LTLCardinality-13 192133 m, 7761 m/sec, 343522 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 952 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 30/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 4333 m, 122 m/sec, 8999 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 30/222 3/2000 DLCflexbar-PT-5b-LTLCardinality-13 231670 m, 7907 m/sec, 414294 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 957 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 35/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 4863 m, 106 m/sec, 10238 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 35/222 3/2000 DLCflexbar-PT-5b-LTLCardinality-13 270865 m, 7839 m/sec, 484865 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 962 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 40/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 5410 m, 109 m/sec, 11546 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 40/222 4/2000 DLCflexbar-PT-5b-LTLCardinality-13 309928 m, 7812 m/sec, 555140 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 967 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 45/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 6001 m, 118 m/sec, 12978 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 45/222 4/2000 DLCflexbar-PT-5b-LTLCardinality-13 349191 m, 7852 m/sec, 625756 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 972 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 50/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 6485 m, 96 m/sec, 14096 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 50/222 5/2000 DLCflexbar-PT-5b-LTLCardinality-13 388114 m, 7784 m/sec, 696067 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 977 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 55/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 7003 m, 103 m/sec, 15354 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 55/222 5/2000 DLCflexbar-PT-5b-LTLCardinality-13 427353 m, 7847 m/sec, 766172 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 982 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 60/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 7565 m, 112 m/sec, 16716 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 60/222 5/2000 DLCflexbar-PT-5b-LTLCardinality-13 465770 m, 7683 m/sec, 835727 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 987 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 65/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 8281 m, 143 m/sec, 18728 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 65/222 6/2000 DLCflexbar-PT-5b-LTLCardinality-13 503709 m, 7587 m/sec, 904305 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 992 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 70/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 9447 m, 233 m/sec, 22780 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 70/222 6/2000 DLCflexbar-PT-5b-LTLCardinality-13 541868 m, 7631 m/sec, 973240 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 997 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 75/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 10720 m, 254 m/sec, 27100 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 75/222 6/2000 DLCflexbar-PT-5b-LTLCardinality-13 580471 m, 7720 m/sec, 1043123 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1002 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 80/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 12037 m, 263 m/sec, 31562 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 80/222 7/2000 DLCflexbar-PT-5b-LTLCardinality-13 619423 m, 7790 m/sec, 1113042 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1007 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 85/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 13388 m, 270 m/sec, 36130 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 85/222 7/2000 DLCflexbar-PT-5b-LTLCardinality-13 658304 m, 7776 m/sec, 1183378 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1012 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 90/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 14685 m, 259 m/sec, 40534 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 90/222 8/2000 DLCflexbar-PT-5b-LTLCardinality-13 697112 m, 7761 m/sec, 1253676 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1017 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 95/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 15920 m, 247 m/sec, 44742 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 95/222 8/2000 DLCflexbar-PT-5b-LTLCardinality-13 735858 m, 7749 m/sec, 1323863 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1022 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 100/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 17238 m, 263 m/sec, 49183 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 100/222 8/2000 DLCflexbar-PT-5b-LTLCardinality-13 774510 m, 7730 m/sec, 1393902 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1027 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 105/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 18502 m, 252 m/sec, 53506 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 105/222 9/2000 DLCflexbar-PT-5b-LTLCardinality-13 812804 m, 7658 m/sec, 1463328 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1032 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 110/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 19755 m, 250 m/sec, 57740 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 110/222 10/2000 DLCflexbar-PT-5b-LTLCardinality-13 850799 m, 7599 m/sec, 1532464 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1037 secs. Pages in use: 17
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 115/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 20959 m, 240 m/sec, 61892 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 115/222 12/2000 DLCflexbar-PT-5b-LTLCardinality-13 889852 m, 7810 m/sec, 1600862 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1042 secs. Pages in use: 19
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 120/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 22294 m, 267 m/sec, 66424 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 120/222 13/2000 DLCflexbar-PT-5b-LTLCardinality-13 929197 m, 7869 m/sec, 1669607 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1047 secs. Pages in use: 20
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 125/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 23780 m, 297 m/sec, 71419 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 125/222 14/2000 DLCflexbar-PT-5b-LTLCardinality-13 968463 m, 7853 m/sec, 1738291 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1052 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 130/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 25252 m, 294 m/sec, 76441 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 130/222 16/2000 DLCflexbar-PT-5b-LTLCardinality-13 1007609 m, 7829 m/sec, 1806731 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1057 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 135/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 26405 m, 230 m/sec, 80442 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 135/222 17/2000 DLCflexbar-PT-5b-LTLCardinality-13 1044549 m, 7388 m/sec, 1876628 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1062 secs. Pages in use: 24
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 140/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 27672 m, 253 m/sec, 84780 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 140/222 19/2000 DLCflexbar-PT-5b-LTLCardinality-13 1079175 m, 6925 m/sec, 1947663 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1067 secs. Pages in use: 26
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 145/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 28934 m, 252 m/sec, 89117 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 145/222 20/2000 DLCflexbar-PT-5b-LTLCardinality-13 1115755 m, 7316 m/sec, 2017043 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1072 secs. Pages in use: 27
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 150/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 30346 m, 282 m/sec, 93875 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 150/222 21/2000 DLCflexbar-PT-5b-LTLCardinality-13 1150657 m, 6980 m/sec, 2087116 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1077 secs. Pages in use: 28
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 155/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 31612 m, 253 m/sec, 98207 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 155/222 23/2000 DLCflexbar-PT-5b-LTLCardinality-13 1183852 m, 6639 m/sec, 2158650 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1082 secs. Pages in use: 30
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 160/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 32804 m, 238 m/sec, 102303 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 160/222 24/2000 DLCflexbar-PT-5b-LTLCardinality-13 1220694 m, 7368 m/sec, 2227946 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1087 secs. Pages in use: 31
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 165/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 34090 m, 257 m/sec, 106646 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 165/222 25/2000 DLCflexbar-PT-5b-LTLCardinality-13 1254662 m, 6793 m/sec, 2299626 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1092 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 170/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 35368 m, 255 m/sec, 111009 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 170/222 26/2000 DLCflexbar-PT-5b-LTLCardinality-13 1290324 m, 7132 m/sec, 2371228 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1097 secs. Pages in use: 33
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 175/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 36652 m, 256 m/sec, 115375 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 175/222 28/2000 DLCflexbar-PT-5b-LTLCardinality-13 1326793 m, 7293 m/sec, 2443015 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1102 secs. Pages in use: 35
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 180/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 37894 m, 248 m/sec, 119582 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 180/222 29/2000 DLCflexbar-PT-5b-LTLCardinality-13 1361623 m, 6966 m/sec, 2515600 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1107 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 185/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 39215 m, 264 m/sec, 124041 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 185/222 30/2000 DLCflexbar-PT-5b-LTLCardinality-13 1398707 m, 7416 m/sec, 2586803 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1112 secs. Pages in use: 37
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 190/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 40493 m, 255 m/sec, 128348 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 190/222 31/2000 DLCflexbar-PT-5b-LTLCardinality-13 1436371 m, 7532 m/sec, 2657490 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1117 secs. Pages in use: 38
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 195/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 42054 m, 312 m/sec, 133559 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 195/222 33/2000 DLCflexbar-PT-5b-LTLCardinality-13 1472635 m, 7252 m/sec, 2729180 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1122 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 200/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 43232 m, 235 m/sec, 137626 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 200/222 34/2000 DLCflexbar-PT-5b-LTLCardinality-13 1508501 m, 7173 m/sec, 2801166 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1127 secs. Pages in use: 41
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 205/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 44416 m, 236 m/sec, 141774 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 205/222 36/2000 DLCflexbar-PT-5b-LTLCardinality-13 1541730 m, 6645 m/sec, 2874810 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1132 secs. Pages in use: 44
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 210/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 45618 m, 240 m/sec, 145920 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 210/222 37/2000 DLCflexbar-PT-5b-LTLCardinality-13 1576363 m, 6926 m/sec, 2947491 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1137 secs. Pages in use: 45
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 215/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 46875 m, 251 m/sec, 150196 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 215/222 38/2000 DLCflexbar-PT-5b-LTLCardinality-13 1613103 m, 7348 m/sec, 3018755 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1142 secs. Pages in use: 46
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 220/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 48165 m, 258 m/sec, 154655 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 220/222 39/2000 DLCflexbar-PT-5b-LTLCardinality-13 1648286 m, 7036 m/sec, 3091088 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1147 secs. Pages in use: 47
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 40 (type EXCL) for DLCflexbar-PT-5b-LTLCardinality-13 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 225/2673 1/5 DLCflexbar-PT-5b-LTLCardinality-02 49368 m, 240 m/sec, 158771 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1152 secs. Pages in use: 49
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 40 (type EXCL) for 39 DLCflexbar-PT-5b-LTLCardinality-13
[[35mlola[0m][I] time limit : 2448 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 230/243 2/5 DLCflexbar-PT-5b-LTLCardinality-02 50448 m, 216 m/sec, 162532 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 5/2448 1/5 DLCflexbar-PT-5b-LTLCardinality-13 39868 m, -321683 m/sec, 70724 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1157 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 235/243 2/5 DLCflexbar-PT-5b-LTLCardinality-02 51625 m, 235 m/sec, 166578 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 10/204 1/5 DLCflexbar-PT-5b-LTLCardinality-13 79279 m, 7882 m/sec, 141007 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1162 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 240/243 2/5 DLCflexbar-PT-5b-LTLCardinality-02 52846 m, 244 m/sec, 170760 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 15/204 2/5 DLCflexbar-PT-5b-LTLCardinality-13 118791 m, 7902 m/sec, 211496 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1167 secs. Pages in use: 52
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 7 (type EXCL) for DLCflexbar-PT-5b-LTLCardinality-02 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 20/204 2/5 DLCflexbar-PT-5b-LTLCardinality-13 158707 m, 7983 m/sec, 283256 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1172 secs. Pages in use: 52
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 DLCflexbar-PT-5b-LTLCardinality-02
[[35mlola[0m][I] time limit : 2428 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 5/2428 1/5 DLCflexbar-PT-5b-LTLCardinality-02 1370 m, -10295 m/sec, 1892 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 25/222 3/5 DLCflexbar-PT-5b-LTLCardinality-13 190603 m, 6379 m/sec, 340794 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1177 secs. Pages in use: 55
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 10/2428 1/5 DLCflexbar-PT-5b-LTLCardinality-02 1839 m, 93 m/sec, 3011 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 30/204 3/5 DLCflexbar-PT-5b-LTLCardinality-13 222025 m, 6284 m/sec, 397103 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1182 secs. Pages in use: 55
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 15/2428 1/5 DLCflexbar-PT-5b-LTLCardinality-02 2336 m, 99 m/sec, 4207 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 35/204 3/5 DLCflexbar-PT-5b-LTLCardinality-13 253185 m, 6232 m/sec, 453085 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1187 secs. Pages in use: 55
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 20/2428 1/5 DLCflexbar-PT-5b-LTLCardinality-02 2785 m, 89 m/sec, 5276 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 40/204 4/5 DLCflexbar-PT-5b-LTLCardinality-13 284662 m, 6295 m/sec, 509718 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1192 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 25/2428 1/5 DLCflexbar-PT-5b-LTLCardinality-02 3218 m, 86 m/sec, 6289 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 45/204 4/5 DLCflexbar-PT-5b-LTLCardinality-13 315068 m, 6081 m/sec, 564338 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1197 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 30/2428 1/5 DLCflexbar-PT-5b-LTLCardinality-02 3654 m, 87 m/sec, 7342 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 50/204 4/5 DLCflexbar-PT-5b-LTLCardinality-13 346297 m, 6245 m/sec, 620559 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1202 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 35/2428 1/5 DLCflexbar-PT-5b-LTLCardinality-02 4162 m, 101 m/sec, 8582 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 55/204 4/5 DLCflexbar-PT-5b-LTLCardinality-13 377159 m, 6172 m/sec, 676142 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1207 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 40/2428 1/5 DLCflexbar-PT-5b-LTLCardinality-02 4621 m, 91 m/sec, 9667 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 60/204 5/5 DLCflexbar-PT-5b-LTLCardinality-13 409142 m, 6396 m/sec, 733176 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1212 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 45/2428 1/5 DLCflexbar-PT-5b-LTLCardinality-02 5063 m, 88 m/sec, 10708 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 65/204 5/5 DLCflexbar-PT-5b-LTLCardinality-13 439505 m, 6072 m/sec, 788214 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1217 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 50/2428 1/5 DLCflexbar-PT-5b-LTLCardinality-02 5506 m, 88 m/sec, 11775 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 70/204 5/5 DLCflexbar-PT-5b-LTLCardinality-13 470038 m, 6106 m/sec, 843393 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1222 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 40 (type EXCL) for DLCflexbar-PT-5b-LTLCardinality-13 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 55/2428 1/5 DLCflexbar-PT-5b-LTLCardinality-02 6059 m, 110 m/sec, 13110 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1227 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 60/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 6572 m, 102 m/sec, 14304 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1232 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 65/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 7111 m, 107 m/sec, 15608 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1237 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 70/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 7706 m, 119 m/sec, 17060 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1242 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 75/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 8591 m, 177 m/sec, 19796 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1247 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 80/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 9817 m, 245 m/sec, 24025 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1252 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 85/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 11170 m, 270 m/sec, 28621 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1257 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 90/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 12472 m, 260 m/sec, 33033 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1262 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 95/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 13917 m, 289 m/sec, 37909 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1267 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 100/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 15169 m, 250 m/sec, 42191 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1272 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 105/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 16494 m, 265 m/sec, 46689 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1277 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 110/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 17902 m, 281 m/sec, 51428 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1282 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 115/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 19073 m, 234 m/sec, 55454 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1287 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 120/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 20380 m, 261 m/sec, 59893 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1292 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 125/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 21670 m, 258 m/sec, 64316 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1297 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 130/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 23150 m, 296 m/sec, 69280 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1302 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 135/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 24693 m, 308 m/sec, 74494 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1307 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 140/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 25935 m, 248 m/sec, 78826 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1312 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 145/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 27185 m, 250 m/sec, 83107 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1317 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 150/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 28505 m, 264 m/sec, 87617 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1322 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 155/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 29850 m, 269 m/sec, 92210 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1327 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 160/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 31281 m, 286 m/sec, 97052 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1332 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 165/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 32477 m, 239 m/sec, 101204 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1337 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 170/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 33807 m, 266 m/sec, 105725 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1342 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 175/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 35113 m, 261 m/sec, 110141 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1347 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 180/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 36457 m, 268 m/sec, 114699 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1352 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 185/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 37684 m, 245 m/sec, 118893 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1357 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 190/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 39008 m, 264 m/sec, 123353 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1362 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 195/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 40337 m, 265 m/sec, 127836 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1367 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 200/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 41894 m, 311 m/sec, 133042 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1372 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 205/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 43143 m, 249 m/sec, 137325 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1377 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 210/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 44331 m, 237 m/sec, 141471 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1382 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 215/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 45567 m, 247 m/sec, 145765 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1387 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 220/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 46848 m, 256 m/sec, 150112 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1392 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 7 (type EXCL) for DLCflexbar-PT-5b-LTLCardinality-02 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1397 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 37 (type EXCL) for 36 DLCflexbar-PT-5b-LTLCardinality-12
[[35mlola[0m][I] time limit : 220 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 DLCflexbar-PT-5b-LTLCardinality-02
[[35mlola[0m][I] time limit : 2203 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 37 (type EXCL) for DLCflexbar-PT-5b-LTLCardinality-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 54
[[35mlola[0m][I] fired transitions : 54
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 5/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 1389 m, -9091 m/sec, 1936 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1402 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 10/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 1893 m, 100 m/sec, 3141 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1407 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 15/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 2400 m, 101 m/sec, 4360 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1412 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 20/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 2823 m, 84 m/sec, 5364 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1417 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 25/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 3275 m, 90 m/sec, 6424 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1422 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 30/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 3726 m, 90 m/sec, 7510 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1427 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 35/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 4205 m, 95 m/sec, 8689 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1432 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 40/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 4642 m, 87 m/sec, 9717 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1437 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 45/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 5085 m, 88 m/sec, 10758 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1442 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 50/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 5524 m, 87 m/sec, 11822 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1447 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 55/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 6007 m, 96 m/sec, 12995 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1452 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 60/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 6399 m, 78 m/sec, 13905 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1457 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 65/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 6838 m, 87 m/sec, 14943 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1462 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 70/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 7269 m, 86 m/sec, 15986 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1467 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 75/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 7745 m, 95 m/sec, 17160 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1472 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 80/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 8415 m, 134 m/sec, 19216 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1477 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 85/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 9388 m, 194 m/sec, 22563 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1482 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 90/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 10391 m, 200 m/sec, 25981 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1487 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 95/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 11409 m, 203 m/sec, 29423 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1492 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 100/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 12472 m, 212 m/sec, 33033 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1497 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 105/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 13667 m, 239 m/sec, 37056 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1502 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 110/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 14730 m, 212 m/sec, 40713 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1507 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 115/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 15707 m, 195 m/sec, 44046 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1512 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 120/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 16731 m, 204 m/sec, 47474 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1517 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 125/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 17874 m, 228 m/sec, 51296 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1522 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 130/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 18758 m, 176 m/sec, 54362 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1527 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 135/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 19778 m, 204 m/sec, 57848 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1532 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 140/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 20780 m, 200 m/sec, 61279 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1537 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 145/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 21815 m, 207 m/sec, 64791 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1542 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 150/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 23011 m, 239 m/sec, 68809 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1547 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 155/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 24202 m, 238 m/sec, 72849 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1552 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 160/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 25300 m, 219 m/sec, 76612 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1557 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 165/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 26189 m, 177 m/sec, 79704 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1562 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 170/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 27207 m, 203 m/sec, 83179 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1567 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 175/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 28258 m, 210 m/sec, 86764 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1572 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 180/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 29278 m, 204 m/sec, 90300 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1577 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 185/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 30432 m, 230 m/sec, 94147 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1582 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 190/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 31445 m, 202 m/sec, 97634 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1587 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 195/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 32399 m, 190 m/sec, 100940 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1592 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 200/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 33441 m, 208 m/sec, 104487 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1597 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 205/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 34413 m, 194 m/sec, 107774 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1602 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 210/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 35500 m, 217 m/sec, 111456 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1607 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 215/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 36496 m, 199 m/sec, 114825 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1612 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 220/220 1/5 DLCflexbar-PT-5b-LTLCardinality-02 37415 m, 183 m/sec, 117959 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1617 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 7 (type EXCL) for DLCflexbar-PT-5b-LTLCardinality-02 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1622 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 31 (type EXCL) for 30 DLCflexbar-PT-5b-LTLCardinality-10
[[35mlola[0m][I] time limit : 219 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 DLCflexbar-PT-5b-LTLCardinality-02
[[35mlola[0m][I] time limit : 1978 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 5/1978 1/5 DLCflexbar-PT-5b-LTLCardinality-02 1240 m, -7235 m/sec, 1585 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 5/219 1/2000 DLCflexbar-PT-5b-LTLCardinality-10 31307 m, 6261 m/sec, 34002 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1627 secs. Pages in use: 61
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 10/1978 1/5 DLCflexbar-PT-5b-LTLCardinality-02 1574 m, 66 m/sec, 2375 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 10/197 2/2000 DLCflexbar-PT-5b-LTLCardinality-10 62260 m, 6190 m/sec, 67711 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1632 secs. Pages in use: 62
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 15/1978 1/5 DLCflexbar-PT-5b-LTLCardinality-02 1894 m, 64 m/sec, 3143 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 15/197 3/2000 DLCflexbar-PT-5b-LTLCardinality-10 91089 m, 5765 m/sec, 99098 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1637 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 20/1978 1/5 DLCflexbar-PT-5b-LTLCardinality-02 2273 m, 75 m/sec, 4051 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 20/197 3/2000 DLCflexbar-PT-5b-LTLCardinality-10 121756 m, 6133 m/sec, 132495 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1642 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 25/1978 1/5 DLCflexbar-PT-5b-LTLCardinality-02 2616 m, 68 m/sec, 4886 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 25/197 4/2000 DLCflexbar-PT-5b-LTLCardinality-10 152197 m, 6088 m/sec, 165615 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1647 secs. Pages in use: 64
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 30/1978 1/5 DLCflexbar-PT-5b-LTLCardinality-02 2906 m, 58 m/sec, 5555 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 30/197 5/2000 DLCflexbar-PT-5b-LTLCardinality-10 182568 m, 6074 m/sec, 198683 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1652 secs. Pages in use: 66
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 35/1978 1/5 DLCflexbar-PT-5b-LTLCardinality-02 3180 m, 54 m/sec, 6199 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 35/197 5/2000 DLCflexbar-PT-5b-LTLCardinality-10 212467 m, 5979 m/sec, 231238 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1657 secs. Pages in use: 66
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 40/1978 1/5 DLCflexbar-PT-5b-LTLCardinality-02 3510 m, 66 m/sec, 6995 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 40/197 6/2000 DLCflexbar-PT-5b-LTLCardinality-10 246243 m, 6755 m/sec, 268019 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1662 secs. Pages in use: 67
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 45/1978 1/5 DLCflexbar-PT-5b-LTLCardinality-02 3804 m, 58 m/sec, 7705 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 45/197 7/2000 DLCflexbar-PT-5b-LTLCardinality-10 276102 m, 5971 m/sec, 300529 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1667 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 50/1978 1/5 DLCflexbar-PT-5b-LTLCardinality-02 4126 m, 64 m/sec, 8496 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 50/197 7/2000 DLCflexbar-PT-5b-LTLCardinality-10 307510 m, 6281 m/sec, 334720 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1672 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 55/1978 1/5 DLCflexbar-PT-5b-LTLCardinality-02 4457 m, 66 m/sec, 9298 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 55/197 8/2000 DLCflexbar-PT-5b-LTLCardinality-10 340670 m, 6632 m/sec, 370819 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1677 secs. Pages in use: 69
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 60/1978 1/5 DLCflexbar-PT-5b-LTLCardinality-02 4715 m, 51 m/sec, 9889 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 60/197 9/2000 DLCflexbar-PT-5b-LTLCardinality-10 375503 m, 6966 m/sec, 408741 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1682 secs. Pages in use: 70
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 65/1978 1/5 DLCflexbar-PT-5b-LTLCardinality-02 5015 m, 60 m/sec, 10597 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 65/197 10/2000 DLCflexbar-PT-5b-LTLCardinality-10 411878 m, 7275 m/sec, 448338 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1687 secs. Pages in use: 72
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 70/1978 1/5 DLCflexbar-PT-5b-LTLCardinality-02 5315 m, 60 m/sec, 11317 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 70/197 10/2000 DLCflexbar-PT-5b-LTLCardinality-10 444037 m, 6431 m/sec, 483351 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1692 secs. Pages in use: 72
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 75/1978 1/5 DLCflexbar-PT-5b-LTLCardinality-02 5679 m, 72 m/sec, 12197 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 75/197 11/2000 DLCflexbar-PT-5b-LTLCardinality-10 474965 m, 6185 m/sec, 517020 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1697 secs. Pages in use: 73
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 80/1978 1/5 DLCflexbar-PT-5b-LTLCardinality-02 6017 m, 67 m/sec, 13016 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 80/197 12/2000 DLCflexbar-PT-5b-LTLCardinality-10 506458 m, 6298 m/sec, 551301 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1702 secs. Pages in use: 74
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 85/1978 1/5 DLCflexbar-PT-5b-LTLCardinality-02 6291 m, 54 m/sec, 13647 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 85/197 12/2000 DLCflexbar-PT-5b-LTLCardinality-10 537285 m, 6165 m/sec, 584867 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1707 secs. Pages in use: 74
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 90/1978 1/5 DLCflexbar-PT-5b-LTLCardinality-02 6604 m, 62 m/sec, 14381 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 90/197 13/2000 DLCflexbar-PT-5b-LTLCardinality-10 566931 m, 5929 m/sec, 617176 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1712 secs. Pages in use: 75
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 95/1978 1/5 DLCflexbar-PT-5b-LTLCardinality-02 6904 m, 60 m/sec, 15105 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 95/197 14/2000 DLCflexbar-PT-5b-LTLCardinality-10 598637 m, 6341 m/sec, 651704 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1717 secs. Pages in use: 76
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 100/1978 1/5 DLCflexbar-PT-5b-LTLCardinality-02 7201 m, 59 m/sec, 15820 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 100/197 14/2000 DLCflexbar-PT-5b-LTLCardinality-10 632779 m, 6828 m/sec, 688873 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1722 secs. Pages in use: 76
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 105/1978 1/5 DLCflexbar-PT-5b-LTLCardinality-02 7550 m, 69 m/sec, 16677 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 105/197 15/2000 DLCflexbar-PT-5b-LTLCardinality-10 664616 m, 6367 m/sec, 723543 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1727 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 110/1978 1/5 DLCflexbar-PT-5b-LTLCardinality-02 7905 m, 71 m/sec, 17480 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 110/197 16/2000 DLCflexbar-PT-5b-LTLCardinality-10 697695 m, 6615 m/sec, 759567 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1732 secs. Pages in use: 78
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 115/1978 1/5 DLCflexbar-PT-5b-LTLCardinality-02 8418 m, 102 m/sec, 19222 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 115/197 17/2000 DLCflexbar-PT-5b-LTLCardinality-10 730175 m, 6496 m/sec, 794934 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1737 secs. Pages in use: 79
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 120/1978 1/5 DLCflexbar-PT-5b-LTLCardinality-02 9042 m, 124 m/sec, 21374 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 120/197 17/2000 DLCflexbar-PT-5b-LTLCardinality-10 760905 m, 6146 m/sec, 828390 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1742 secs. Pages in use: 79
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 125/1978 1/5 DLCflexbar-PT-5b-LTLCardinality-02 9860 m, 163 m/sec, 24169 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 125/197 18/2000 DLCflexbar-PT-5b-LTLCardinality-10 791124 m, 6043 m/sec, 861300 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1747 secs. Pages in use: 81
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 130/1978 1/5 DLCflexbar-PT-5b-LTLCardinality-02 10615 m, 151 m/sec, 26735 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 130/197 18/2000 DLCflexbar-PT-5b-LTLCardinality-10 824531 m, 6681 m/sec, 897680 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1752 secs. Pages in use: 81
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 135/1978 1/5 DLCflexbar-PT-5b-LTLCardinality-02 11389 m, 154 m/sec, 29341 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 135/197 19/2000 DLCflexbar-PT-5b-LTLCardinality-10 855500 m, 6193 m/sec, 931392 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1757 secs. Pages in use: 82
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 140/1978 1/5 DLCflexbar-PT-5b-LTLCardinality-02 12123 m, 146 m/sec, 31857 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 140/197 20/2000 DLCflexbar-PT-5b-LTLCardinality-10 887616 m, 6423 m/sec, 966364 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1762 secs. Pages in use: 83
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 145/1978 1/5 DLCflexbar-PT-5b-LTLCardinality-02 12815 m, 138 m/sec, 34210 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 145/197 21/2000 DLCflexbar-PT-5b-LTLCardinality-10 922708 m, 7018 m/sec, 1004586 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1767 secs. Pages in use: 84
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 150/1978 1/5 DLCflexbar-PT-5b-LTLCardinality-02 13649 m, 166 m/sec, 37016 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 150/197 21/2000 DLCflexbar-PT-5b-LTLCardinality-10 950409 m, 5540 m/sec, 1034790 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1772 secs. Pages in use: 84
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 155/1978 1/5 DLCflexbar-PT-5b-LTLCardinality-02 14473 m, 164 m/sec, 39801 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 155/197 22/2000 DLCflexbar-PT-5b-LTLCardinality-10 981684 m, 6255 m/sec, 1068835 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1777 secs. Pages in use: 85
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 160/1978 1/5 DLCflexbar-PT-5b-LTLCardinality-02 15081 m, 121 m/sec, 41907 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 160/197 24/2000 DLCflexbar-PT-5b-LTLCardinality-10 1013427 m, 6348 m/sec, 1104022 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1782 secs. Pages in use: 87
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 165/1978 1/5 DLCflexbar-PT-5b-LTLCardinality-02 15778 m, 139 m/sec, 44275 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 165/197 26/2000 DLCflexbar-PT-5b-LTLCardinality-10 1045290 m, 6372 m/sec, 1139804 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1787 secs. Pages in use: 89
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 170/1978 1/5 DLCflexbar-PT-5b-LTLCardinality-02 16542 m, 152 m/sec, 46843 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 170/197 28/2000 DLCflexbar-PT-5b-LTLCardinality-10 1076286 m, 6199 m/sec, 1175116 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1792 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 175/1978 1/5 DLCflexbar-PT-5b-LTLCardinality-02 17282 m, 148 m/sec, 49328 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 175/197 30/2000 DLCflexbar-PT-5b-LTLCardinality-10 1104949 m, 5732 m/sec, 1207390 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1797 secs. Pages in use: 93
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 180/1978 1/5 DLCflexbar-PT-5b-LTLCardinality-02 18047 m, 153 m/sec, 51923 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 180/197 32/2000 DLCflexbar-PT-5b-LTLCardinality-10 1135492 m, 6108 m/sec, 1241745 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1802 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 185/1978 1/5 DLCflexbar-PT-5b-LTLCardinality-02 18746 m, 139 m/sec, 54319 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 185/197 34/2000 DLCflexbar-PT-5b-LTLCardinality-10 1164808 m, 5863 m/sec, 1275146 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1807 secs. Pages in use: 97
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 190/1978 1/5 DLCflexbar-PT-5b-LTLCardinality-02 19396 m, 130 m/sec, 56542 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 190/197 36/2000 DLCflexbar-PT-5b-LTLCardinality-10 1193054 m, 5649 m/sec, 1307188 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1812 secs. Pages in use: 99
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 195/1978 1/5 DLCflexbar-PT-5b-LTLCardinality-02 20123 m, 145 m/sec, 59022 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 195/197 38/2000 DLCflexbar-PT-5b-LTLCardinality-10 1222651 m, 5919 m/sec, 1343147 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1817 secs. Pages in use: 101
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 31 (type EXCL) for DLCflexbar-PT-5b-LTLCardinality-10 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 200/1978 1/5 DLCflexbar-PT-5b-LTLCardinality-02 20838 m, 143 m/sec, 61479 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1822 secs. Pages in use: 101
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 31 (type EXCL) for 30 DLCflexbar-PT-5b-LTLCardinality-10
[[35mlola[0m][I] time limit : 1778 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 205/219 1/5 DLCflexbar-PT-5b-LTLCardinality-02 21562 m, 144 m/sec, 63932 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 5/1778 2/5 DLCflexbar-PT-5b-LTLCardinality-10 34198 m, -237690 m/sec, 37148 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1827 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 210/219 1/5 DLCflexbar-PT-5b-LTLCardinality-02 22346 m, 156 m/sec, 66597 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 10/177 2/5 DLCflexbar-PT-5b-LTLCardinality-10 67258 m, 6612 m/sec, 73139 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1832 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 215/219 1/5 DLCflexbar-PT-5b-LTLCardinality-02 23280 m, 186 m/sec, 69701 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 15/177 3/5 DLCflexbar-PT-5b-LTLCardinality-10 98363 m, 6221 m/sec, 107015 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1837 secs. Pages in use: 104
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 7 (type EXCL) for DLCflexbar-PT-5b-LTLCardinality-02 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 20/177 4/5 DLCflexbar-PT-5b-LTLCardinality-10 130449 m, 6417 m/sec, 141954 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1842 secs. Pages in use: 105
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 DLCflexbar-PT-5b-LTLCardinality-02
[[35mlola[0m][I] time limit : 1758 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 5/1758 1/5 DLCflexbar-PT-5b-LTLCardinality-02 1184 m, -4419 m/sec, 1456 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 25/197 4/5 DLCflexbar-PT-5b-LTLCardinality-10 157784 m, 5467 m/sec, 171692 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1847 secs. Pages in use: 107
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 10/1758 1/5 DLCflexbar-PT-5b-LTLCardinality-02 1461 m, 55 m/sec, 2106 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 30/177 5/5 DLCflexbar-PT-5b-LTLCardinality-10 184979 m, 5439 m/sec, 201314 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1852 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 15/1758 1/5 DLCflexbar-PT-5b-LTLCardinality-02 1742 m, 56 m/sec, 2776 t fired, .
[[35mlola[0m][.] 31 LTL EXCL 35/177 5/5 DLCflexbar-PT-5b-LTLCardinality-10 212292 m, 5462 m/sec, 231052 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1857 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 31 (type EXCL) for DLCflexbar-PT-5b-LTLCardinality-10 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 20/1758 1/5 DLCflexbar-PT-5b-LTLCardinality-02 2064 m, 64 m/sec, 3548 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1862 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 25/195 1/5 DLCflexbar-PT-5b-LTLCardinality-02 2416 m, 70 m/sec, 4404 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1867 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 30/195 1/5 DLCflexbar-PT-5b-LTLCardinality-02 2699 m, 56 m/sec, 5075 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1872 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 35/195 1/5 DLCflexbar-PT-5b-LTLCardinality-02 3001 m, 60 m/sec, 5781 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1877 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 40/195 1/5 DLCflexbar-PT-5b-LTLCardinality-02 3338 m, 67 m/sec, 6575 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1882 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 45/195 1/5 DLCflexbar-PT-5b-LTLCardinality-02 3619 m, 56 m/sec, 7259 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1887 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 50/195 1/5 DLCflexbar-PT-5b-LTLCardinality-02 3926 m, 61 m/sec, 7999 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1892 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 55/195 1/5 DLCflexbar-PT-5b-LTLCardinality-02 4287 m, 72 m/sec, 8885 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1897 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 60/195 1/5 DLCflexbar-PT-5b-LTLCardinality-02 4573 m, 57 m/sec, 9558 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1902 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 65/195 1/5 DLCflexbar-PT-5b-LTLCardinality-02 4864 m, 58 m/sec, 10240 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1907 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 70/195 1/5 DLCflexbar-PT-5b-LTLCardinality-02 5179 m, 63 m/sec, 10993 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1912 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 75/195 1/5 DLCflexbar-PT-5b-LTLCardinality-02 5485 m, 61 m/sec, 11725 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1917 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 80/195 1/5 DLCflexbar-PT-5b-LTLCardinality-02 5800 m, 63 m/sec, 12489 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1922 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 85/195 1/5 DLCflexbar-PT-5b-LTLCardinality-02 6114 m, 62 m/sec, 13237 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1927 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 90/195 1/5 DLCflexbar-PT-5b-LTLCardinality-02 6384 m, 54 m/sec, 13867 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1932 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 95/195 1/5 DLCflexbar-PT-5b-LTLCardinality-02 6693 m, 61 m/sec, 14589 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1937 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 100/195 1/5 DLCflexbar-PT-5b-LTLCardinality-02 6985 m, 58 m/sec, 15308 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1942 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 105/195 1/5 DLCflexbar-PT-5b-LTLCardinality-02 7289 m, 60 m/sec, 16033 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1947 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 110/195 1/5 DLCflexbar-PT-5b-LTLCardinality-02 7638 m, 69 m/sec, 16893 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1952 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 115/195 1/5 DLCflexbar-PT-5b-LTLCardinality-02 7983 m, 69 m/sec, 17671 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1957 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 120/195 1/5 DLCflexbar-PT-5b-LTLCardinality-02 8469 m, 97 m/sec, 19400 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1962 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 125/195 1/5 DLCflexbar-PT-5b-LTLCardinality-02 9097 m, 125 m/sec, 21552 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1967 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 130/195 1/5 DLCflexbar-PT-5b-LTLCardinality-02 9813 m, 143 m/sec, 24020 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1972 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 135/195 1/5 DLCflexbar-PT-5b-LTLCardinality-02 10512 m, 139 m/sec, 26382 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1977 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 140/195 1/5 DLCflexbar-PT-5b-LTLCardinality-02 11303 m, 158 m/sec, 29046 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1982 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 145/195 1/5 DLCflexbar-PT-5b-LTLCardinality-02 12040 m, 147 m/sec, 31572 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1987 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 150/195 1/5 DLCflexbar-PT-5b-LTLCardinality-02 12810 m, 154 m/sec, 34201 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1992 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 155/195 1/5 DLCflexbar-PT-5b-LTLCardinality-02 13555 m, 149 m/sec, 36701 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1997 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 160/195 1/5 DLCflexbar-PT-5b-LTLCardinality-02 14291 m, 147 m/sec, 39176 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2002 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 165/195 1/5 DLCflexbar-PT-5b-LTLCardinality-02 14936 m, 129 m/sec, 41401 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2007 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 170/195 1/5 DLCflexbar-PT-5b-LTLCardinality-02 15598 m, 132 m/sec, 43659 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2012 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 175/195 1/5 DLCflexbar-PT-5b-LTLCardinality-02 16401 m, 160 m/sec, 46359 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2017 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 180/195 1/5 DLCflexbar-PT-5b-LTLCardinality-02 17168 m, 153 m/sec, 48950 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2022 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 185/195 1/5 DLCflexbar-PT-5b-LTLCardinality-02 17931 m, 152 m/sec, 51507 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2027 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 190/195 1/5 DLCflexbar-PT-5b-LTLCardinality-02 18557 m, 125 m/sec, 53691 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2032 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 195/195 1/5 DLCflexbar-PT-5b-LTLCardinality-02 19249 m, 138 m/sec, 56056 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2037 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 7 (type EXCL) for DLCflexbar-PT-5b-LTLCardinality-02 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2042 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 28 (type EXCL) for 27 DLCflexbar-PT-5b-LTLCardinality-09
[[35mlola[0m][I] time limit : 194 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 DLCflexbar-PT-5b-LTLCardinality-02
[[35mlola[0m][I] time limit : 1558 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 5/1558 1/5 DLCflexbar-PT-5b-LTLCardinality-02 1168 m, -3616 m/sec, 1419 t fired, .
[[35mlola[0m][.] 28 LTL EXCL 5/194 1/2000 DLCflexbar-PT-5b-LTLCardinality-09 24311 m, 4862 m/sec, 26358 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2047 secs. Pages in use: 109
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 10/1558 1/5 DLCflexbar-PT-5b-LTLCardinality-02 1429 m, 52 m/sec, 2028 t fired, .
[[35mlola[0m][.] 28 LTL EXCL 10/173 2/2000 DLCflexbar-PT-5b-LTLCardinality-09 48800 m, 4897 m/sec, 53022 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2052 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 15/1558 1/5 DLCflexbar-PT-5b-LTLCardinality-02 1689 m, 52 m/sec, 2642 t fired, .
[[35mlola[0m][.] 28 LTL EXCL 15/173 2/2000 DLCflexbar-PT-5b-LTLCardinality-09 73259 m, 4891 m/sec, 79684 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2057 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 20/1558 1/5 DLCflexbar-PT-5b-LTLCardinality-02 1967 m, 55 m/sec, 3314 t fired, .
[[35mlola[0m][.] 28 LTL EXCL 20/173 3/2000 DLCflexbar-PT-5b-LTLCardinality-09 97595 m, 4867 m/sec, 106171 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2062 secs. Pages in use: 111
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 25/1558 1/5 DLCflexbar-PT-5b-LTLCardinality-02 2248 m, 56 m/sec, 3993 t fired, .
[[35mlola[0m][.] 28 LTL EXCL 25/173 3/2000 DLCflexbar-PT-5b-LTLCardinality-09 122259 m, 4932 m/sec, 133051 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2067 secs. Pages in use: 111
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 30/1558 1/5 DLCflexbar-PT-5b-LTLCardinality-02 2512 m, 52 m/sec, 4637 t fired, .
[[35mlola[0m][.] 28 LTL EXCL 30/173 4/2000 DLCflexbar-PT-5b-LTLCardinality-09 146401 m, 4828 m/sec, 159303 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2072 secs. Pages in use: 112
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 35/1558 1/5 DLCflexbar-PT-5b-LTLCardinality-02 2765 m, 50 m/sec, 5232 t fired, .
[[35mlola[0m][.] 28 LTL EXCL 35/173 5/2000 DLCflexbar-PT-5b-LTLCardinality-09 170648 m, 4849 m/sec, 185712 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2077 secs. Pages in use: 113
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 40/1558 1/5 DLCflexbar-PT-5b-LTLCardinality-02 2997 m, 46 m/sec, 5773 t fired, .
[[35mlola[0m][.] 28 LTL EXCL 40/173 5/2000 DLCflexbar-PT-5b-LTLCardinality-09 195107 m, 4891 m/sec, 212336 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2082 secs. Pages in use: 113
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 45/1558 1/5 DLCflexbar-PT-5b-LTLCardinality-02 3228 m, 46 m/sec, 6309 t fired, .
[[35mlola[0m][.] 28 LTL EXCL 45/173 6/2000 DLCflexbar-PT-5b-LTLCardinality-09 219217 m, 4822 m/sec, 238588 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2087 secs. Pages in use: 114
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 50/1558 1/5 DLCflexbar-PT-5b-LTLCardinality-02 3487 m, 51 m/sec, 6935 t fired, .
[[35mlola[0m][.] 28 LTL EXCL 50/173 6/2000 DLCflexbar-PT-5b-LTLCardinality-09 243466 m, 4849 m/sec, 264995 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2092 secs. Pages in use: 114
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 55/1558 1/5 DLCflexbar-PT-5b-LTLCardinality-02 3729 m, 48 m/sec, 7521 t fired, .
[[35mlola[0m][.] 28 LTL EXCL 55/173 7/2000 DLCflexbar-PT-5b-LTLCardinality-09 268097 m, 4926 m/sec, 291819 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2097 secs. Pages in use: 115
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 60/1558 1/5 DLCflexbar-PT-5b-LTLCardinality-02 3974 m, 49 m/sec, 8114 t fired, .
[[35mlola[0m][.] 28 LTL EXCL 60/173 7/2000 DLCflexbar-PT-5b-LTLCardinality-09 292221 m, 4824 m/sec, 318071 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2102 secs. Pages in use: 115
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 65/1558 1/5 DLCflexbar-PT-5b-LTLCardinality-02 4253 m, 55 m/sec, 8802 t fired, .
[[35mlola[0m][.] 28 LTL EXCL 65/173 8/2000 DLCflexbar-PT-5b-LTLCardinality-09 316947 m, 4945 m/sec, 344991 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2107 secs. Pages in use: 116
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 70/1558 1/5 DLCflexbar-PT-5b-LTLCardinality-02 4509 m, 51 m/sec, 9413 t fired, .
[[35mlola[0m][.] 28 LTL EXCL 70/173 8/2000 DLCflexbar-PT-5b-LTLCardinality-09 342197 m, 5050 m/sec, 372476 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2112 secs. Pages in use: 117
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 75/1558 1/5 DLCflexbar-PT-5b-LTLCardinality-02 4747 m, 47 m/sec, 9963 t fired, .
[[35mlola[0m][.] 28 LTL EXCL 75/173 9/2000 DLCflexbar-PT-5b-LTLCardinality-09 366601 m, 4880 m/sec, 399049 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2117 secs. Pages in use: 118
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 80/1558 1/5 DLCflexbar-PT-5b-LTLCardinality-02 4997 m, 50 m/sec, 10557 t fired, .
[[35mlola[0m][.] 28 LTL EXCL 80/173 9/2000 DLCflexbar-PT-5b-LTLCardinality-09 390990 m, 4877 m/sec, 425605 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2122 secs. Pages in use: 118
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 85/1558 1/5 DLCflexbar-PT-5b-LTLCardinality-02 5250 m, 50 m/sec, 11165 t fired, .
[[35mlola[0m][.] 28 LTL EXCL 85/173 10/2000 DLCflexbar-PT-5b-LTLCardinality-09 415780 m, 4958 m/sec, 452591 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2127 secs. Pages in use: 120
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 90/1558 1/5 DLCflexbar-PT-5b-LTLCardinality-02 5485 m, 47 m/sec, 11725 t fired, .
[[35mlola[0m][.] 28 LTL EXCL 90/173 10/2000 DLCflexbar-PT-5b-LTLCardinality-09 440634 m, 4970 m/sec, 479655 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2132 secs. Pages in use: 120
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 95/1558 1/5 DLCflexbar-PT-5b-LTLCardinality-02 5750 m, 53 m/sec, 12364 t fired, .
[[35mlola[0m][.] 28 LTL EXCL 95/173 11/2000 DLCflexbar-PT-5b-LTLCardinality-09 465695 m, 5012 m/sec, 506930 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2137 secs. Pages in use: 121
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 100/1558 1/5 DLCflexbar-PT-5b-LTLCardinality-02 6007 m, 51 m/sec, 12995 t fired, .
[[35mlola[0m][.] 28 LTL EXCL 100/173 11/2000 DLCflexbar-PT-5b-LTLCardinality-09 490102 m, 4881 m/sec, 533499 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2142 secs. Pages in use: 121
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 105/1558 1/5 DLCflexbar-PT-5b-LTLCardinality-02 6225 m, 43 m/sec, 13496 t fired, .
[[35mlola[0m][.] 28 LTL EXCL 105/173 12/2000 DLCflexbar-PT-5b-LTLCardinality-09 514191 m, 4817 m/sec, 559721 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2147 secs. Pages in use: 122
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 110/1558 1/5 DLCflexbar-PT-5b-LTLCardinality-02 6454 m, 45 m/sec, 14030 t fired, .
[[35mlola[0m][.] 28 LTL EXCL 110/173 12/2000 DLCflexbar-PT-5b-LTLCardinality-09 539001 m, 4962 m/sec, 586734 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2152 secs. Pages in use: 122
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-04: AG false findpath[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-5b-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-5b-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-5b-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-5b"
export BK_EXAMINATION="LTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is DLCflexbar-PT-5b, examination is LTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r115-smll-171624276300059"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-5b.tgz
mv DLCflexbar-PT-5b execution
cd execution
if [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "UpperBounds" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] || [ "LTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;