Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r115-smll-171624276300050.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is DLCflexbar-PT-5a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r115-smll-171624276300050
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 3.2M
-rw-r--r-- 1 mcc users 5.9K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 62K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.0K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 56K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Apr 22 14:37 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Apr 22 14:37 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Apr 22 14:37 LTLFireability.txt
-rw-r--r-- 1 mcc users 20K Apr 22 14:37 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Apr 12 17:57 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 105K Apr 12 17:57 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Apr 12 16:42 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 94K Apr 12 16:42 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 22 14:37 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Apr 22 14:37 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 3 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 2.8M May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCflexbar-PT-5a-CTLFireability-2024-00
FORMULA_NAME DLCflexbar-PT-5a-CTLFireability-2024-01
FORMULA_NAME DLCflexbar-PT-5a-CTLFireability-2024-02
FORMULA_NAME DLCflexbar-PT-5a-CTLFireability-2024-03
FORMULA_NAME DLCflexbar-PT-5a-CTLFireability-2024-04
FORMULA_NAME DLCflexbar-PT-5a-CTLFireability-2024-05
FORMULA_NAME DLCflexbar-PT-5a-CTLFireability-2024-06
FORMULA_NAME DLCflexbar-PT-5a-CTLFireability-2024-07
FORMULA_NAME DLCflexbar-PT-5a-CTLFireability-2024-08
FORMULA_NAME DLCflexbar-PT-5a-CTLFireability-2024-09
FORMULA_NAME DLCflexbar-PT-5a-CTLFireability-2024-10
FORMULA_NAME DLCflexbar-PT-5a-CTLFireability-2024-11
FORMULA_NAME DLCflexbar-PT-5a-CTLFireability-2023-12
FORMULA_NAME DLCflexbar-PT-5a-CTLFireability-2023-13
FORMULA_NAME DLCflexbar-PT-5a-CTLFireability-2023-14
FORMULA_NAME DLCflexbar-PT-5a-CTLFireability-2023-15

=== Now, execution of the tool begins

BK_START 1717020196449

FORMULA DLCflexbar-PT-5a-CTLFireability-2024-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1717021303709

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains place/transition net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading formula.
[lola][I] Using XML format (--xmlformula)
[lola][I] reading XML formula
[lola][I] reading formula from CTLFireability.xml
[lola][I] Rule S: 0 transitions removed,0 places removed
[lola][I] NOTDEADLOCKFREE
[lola][I] LAUNCH task # 48 (type SKEL/SRCH) for 9 DLCflexbar-PT-5a-CTLFireability-2024-03
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] NOTDEADLOCKFREE
[lola][I] LAUNCH task # 49 (type SKEL/SRCH) for 30 DLCflexbar-PT-5a-CTLFireability-2024-10
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-02: EFAG 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-03: CTL 0 0 1 0 0 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-07: AGEF 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-10: CTL 0 0 1 0 0 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2023-14: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL SRCH 3/3595 1/5 DLCflexbar-PT-5a-CTLFireability-2024-03 128472 m, 25694 m/sec, 945931 t fired, .
[lola][.] 49 CTL SRCH 1/3593 1/5 DLCflexbar-PT-5a-CTLFireability-2024-10 116522 m, 23304 m/sec, 359691 t fired, .
[lola][.]
[lola][.] Time elapsed: 8 secs. Pages in use: 2
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-02: EFAG 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-03: CTL 0 0 1 0 0 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-07: AGEF 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-10: CTL 0 0 1 0 0 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2023-14: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL SRCH 8/3595 1/5 DLCflexbar-PT-5a-CTLFireability-2024-03 302961 m, 34897 m/sec, 1974597 t fired, .
[lola][.] 49 CTL SRCH 6/3593 1/5 DLCflexbar-PT-5a-CTLFireability-2024-10 400217 m, 56739 m/sec, 1259157 t fired, .
[lola][.]
[lola][.] Time elapsed: 13 secs. Pages in use: 2
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-00: CTL 1 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-02: EFAG 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-03: CTL 0 0 1 0 0 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-07: AGEF 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-10: CTL 0 0 1 0 0 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2023-14: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL SRCH 13/3595 1/5 DLCflexbar-PT-5a-CTLFireability-2024-03 396307 m, 18669 m/sec, 2387726 t fired, .
[lola][.] 49 CTL SRCH 11/3593 1/5 DLCflexbar-PT-5a-CTLFireability-2024-10 514410 m, 22838 m/sec, 1629185 t fired, .
[lola][.]
[lola][.] Time elapsed: 18 secs. Pages in use: 2
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I] LAUNCH task # 1 (type EXCL) for 0 DLCflexbar-PT-5a-CTLFireability-2024-00
[lola][I] time limit : 238 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 57 (type EQUN) for 21 DLCflexbar-PT-5a-CTLFireability-2024-07
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 1 (type EXCL) for DLCflexbar-PT-5a-CTLFireability-2024-00
[lola][I] result : false
[lola][I] markings : 72
[lola][I] fired transitions : 5490
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 50 (type EXCL) for 21 DLCflexbar-PT-5a-CTLFireability-2024-07
[lola][I] time limit : 238 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 57 (type EQUN) for DLCflexbar-PT-5a-CTLFireability-2024-07
[lola][I] result : unknown
[lola][I] LAUNCH task # 58 (type EQUN) for 6 DLCflexbar-PT-5a-CTLFireability-2024-02
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-00: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-02: EFAG 0 2 1 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-03: CTL 0 0 1 0 0 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-05: CTL 1 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-07: AGEF 0 1 1 0 2 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-10: CTL 0 0 1 0 0 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2023-14: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL SRCH 18/3577 1/5 DLCflexbar-PT-5a-CTLFireability-2024-03 566109 m, 33960 m/sec, 3167770 t fired, .
[lola][.] 49 CTL SRCH 16/1780 1/5 DLCflexbar-PT-5a-CTLFireability-2024-10 715976 m, 40313 m/sec, 2248952 t fired, .
[lola][.] 50 AGEF EXCL 1/238 1/2000 DLCflexbar-PT-5a-CTLFireability-2024-07 2119 m, 423 m/sec, 282065 t fired, .
[lola][.] 58 EF STEQ 0/1788 0/5 DLCflexbar-PT-5a-CTLFireability-2024-02 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 23 secs. Pages in use: 3
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I] FINISHED task # 58 (type EQUN) for DLCflexbar-PT-5a-CTLFireability-2024-02
[lola][I] result : true
[lola][I] LAUNCH task # 62 (type EQUN) for 6 DLCflexbar-PT-5a-CTLFireability-2024-02
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-00: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-02: EFAG 0 1 1 0 2 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-03: CTL 1 0 1 0 0 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-07: AGEF 0 1 1 0 2 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-10: CTL 0 1 1 0 0 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2023-14: CTL 1 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL SRCH 25/3570 1/5 DLCflexbar-PT-5a-CTLFireability-2024-03 1332969 m, 153372 m/sec, 6830133 t fired, .
[lola][.] 49 CTL SRCH 23/3570 1/5 DLCflexbar-PT-5a-CTLFireability-2024-10 1638159 m, 184436 m/sec, 5134266 t fired, .
[lola][.] 50 AGEF EXCL 8/238 1/2000 DLCflexbar-PT-5a-CTLFireability-2024-07 28067 m, 5189 m/sec, 3778325 t fired, .
[lola][.] 62 EF STEQ 3/1783 0/5 DLCflexbar-PT-5a-CTLFireability-2024-02 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 30 secs. Pages in use: 3
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I] FINISHED task # 62 (type EQUN) for DLCflexbar-PT-5a-CTLFireability-2024-02
[lola][I] result : unknown
[lola][I] LAUNCH task # 60 (type EQUN) for 21 DLCflexbar-PT-5a-CTLFireability-2024-07
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 60 (type EQUN) for DLCflexbar-PT-5a-CTLFireability-2024-07
[lola][I] result : true
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
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[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-07: AGEF 0 0 1 0 3 0 0 0
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[lola][.] DLCflexbar-PT-5a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[lola][.] 48 CTL SRCH 30/3595 1/5 DLCflexbar-PT-5a-CTLFireability-2024-03 2196293 m, 172664 m/sec, 10998817 t fired, .
[lola][.] 49 CTL SRCH 28/3593 1/5 DLCflexbar-PT-5a-CTLFireability-2024-10 2101138 m, 92595 m/sec, 8833401 t fired, .
[lola][.] 50 AGEF EXCL 13/238 1/2000 DLCflexbar-PT-5a-CTLFireability-2024-07 50279 m, 4442 m/sec, 6874856 t fired, .
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[lola][I] FINISHED task # 49 (type SKEL/SRCH) for DLCflexbar-PT-5a-CTLFireability-2024-10
[lola][I] result : false
[lola][I] markings : 2111632
[lola][I] fired transitions : 8864156
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[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-00: CTL false CTL model checker
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[lola][.] DLCflexbar-PT-5a-CTLFireability-2024-07: AGEF 0 0 1 0 3 0 0 0
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[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL SRCH 35/3595 1/5 DLCflexbar-PT-5a-CTLFireability-2024-03 3270530 m, 214847 m/sec, 16283139 t fired, .
[lola][.] 50 AGEF EXCL 18/238 1/2000 DLCflexbar-PT-5a-CTLFireability-2024-07 76906 m, 5325 m/sec, 10523655 t fired, .
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[lola][.] 48 CTL SRCH 40/3595 1/5 DLCflexbar-PT-5a-CTLFireability-2024-03 4312261 m, 208346 m/sec, 21374805 t fired, .
[lola][.] 50 AGEF EXCL 23/238 1/2000 DLCflexbar-PT-5a-CTLFireability-2024-07 103186 m, 5256 m/sec, 14142016 t fired, .
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[lola][.] 48 CTL SRCH 45/3595 1/5 DLCflexbar-PT-5a-CTLFireability-2024-03 5401071 m, 217762 m/sec, 26524444 t fired, .
[lola][.] 50 AGEF EXCL 28/238 1/2000 DLCflexbar-PT-5a-CTLFireability-2024-07 129074 m, 5177 m/sec, 17734141 t fired, .
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[lola][.] 48 CTL SRCH 50/3595 1/5 DLCflexbar-PT-5a-CTLFireability-2024-03 6391354 m, 198056 m/sec, 31402337 t fired, .
[lola][.] 50 AGEF EXCL 33/238 1/2000 DLCflexbar-PT-5a-CTLFireability-2024-07 154835 m, 5152 m/sec, 21324680 t fired, .
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[lola][.] 48 CTL SRCH 55/3595 1/5 DLCflexbar-PT-5a-CTLFireability-2024-03 7428091 m, 207347 m/sec, 36179166 t fired, .
[lola][.] 50 AGEF EXCL 38/238 1/2000 DLCflexbar-PT-5a-CTLFireability-2024-07 180326 m, 5098 m/sec, 24896688 t fired, .
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[lola][.] 48 CTL SRCH 60/3595 1/5 DLCflexbar-PT-5a-CTLFireability-2024-03 8415334 m, 197448 m/sec, 40809299 t fired, .
[lola][.] 50 AGEF EXCL 43/238 1/2000 DLCflexbar-PT-5a-CTLFireability-2024-07 206398 m, 5214 m/sec, 28548858 t fired, .
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[lola][.] 48 CTL SRCH 65/3595 1/5 DLCflexbar-PT-5a-CTLFireability-2024-03 9352903 m, 187513 m/sec, 45391299 t fired, .
[lola][.] 50 AGEF EXCL 48/238 2/2000 DLCflexbar-PT-5a-CTLFireability-2024-07 231969 m, 5114 m/sec, 32170208 t fired, .
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[lola][.] 48 CTL SRCH 70/3595 1/5 DLCflexbar-PT-5a-CTLFireability-2024-03 10299011 m, 189221 m/sec, 50175209 t fired, .
[lola][.] 50 AGEF EXCL 53/238 2/2000 DLCflexbar-PT-5a-CTLFireability-2024-07 257408 m, 5087 m/sec, 35727106 t fired, .
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[lola][I] FINISHED task # 48 (type SKEL/SRCH) for DLCflexbar-PT-5a-CTLFireability-2024-03
[lola][I] result : true
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[lola][.] 50 AGEF EXCL 58/238 2/2000 DLCflexbar-PT-5a-CTLFireability-2024-07 282752 m, 5068 m/sec, 39303792 t fired, .
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[lola][.] 50 AGEF EXCL 108/238 3/2000 DLCflexbar-PT-5a-CTLFireability-2024-07 547035 m, 5211 m/sec, 76844734 t fired, .
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[lola][.] 50 AGEF EXCL 113/238 3/2000 DLCflexbar-PT-5a-CTLFireability-2024-07 571578 m, 4908 m/sec, 80375549 t fired, .
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[lola][.] 50 AGEF EXCL 118/238 3/2000 DLCflexbar-PT-5a-CTLFireability-2024-07 597490 m, 5182 m/sec, 84081833 t fired, .
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[lola][.] 50 AGEF EXCL 123/238 3/2000 DLCflexbar-PT-5a-CTLFireability-2024-07 623239 m, 5149 m/sec, 87771208 t fired, .
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[lola][.] 50 AGEF EXCL 128/238 3/2000 DLCflexbar-PT-5a-CTLFireability-2024-07 648769 m, 5106 m/sec, 91447698 t fired, .
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[lola][.] 50 AGEF EXCL 133/238 4/2000 DLCflexbar-PT-5a-CTLFireability-2024-07 674278 m, 5101 m/sec, 95127003 t fired, .
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[lola][.] 50 AGEF EXCL 163/238 4/2000 DLCflexbar-PT-5a-CTLFireability-2024-07 830326 m, 5174 m/sec, 117396104 t fired, .
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[lola][.] 50 AGEF EXCL 168/238 4/2000 DLCflexbar-PT-5a-CTLFireability-2024-07 855531 m, 5041 m/sec, 121067033 t fired, .
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[lola][.] 50 AGEF EXCL 20/238 1/5 DLCflexbar-PT-5a-CTLFireability-2024-07 110142 m, 5488 m/sec, 15110115 t fired, .
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[lola][.] 50 AGEF EXCL 125/238 4/5 DLCflexbar-PT-5a-CTLFireability-2024-07 657379 m, 5123 m/sec, 92685359 t fired, .
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[lola][.] 50 AGEF EXCL 130/238 4/5 DLCflexbar-PT-5a-CTLFireability-2024-07 683078 m, 5139 m/sec, 96401660 t fired, .
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[lola][.] 50 AGEF EXCL 135/238 4/5 DLCflexbar-PT-5a-CTLFireability-2024-07 709380 m, 5260 m/sec, 100119294 t fired, .
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[lola][.] 50 AGEF EXCL 140/238 4/5 DLCflexbar-PT-5a-CTLFireability-2024-07 734086 m, 4941 m/sec, 103637685 t fired, .
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[lola][.] 50 AGEF EXCL 145/238 4/5 DLCflexbar-PT-5a-CTLFireability-2024-07 760398 m, 5262 m/sec, 107384936 t fired, .
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[lola][.] 50 AGEF EXCL 150/238 4/5 DLCflexbar-PT-5a-CTLFireability-2024-07 786676 m, 5255 m/sec, 111110130 t fired, .
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[lola][.] 40 CTL EXCL 30/240 3/2000 DLCflexbar-PT-5a-CTLFireability-2023-13 457354 m, 15661 m/sec, 15140826 t fired, .
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/home/mcc/BenchKit/BenchKit_head.sh: line 23: 409 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-5a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is DLCflexbar-PT-5a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r115-smll-171624276300050"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-5a.tgz
mv DLCflexbar-PT-5a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;