fond
Model Checking Contest 2024
14th edition, Geneva, Switzerland, June 25, 2024
Execution of r115-smll-171624276300049
Last Updated
July 7, 2024

About the Execution of LoLA for DLCflexbar-PT-5a

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
16207.243 637228.00 685007.00 2186.60 T?F??T?T??F?TF?? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r115-smll-171624276300049.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.....................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is DLCflexbar-PT-5a, examination is CTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r115-smll-171624276300049
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 3.2M
-rw-r--r-- 1 mcc users 5.9K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 62K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.0K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 56K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Apr 22 14:37 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Apr 22 14:37 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Apr 22 14:37 LTLFireability.txt
-rw-r--r-- 1 mcc users 20K Apr 22 14:37 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Apr 12 17:57 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 105K Apr 12 17:57 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Apr 12 16:42 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 94K Apr 12 16:42 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 22 14:37 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Apr 22 14:37 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 3 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 2.8M May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCflexbar-PT-5a-CTLCardinality-2024-00
FORMULA_NAME DLCflexbar-PT-5a-CTLCardinality-2024-01
FORMULA_NAME DLCflexbar-PT-5a-CTLCardinality-2024-02
FORMULA_NAME DLCflexbar-PT-5a-CTLCardinality-2024-03
FORMULA_NAME DLCflexbar-PT-5a-CTLCardinality-2024-04
FORMULA_NAME DLCflexbar-PT-5a-CTLCardinality-2024-05
FORMULA_NAME DLCflexbar-PT-5a-CTLCardinality-2024-06
FORMULA_NAME DLCflexbar-PT-5a-CTLCardinality-2024-07
FORMULA_NAME DLCflexbar-PT-5a-CTLCardinality-2024-08
FORMULA_NAME DLCflexbar-PT-5a-CTLCardinality-2024-09
FORMULA_NAME DLCflexbar-PT-5a-CTLCardinality-2024-10
FORMULA_NAME DLCflexbar-PT-5a-CTLCardinality-2024-11
FORMULA_NAME DLCflexbar-PT-5a-CTLCardinality-2023-12
FORMULA_NAME DLCflexbar-PT-5a-CTLCardinality-2023-13
FORMULA_NAME DLCflexbar-PT-5a-CTLCardinality-2023-14
FORMULA_NAME DLCflexbar-PT-5a-CTLCardinality-2023-15

=== Now, execution of the tool begins

BK_START 1717020010882

FORMULA DLCflexbar-PT-5a-CTLCardinality-2024-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5a-CTLCardinality-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5a-CTLCardinality-2024-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5a-CTLCardinality-2023-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5a-CTLCardinality-2024-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5a-CTLCardinality-2024-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5a-CTLCardinality-2023-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1717020648110

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains place/transition net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading formula.
[lola][I] Using XML format (--xmlformula)
[lola][I] reading XML formula
[lola][I] reading formula from CTLCardinality.xml
[lola][I] Rule S: 0 transitions removed,0 places removed
[lola][I] NOTDEADLOCKFREE
[lola][I] NOTDEADLOCKFREE
[lola][I] LAUNCH task # 7 (type CNST) for 6 DLCflexbar-PT-5a-CTLCardinality-2024-02
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] FINISHED task # 7 (type CNST) for DLCflexbar-PT-5a-CTLCardinality-2024-02
[lola][I] result : false
[lola][I] LAUNCH task # 16 (type CNST) for 15 DLCflexbar-PT-5a-CTLCardinality-2024-05
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] LAUNCH task # 22 (type CNST) for 21 DLCflexbar-PT-5a-CTLCardinality-2024-07
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] FINISHED task # 22 (type CNST) for DLCflexbar-PT-5a-CTLCardinality-2024-07
[lola][I] NOTDEADLOCKFREE
[lola][I] result : true
[lola][I] FINISHED task # 16 (type CNST) for DLCflexbar-PT-5a-CTLCardinality-2024-05
[lola][I] result : true
[lola][I] LAUNCH task # 31 (type CNST) for 30 DLCflexbar-PT-5a-CTLCardinality-2024-10
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] LAUNCH task # 40 (type CNST) for 39 DLCflexbar-PT-5a-CTLCardinality-2023-13
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] FINISHED task # 40 (type CNST) for DLCflexbar-PT-5a-CTLCardinality-2023-13
[lola][I] result : false
[lola][I] FINISHED task # 31 (type CNST) for DLCflexbar-PT-5a-CTLCardinality-2024-10
[lola][I] result : false
[lola][I] NOTDEADLOCKFREE
[lola][I] NOTDEADLOCKFREE
[lola][I] LAUNCH task # 1 (type EXCL) for 0 DLCflexbar-PT-5a-CTLCardinality-2024-00
[lola][I] time limit : 325 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 1 (type EXCL) for DLCflexbar-PT-5a-CTLCardinality-2024-00
[lola][I] result : true
[lola][I] markings : 4
[lola][I] fired transitions : 19
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 48 (type EXCL) for 36 DLCflexbar-PT-5a-CTLCardinality-2023-12
[lola][I] time limit : 358 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 51 (type EQUN) for 36 DLCflexbar-PT-5a-CTLCardinality-2023-12
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 53 (type EQUN) for 36 DLCflexbar-PT-5a-CTLCardinality-2023-12
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 48 (type EXCL) for DLCflexbar-PT-5a-CTLCardinality-2023-12
[lola][I] result : true
[lola][I] markings : 2
[lola][I] fired transitions : 2
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 51 (type EQUN) for DLCflexbar-PT-5a-CTLCardinality-2023-12 (obsolete)
[lola][W] CANCELED task # 53 (type EQUN) for DLCflexbar-PT-5a-CTLCardinality-2023-12 (obsolete)
[lola][I] FINISHED task # 51 (type EQUN) for DLCflexbar-PT-5a-CTLCardinality-2023-12
[lola][I] result : unknown
[lola][I] FINISHED task # 53 (type EQUN) for DLCflexbar-PT-5a-CTLCardinality-2023-12
[lola][I] result : true
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-00: CTL true CTL model checker
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-02: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-05: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-07: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-10: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2023-12: EFEG true state space /EFEG
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2023-14: CTL 0 0 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 18 secs. Pages in use: 1
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I] LAUNCH task # 25 (type EXCL) for 24 DLCflexbar-PT-5a-CTLCardinality-2024-08
[lola][I] time limit : 397 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 25 (type EXCL) for DLCflexbar-PT-5a-CTLCardinality-2024-08
[lola][I] result : true
[lola][I] markings : 2
[lola][I] fired transitions : 6
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 28 (type EXCL) for 27 DLCflexbar-PT-5a-CTLCardinality-2024-09
[lola][I] time limit : 447 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 28 (type EXCL) for DLCflexbar-PT-5a-CTLCardinality-2024-09
[lola][I] result : false
[lola][I] markings : 64
[lola][I] fired transitions : 8468
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 34 (type EXCL) for 33 DLCflexbar-PT-5a-CTLCardinality-2024-11
[lola][I] time limit : 511 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-00: CTL true CTL model checker
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-02: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-05: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-07: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-08: CTL true CTL model checker
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-09: CTL false CTL model checker
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-10: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2023-12: EFEG true state space /EFEG
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 34 CTL EXCL 0/511 1/2000 DLCflexbar-PT-5a-CTLCardinality-2024-11 26859 m, 5371 m/sec, 266981 t fired, .
[lola][.]
[lola][.] Time elapsed: 23 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-00: CTL true CTL model checker
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-02: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-05: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-07: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-08: CTL true CTL model checker
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-09: CTL false CTL model checker
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-10: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2023-12: EFEG true state space /EFEG
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 34 CTL EXCL 5/511 2/2000 DLCflexbar-PT-5a-CTLCardinality-2024-11 234999 m, 41628 m/sec, 2345315 t fired, .
[lola][.]
[lola][.] Time elapsed: 28 secs. Pages in use: 2
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-00: CTL true CTL model checker
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-02: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-05: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-07: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-08: CTL true CTL model checker
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-09: CTL false CTL model checker
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-10: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2023-12: EFEG true state space /EFEG
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 34 CTL EXCL 10/511 3/2000 DLCflexbar-PT-5a-CTLCardinality-2024-11 431082 m, 39216 m/sec, 4420069 t fired, .
[lola][.]
[lola][.] Time elapsed: 33 secs. Pages in use: 3
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-00: CTL true CTL model checker
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-02: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-05: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-07: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-08: CTL true CTL model checker
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-09: CTL false CTL model checker
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-10: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2023-12: EFEG true state space /EFEG
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 34 CTL EXCL 15/511 4/2000 DLCflexbar-PT-5a-CTLCardinality-2024-11 609075 m, 35598 m/sec, 6472662 t fired, .
[lola][.]
[lola][.] Time elapsed: 38 secs. Pages in use: 4
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-00: CTL true CTL model checker
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-02: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-05: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-07: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-08: CTL true CTL model checker
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-09: CTL false CTL model checker
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-10: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2023-12: EFEG true state space /EFEG
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2023-13: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
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[lola][.] 34 CTL EXCL 20/511 4/2000 DLCflexbar-PT-5a-CTLCardinality-2024-11 746902 m, 27565 m/sec, 8567474 t fired, .
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[lola][.] 34 CTL EXCL 25/511 5/2000 DLCflexbar-PT-5a-CTLCardinality-2024-11 910057 m, 32631 m/sec, 10647597 t fired, .
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[lola][.] 34 CTL EXCL 30/511 6/2000 DLCflexbar-PT-5a-CTLCardinality-2024-11 1043148 m, 26618 m/sec, 12748215 t fired, .
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[lola][.] 34 CTL EXCL 35/511 6/2000 DLCflexbar-PT-5a-CTLCardinality-2024-11 1174828 m, 26336 m/sec, 14848454 t fired, .
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[lola][.] 34 CTL EXCL 40/511 7/2000 DLCflexbar-PT-5a-CTLCardinality-2024-11 1319230 m, 28880 m/sec, 16942473 t fired, .
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[lola][.] 34 CTL EXCL 45/511 8/2000 DLCflexbar-PT-5a-CTLCardinality-2024-11 1460475 m, 28249 m/sec, 19025779 t fired, .
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[lola][.] 34 CTL EXCL 125/511 19/2000 DLCflexbar-PT-5a-CTLCardinality-2024-11 3506723 m, 24080 m/sec, 52101968 t fired, .
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[lola][.] 34 CTL EXCL 175/511 24/2000 DLCflexbar-PT-5a-CTLCardinality-2024-11 4564606 m, 18227 m/sec, 72667606 t fired, .
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[lola][.] 34 CTL EXCL 180/511 25/2000 DLCflexbar-PT-5a-CTLCardinality-2024-11 4662566 m, 19592 m/sec, 74665034 t fired, .
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[lola][.] 34 CTL EXCL 190/511 26/2000 DLCflexbar-PT-5a-CTLCardinality-2024-11 4877076 m, 21552 m/sec, 78639710 t fired, .
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[lola][.] 34 CTL EXCL 230/511 30/2000 DLCflexbar-PT-5a-CTLCardinality-2024-11 5671964 m, 18641 m/sec, 94445802 t fired, .
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[lola][.] DLCflexbar-PT-5a-CTLCardinality-2024-08: CTL true CTL model checker
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[lola][.] 34 CTL EXCL 24/3062 5/5 DLCflexbar-PT-5a-CTLCardinality-2024-11 861365 m, 30585 m/sec, 10043252 t fired, .
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[lola][.] 46 CTL EXCL 30/437 1/2000 DLCflexbar-PT-5a-CTLCardinality-2023-15 78576 m, 2736 m/sec, 8841432 t fired, .
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[lola][.] 46 CTL EXCL 75/510 2/2000 DLCflexbar-PT-5a-CTLCardinality-2023-15 201104 m, 2709 m/sec, 22383860 t fired, .
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/home/mcc/BenchKit/BenchKit_head.sh: line 23: 408 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-5a"
export BK_EXAMINATION="CTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is DLCflexbar-PT-5a, examination is CTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r115-smll-171624276300049"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-5a.tgz
mv DLCflexbar-PT-5a execution
cd execution
if [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "UpperBounds" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] || [ "CTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;