MCC'2024- Execution of r115-smll-171624276200044

About the Execution of LoLA for DLCflexbar-PT-4b

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
16207.352	1881326.00	3274700.00	6271.40	???F???F??FFF?F?	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r115-smll-171624276200044.qcow2',
Waiting for the VM to be ready (probing ssh)
........................................................
..................................
========================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is DLCflexbar-PT-4b, examination is LTLFireabi
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r115-smll-171624276200044
========================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 4.6M
-rw-r--r-- 1 mcc users 9.7K May 14 13:22 CTLCardinality.
-rw-r--r-- 1 mcc users 115K May 14 13:22 CTLCardinality.
-rw-r--r-- 1 mcc users 5.5K May 14 13:22 CTLFireability.
-rw-r--r-- 1 mcc users 48K May 14 13:22 CTLFireability.
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericProperti
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericProperti
-rw-r--r-- 1 mcc users 3.4K Apr 22 14:37 LTLCardinality.
-rw-r--r-- 1 mcc users 23K Apr 22 14:37 LTLCardinality.
-rw-r--r-- 1 mcc users 2.2K Apr 22 14:37 LTLFireability.
-rw-r--r-- 1 mcc users 18K Apr 22 14:37 LTLFireability.
-rw-r--r-- 1 mcc users 8.1K Apr 12 12:57 ReachabilityCar
-rw-r--r-- 1 mcc users 78K Apr 12 12:57 ReachabilityCar
-rw-r--r-- 1 mcc users 10K Apr 12 12:56 ReachabilityFir
-rw-r--r-- 1 mcc users 87K Apr 12 12:56 ReachabilityFir
-rw-r--r-- 1 mcc users 1.6K Apr 22 14:37 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Apr 22 14:37 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 3 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 4.1M May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from
FORMULA_NAME DLCflexbar-PT-4b-LTLFireability-00
FORMULA_NAME DLCflexbar-PT-4b-LTLFireability-01
FORMULA_NAME DLCflexbar-PT-4b-LTLFireability-02
FORMULA_NAME DLCflexbar-PT-4b-LTLFireability-03
FORMULA_NAME DLCflexbar-PT-4b-LTLFireability-04
FORMULA_NAME DLCflexbar-PT-4b-LTLFireability-05
FORMULA_NAME DLCflexbar-PT-4b-LTLFireability-06
FORMULA_NAME DLCflexbar-PT-4b-LTLFireability-07
FORMULA_NAME DLCflexbar-PT-4b-LTLFireability-08
FORMULA_NAME DLCflexbar-PT-4b-LTLFireability-09
FORMULA_NAME DLCflexbar-PT-4b-LTLFireability-10
FORMULA_NAME DLCflexbar-PT-4b-LTLFireability-11
FORMULA_NAME DLCflexbar-PT-4b-LTLFireability-12
FORMULA_NAME DLCflexbar-PT-4b-LTLFireability-13
FORMULA_NAME DLCflexbar-PT-4b-LTLFireability-14
FORMULA_NAME DLCflexbar-PT-4b-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1717016568414

FORMULA DLCflexbar-PT-4b-LTLFireability-11
FORMULA DLCflexbar-PT-4b-LTLFireability-03
FORMULA DLCflexbar-PT-4b-LTLFireability-14
FORMULA DLCflexbar-PT-4b-LTLFireability-12
FORMULA DLCflexbar-PT-4b-LTLFireability-10
FORMULA DLCflexbar-PT-4b-LTLFireability-07

BK_STOP 1717018449740

--------------------
content from stderr:

[[35mlola[0m][I] LoLA will run for 3600 seconds
[[35mlola[0m][W] [1m[33munknown unit in memory
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlne
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition
[[35mlola[0m][I] closed [1m[34mnet[0m file
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlfor
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 44 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 49 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible:
[[35mlola[0m][I] Rule S: 0 transitions removed,0
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 54 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 59 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 64 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible:
[[35mlola[0m][I] LAUNCH task # 36 (type CNST)
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 36 (type CNST)
[[35mlola[0m][I] result : false
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 69 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 74 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 79 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 84 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 89 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible:
[*** LOG ERROR #0001 ***] [2024-05-29 21:04:20]
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 94 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 99 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 104 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible:
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL)
[[35mlola[0m][I] time limit : 183 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 10 (type EXCL)
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 109 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 114 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible:
[[35mlola[0m][I] LAUNCH task # 63 (type EXCL)
[[35mlola[0m][I] time limit : 204 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 61 (type FNDP)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 62 (type EQUN)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 57 (type FNDP)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 63 (type EXCL)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][W] CANCELED task # 61 (type FNDP)
[[35mlola[0m][W] CANCELED task # 62 (type EQUN)
[[35mlola[0m][I] LAUNCH task # 59 (type EXCL)
[[35mlola[0m][I] time limit : 232 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 58 (type EQUN)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 61 (type FNDP)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] FINISHED task # 57 (type FNDP)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][W] CANCELED task # 58 (type EQUN)
[[35mlola[0m][W] CANCELED task # 59 (type EXCL)
[[35mlola[0m][I] LAUNCH task # 31 (type EXCL)
[[35mlola[0m][I] time limit : 268 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 31 (type EXCL)
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 22 (type EXCL)
[[35mlola[0m][I] time limit : 290 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 22 (type EXCL)
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 28 (type EXCL)
[[35mlola[0m][I] time limit : 316 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 3/316
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 119 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] FINISHED task # 58 (type EQUN)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 62 (type EQUN)
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 8/316
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 124 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 13/316
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 129 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[*** LOG ERROR #0002 ***] [2024-05-29 21:05:02]
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 18/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 134 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 23/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 139 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 28/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 144 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 33/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 149 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 38/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 154 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 43/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 159 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 48/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 164 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 53/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 169 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 58/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 174 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 63/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 179 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 68/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 184 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 73/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 189 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 78/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 194 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 83/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 199 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 88/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 204 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 93/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 209 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 98/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 214 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 103/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 219 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 108/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 224 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 113/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 229 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 118/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 234 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 123/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 239 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 128/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 244 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 133/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 249 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 138/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 254 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 143/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 259 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 148/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 264 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 153/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 269 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 158/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 274 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 163/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 279 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 168/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 284 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 173/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 289 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 178/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 294 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 183/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 299 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 188/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 304 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 193/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 309 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 198/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 314 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 203/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 319 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 208/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 324 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 213/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 329 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 218/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 334 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 223/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 339 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 228/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 344 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 233/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 349 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 238/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 354 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 243/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 359 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 248/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 364 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 253/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 369 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 258/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 374 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 263/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 379 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 268/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 384 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 273/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 389 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 278/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 394 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 283/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 399 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 288/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 404 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 293/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 409 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 298/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 414 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 303/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 419 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 308/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 424 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 313/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 429 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 318/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 434 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 323/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 439 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 328/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 444 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 333/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 449 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 338/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 454 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 343/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 459 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 348/348
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 464 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][W] CANCELED task # 28 (type EXCL)
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 469 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] LAUNCH task # 54 (type EXCL)
[[35mlola[0m][I] time limit : 347 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 28 (type EXCL)
[[35mlola[0m][I] time limit : 3131 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 5/3131
[[35mlola[0m][.] 54 LTL EXCL 5/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 474 secs.
[[35mlola[0m][.] # running tasks: 2 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 10/3131
[[35mlola[0m][.] 54 LTL EXCL 10/313
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 479 secs.
[[35mlola[0m][.] # running tasks: 2 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 15/3131
[[35mlola[0m][.] 54 LTL EXCL 15/313
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 484 secs.
[[35mlola[0m][.] # running tasks: 2 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 20/3131
[[35mlola[0m][.] 54 LTL EXCL 20/313
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 489 secs.
[[35mlola[0m][.] # running tasks: 2 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 25/3131
[[35mlola[0m][.] 54 LTL EXCL 25/313
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 494 secs.
[[35mlola[0m][.] # running tasks: 2 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 30/3131
[[35mlola[0m][.] 54 LTL EXCL 30/313
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 499 secs.
[[35mlola[0m][.] # running tasks: 2 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 35/3131
[[35mlola[0m][.] 54 LTL EXCL 35/313
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 504 secs.
[[35mlola[0m][.] # running tasks: 2 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 40/3131
[[35mlola[0m][.] 54 LTL EXCL 40/313
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 509 secs.
[[35mlola[0m][.] # running tasks: 2 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 45/3131
[[35mlola[0m][.] 54 LTL EXCL 45/313
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 514 secs.
[[35mlola[0m][.] # running tasks: 2 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 50/3131
[[35mlola[0m][.] 54 LTL EXCL 50/313
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 519 secs.
[[35mlola[0m][.] # running tasks: 2 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 55/3131
[[35mlola[0m][.] 54 LTL EXCL 55/313
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 524 secs.
[[35mlola[0m][.] # running tasks: 2 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 28 LTL EXCL 60/3131
[[35mlola[0m][.] 54 LTL EXCL 60/313
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 529 secs.
[[35mlola[0m][.] # running tasks: 2 of 4. Visible:
[[35mlola[0m][I] CANCELED task # 28 (type EXCL)
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 65/313
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 534 secs.
[[35mlola[0m][.] # running tasks: 2 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 70/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 539 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 75/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 544 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 80/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 549 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 85/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 554 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 90/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 559 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 95/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 564 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 100/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 569 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 105/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 574 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 110/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 579 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 115/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 584 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 120/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 589 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 125/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 594 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 130/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 599 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 135/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 604 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 140/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 609 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 145/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 614 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 150/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 619 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 155/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 624 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 160/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 629 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 165/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 634 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 170/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 639 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 175/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 644 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 180/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 649 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 185/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 654 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 190/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 659 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 195/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 664 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 200/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 669 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 205/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 674 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 210/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 679 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 215/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 684 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 220/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 689 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 225/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 694 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 230/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 699 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 235/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 704 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 240/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 709 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 245/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 714 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 250/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 719 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 255/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 724 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 260/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 729 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 265/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 734 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 270/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 739 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 275/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 744 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 280/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 749 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 285/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 754 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 290/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 759 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 295/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 764 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 300/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 769 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 305/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 774 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 310/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 779 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 315/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 784 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 320/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 789 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 325/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 794 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 330/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 799 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 335/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 804 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 340/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 809 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 345/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 814 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][W] CANCELED task # 54 (type EXCL)
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 819 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] LAUNCH task # 48 (type EXCL)
[[35mlola[0m][I] time limit : 347 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 54 (type EXCL)
[[35mlola[0m][I] time limit : 2781 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 48 (type EXCL)
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 5/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 824 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 54 LTL EXCL 10/347
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 829 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] CANCELED task # 54 (type EXCL)
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 834 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] LAUNCH task # 25 (type EXCL)
[[35mlola[0m][I] time limit : 395 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 25 (type EXCL)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 16 (type EXCL)
[[35mlola[0m][I] time limit : 461 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 5/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 839 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 10/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 844 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 15/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 849 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 20/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 854 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 25/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 859 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 30/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 864 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 35/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 869 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 40/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 874 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 45/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 879 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 50/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 884 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 55/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 889 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 60/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 894 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 65/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 899 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 70/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 904 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 75/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 909 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 80/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 914 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 85/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 919 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 90/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 924 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 95/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 929 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 100/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 934 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 105/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 939 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 110/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 944 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 115/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 949 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 120/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 954 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 125/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 959 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 130/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 964 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 135/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 969 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 140/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 974 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 145/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 979 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 150/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 984 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 155/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 989 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 160/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 994 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 165/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 999 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 170/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1004 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 175/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1009 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 180/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1014 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 185/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1019 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 190/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1024 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 195/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1029 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 200/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1034 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 205/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1039 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 210/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1044 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 215/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1049 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 220/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1054 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 225/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1059 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 230/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1064 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 235/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1069 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 240/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1074 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 245/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1079 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 250/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1084 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 255/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1089 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 260/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1094 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 265/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1099 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 270/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1104 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 275/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1109 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 280/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1114 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 285/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1119 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 290/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1124 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 295/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1129 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 300/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1134 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 305/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1139 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 310/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1144 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 315/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1149 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 320/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1154 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 325/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1159 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 330/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1164 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 335/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1169 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 340/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1174 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 345/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1179 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 350/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1184 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 355/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1189 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 360/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1194 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 365/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1199 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 370/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1204 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 375/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1209 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 380/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1214 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 385/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1219 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 390/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1224 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 395/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1229 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 400/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1234 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 405/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1239 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 410/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1244 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 415/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1249 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 420/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1254 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 425/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1259 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 430/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1264 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 435/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1269 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 440/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1274 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 445/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1279 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 450/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1284 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 455/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1289 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 460/461
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1294 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][W] CANCELED task # 16 (type EXCL)
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1299 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] LAUNCH task # 13 (type EXCL)
[[35mlola[0m][I] time limit : 460 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 16 (type EXCL)
[[35mlola[0m][I] time limit : 2301 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 13 (type EXCL)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 5/460
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1304 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 10/460
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1309 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] CANCELED task # 16 (type EXCL)
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1314 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL)
[[35mlola[0m][I] time limit : 571 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 7 LTL EXCL 5/571
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1319 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] FINISHED task # 7 (type EXCL)
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL)
[[35mlola[0m][I] time limit : 759 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 4 (type EXCL)
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL)
[[35mlola[0m][I] time limit : 1139 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 3/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1324 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 8/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1329 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 13/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1334 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 18/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1339 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 23/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1344 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 28/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1349 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 33/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1354 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 38/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1359 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 43/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1364 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 48/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1369 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 53/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1374 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 58/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1379 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 63/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1384 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 68/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1389 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 73/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1394 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 78/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1399 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 83/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1404 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 88/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1409 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 93/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1414 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 98/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1419 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 103/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1424 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 108/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1429 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 113/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1434 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 118/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1439 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 123/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1444 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 128/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1449 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 133/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1454 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 138/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1459 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 143/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1464 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 148/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1469 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 153/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1474 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 158/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1479 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 163/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1484 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 168/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1489 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 173/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1494 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 178/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1499 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 183/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1504 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 188/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1509 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 193/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1514 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 198/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1519 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 203/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1524 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 208/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1529 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 213/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1534 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 218/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1539 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 223/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1544 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 228/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1549 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 233/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1554 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 238/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1559 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 243/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1564 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 248/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1569 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 253/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1574 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 258/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1579 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 263/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1584 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 268/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1589 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 273/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1594 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 278/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1599 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 283/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1604 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 288/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1609 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 293/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1614 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 298/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1619 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 303/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1624 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 308/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1629 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 313/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1634 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 318/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1639 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 323/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1644 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 328/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1649 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 333/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1654 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 338/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1659 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 343/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1664 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 348/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1669 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 353/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1674 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 358/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1679 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 363/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1684 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 368/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1689 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 373/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1694 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 378/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1699 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 383/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1704 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 388/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1709 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-12:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-13:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-00:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-05:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-06:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-09:
[[35mlola[0m][.] DLCflexbar-PT-4b-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 1 LTL EXCL 393/1139
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1714 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-01:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-02:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-03:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-04:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-07:
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4b-LTLFireability-08:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-10:
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4b-LTLFireability-11:

========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16 ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... ============= lity ============= txt xml txt xml esDefinition.xml esVerdict.xml txt xml txt xml dinality.txt dinality.xml eability.txt eability.xml (invocation template) text file) FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT at most ([1m[36m--timelimit[0m) specification: using default[0m [4m[34mmodel.pnml[0m t[0m) net [4m[34mmodel.pnml[0m mula[0m) from [4m[34mLTLFireability.xml[0m CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 AG 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 AG 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 places removed CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 AG 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 AG 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 AG 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 for 33 DLCflexbar-PT-4b-LTLFireability-11 for DLCflexbar-PT-4b-LTLFireability-11 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 AG 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 AG 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 AG 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 AG 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 AG 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 [status_logger] string pointer is null CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 AG 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 AG 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 AG 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 16 for 9 DLCflexbar-PT-4b-LTLFireability-03 for DLCflexbar-PT-4b-LTLFireability-03 287 287 0 1 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 0 0 0 0 AG 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 0 0 0 0 AG 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 16 for 50 DLCflexbar-PT-4b-LTLFireability-14 for 50 DLCflexbar-PT-4b-LTLFireability-14 for 50 DLCflexbar-PT-4b-LTLFireability-14 for 40 DLCflexbar-PT-4b-LTLFireability-12 for DLCflexbar-PT-4b-LTLFireability-14 0 1 for DLCflexbar-PT-4b-LTLFireability-14 (obsolete) for DLCflexbar-PT-4b-LTLFireability-14 (obsolete) for 40 DLCflexbar-PT-4b-LTLFireability-12 for 40 DLCflexbar-PT-4b-LTLFireability-12 for DLCflexbar-PT-4b-LTLFireability-14 1 0 0 for DLCflexbar-PT-4b-LTLFireability-12 1 0 0 for DLCflexbar-PT-4b-LTLFireability-12 (obsolete) for DLCflexbar-PT-4b-LTLFireability-12 (obsolete) for 30 DLCflexbar-PT-4b-LTLFireability-10 for DLCflexbar-PT-4b-LTLFireability-10 562 563 0 1 for 21 DLCflexbar-PT-4b-LTLFireability-07 for DLCflexbar-PT-4b-LTLFireability-07 559 559 0 1 for 27 DLCflexbar-PT-4b-LTLFireability-09 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-4b-LTLFireability-09 1621 m, 324 m/sec, 3818 t fired, . Pages in use: 2 16 for DLCflexbar-PT-4b-LTLFireability-12 for DLCflexbar-PT-4b-LTLFireability-14 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-4b-LTLFireability-09 8427 m, 1361 m/sec, 25650 t fired, . Pages in use: 2 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-4b-LTLFireability-09 14866 m, 1287 m/sec, 45421 t fired, . Pages in use: 2 16 [status_logger] string pointer is null CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-4b-LTLFireability-09 22146 m, 1456 m/sec, 68098 t fired, . Pages in use: 2 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-4b-LTLFireability-09 31462 m, 1863 m/sec, 98042 t fired, . Pages in use: 2 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-4b-LTLFireability-09 40640 m, 1835 m/sec, 127462 t fired, . Pages in use: 2 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-4b-LTLFireability-09 49363 m, 1744 m/sec, 154859 t fired, . Pages in use: 2 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-4b-LTLFireability-09 57672 m, 1661 m/sec, 183652 t fired, . Pages in use: 2 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 DLCflexbar-PT-4b-LTLFireability-09 69266 m, 2318 m/sec, 221622 t fired, . Pages in use: 2 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 2/2000 DLCflexbar-PT-4b-LTLFireability-09 97802 m, 5707 m/sec, 293357 t fired, . Pages in use: 2 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 2/2000 DLCflexbar-PT-4b-LTLFireability-09 162197 m, 12879 m/sec, 437388 t fired, . Pages in use: 2 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 3/2000 DLCflexbar-PT-4b-LTLFireability-09 230919 m, 13744 m/sec, 594358 t fired, . Pages in use: 3 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 3/2000 DLCflexbar-PT-4b-LTLFireability-09 297195 m, 13255 m/sec, 742734 t fired, . Pages in use: 3 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 4/2000 DLCflexbar-PT-4b-LTLFireability-09 364982 m, 13557 m/sec, 894034 t fired, . Pages in use: 4 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 4/2000 DLCflexbar-PT-4b-LTLFireability-09 432980 m, 13599 m/sec, 1046611 t fired, . Pages in use: 4 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 5/2000 DLCflexbar-PT-4b-LTLFireability-09 502635 m, 13931 m/sec, 1201966 t fired, . Pages in use: 5 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 5/2000 DLCflexbar-PT-4b-LTLFireability-09 571011 m, 13675 m/sec, 1355711 t fired, . Pages in use: 5 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 6/2000 DLCflexbar-PT-4b-LTLFireability-09 636804 m, 13158 m/sec, 1502485 t fired, . Pages in use: 6 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 6/2000 DLCflexbar-PT-4b-LTLFireability-09 702137 m, 13066 m/sec, 1648983 t fired, . Pages in use: 6 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 7/2000 DLCflexbar-PT-4b-LTLFireability-09 769435 m, 13459 m/sec, 1801322 t fired, . Pages in use: 7 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 7/2000 DLCflexbar-PT-4b-LTLFireability-09 838395 m, 13792 m/sec, 1960912 t fired, . Pages in use: 7 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 8/2000 DLCflexbar-PT-4b-LTLFireability-09 907526 m, 13826 m/sec, 2116821 t fired, . Pages in use: 8 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 8/2000 DLCflexbar-PT-4b-LTLFireability-09 975315 m, 13557 m/sec, 2270207 t fired, . Pages in use: 8 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 9/2000 DLCflexbar-PT-4b-LTLFireability-09 1039758 m, 12888 m/sec, 2414563 t fired, . Pages in use: 9 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 9/2000 DLCflexbar-PT-4b-LTLFireability-09 1104234 m, 12895 m/sec, 2556405 t fired, . Pages in use: 9 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 10/2000 DLCflexbar-PT-4b-LTLFireability-09 1171328 m, 13418 m/sec, 2708565 t fired, . Pages in use: 10 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 10/2000 DLCflexbar-PT-4b-LTLFireability-09 1239549 m, 13644 m/sec, 2861366 t fired, . Pages in use: 10 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 11/2000 DLCflexbar-PT-4b-LTLFireability-09 1307651 m, 13620 m/sec, 3014336 t fired, . Pages in use: 11 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 11/2000 DLCflexbar-PT-4b-LTLFireability-09 1375219 m, 13513 m/sec, 3168021 t fired, . Pages in use: 11 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 12/2000 DLCflexbar-PT-4b-LTLFireability-09 1441092 m, 13174 m/sec, 3315631 t fired, . Pages in use: 12 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 12/2000 DLCflexbar-PT-4b-LTLFireability-09 1506811 m, 13143 m/sec, 3461341 t fired, . Pages in use: 12 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 13/2000 DLCflexbar-PT-4b-LTLFireability-09 1573475 m, 13332 m/sec, 3610924 t fired, . Pages in use: 13 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 13/2000 DLCflexbar-PT-4b-LTLFireability-09 1641354 m, 13575 m/sec, 3761712 t fired, . Pages in use: 13 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 14/2000 DLCflexbar-PT-4b-LTLFireability-09 1709853 m, 13699 m/sec, 3915848 t fired, . Pages in use: 14 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 14/2000 DLCflexbar-PT-4b-LTLFireability-09 1776460 m, 13321 m/sec, 4066544 t fired, . Pages in use: 14 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 14/2000 DLCflexbar-PT-4b-LTLFireability-09 1841685 m, 13045 m/sec, 4211274 t fired, . Pages in use: 14 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 15/2000 DLCflexbar-PT-4b-LTLFireability-09 1906739 m, 13010 m/sec, 4357771 t fired, . Pages in use: 15 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 15/2000 DLCflexbar-PT-4b-LTLFireability-09 1973178 m, 13287 m/sec, 4508057 t fired, . Pages in use: 15 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 16/2000 DLCflexbar-PT-4b-LTLFireability-09 2040969 m, 13558 m/sec, 4664824 t fired, . Pages in use: 16 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 16/2000 DLCflexbar-PT-4b-LTLFireability-09 2109001 m, 13606 m/sec, 4818382 t fired, . Pages in use: 16 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 17/2000 DLCflexbar-PT-4b-LTLFireability-09 2176635 m, 13526 m/sec, 4971169 t fired, . Pages in use: 17 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 17/2000 DLCflexbar-PT-4b-LTLFireability-09 2243285 m, 13330 m/sec, 5123871 t fired, . Pages in use: 17 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 18/2000 DLCflexbar-PT-4b-LTLFireability-09 2311814 m, 13705 m/sec, 5280795 t fired, . Pages in use: 18 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 18/2000 DLCflexbar-PT-4b-LTLFireability-09 2378588 m, 13354 m/sec, 5433312 t fired, . Pages in use: 18 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 19/2000 DLCflexbar-PT-4b-LTLFireability-09 2444832 m, 13248 m/sec, 5585119 t fired, . Pages in use: 19 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 19/2000 DLCflexbar-PT-4b-LTLFireability-09 2511637 m, 13361 m/sec, 5737528 t fired, . Pages in use: 19 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 20/2000 DLCflexbar-PT-4b-LTLFireability-09 2578258 m, 13324 m/sec, 5889309 t fired, . Pages in use: 20 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 20/2000 DLCflexbar-PT-4b-LTLFireability-09 2643348 m, 13018 m/sec, 6040402 t fired, . Pages in use: 20 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 21/2000 DLCflexbar-PT-4b-LTLFireability-09 2708735 m, 13077 m/sec, 6190441 t fired, . Pages in use: 21 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 21/2000 DLCflexbar-PT-4b-LTLFireability-09 2775281 m, 13309 m/sec, 6341802 t fired, . Pages in use: 21 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 22/2000 DLCflexbar-PT-4b-LTLFireability-09 2841894 m, 13322 m/sec, 6494263 t fired, . Pages in use: 22 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 22/2000 DLCflexbar-PT-4b-LTLFireability-09 2908602 m, 13341 m/sec, 6646109 t fired, . Pages in use: 22 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 23/2000 DLCflexbar-PT-4b-LTLFireability-09 2974434 m, 13166 m/sec, 6799237 t fired, . Pages in use: 23 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 23/2000 DLCflexbar-PT-4b-LTLFireability-09 3039160 m, 12945 m/sec, 6949651 t fired, . Pages in use: 23 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 23/2000 DLCflexbar-PT-4b-LTLFireability-09 3103244 m, 12816 m/sec, 7099349 t fired, . Pages in use: 23 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 24/2000 DLCflexbar-PT-4b-LTLFireability-09 3166746 m, 12700 m/sec, 7247303 t fired, . Pages in use: 24 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 24/2000 DLCflexbar-PT-4b-LTLFireability-09 3233557 m, 13362 m/sec, 7400712 t fired, . Pages in use: 24 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 25/2000 DLCflexbar-PT-4b-LTLFireability-09 3298063 m, 12901 m/sec, 7549789 t fired, . Pages in use: 25 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 25/2000 DLCflexbar-PT-4b-LTLFireability-09 3363866 m, 13160 m/sec, 7700225 t fired, . Pages in use: 25 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 26/2000 DLCflexbar-PT-4b-LTLFireability-09 3431048 m, 13436 m/sec, 7853874 t fired, . Pages in use: 26 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 26/2000 DLCflexbar-PT-4b-LTLFireability-09 3497172 m, 13224 m/sec, 8007693 t fired, . Pages in use: 26 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 27/2000 DLCflexbar-PT-4b-LTLFireability-09 3562881 m, 13141 m/sec, 8160241 t fired, . Pages in use: 27 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 27/2000 DLCflexbar-PT-4b-LTLFireability-09 3628338 m, 13091 m/sec, 8312886 t fired, . Pages in use: 27 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 28/2000 DLCflexbar-PT-4b-LTLFireability-09 3694342 m, 13200 m/sec, 8465212 t fired, . Pages in use: 28 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 28/2000 DLCflexbar-PT-4b-LTLFireability-09 3759294 m, 12990 m/sec, 8613686 t fired, . Pages in use: 28 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 29/2000 DLCflexbar-PT-4b-LTLFireability-09 3823814 m, 12904 m/sec, 8764407 t fired, . Pages in use: 29 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 29/2000 DLCflexbar-PT-4b-LTLFireability-09 3888899 m, 13017 m/sec, 8915289 t fired, . Pages in use: 29 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 29/2000 DLCflexbar-PT-4b-LTLFireability-09 3954474 m, 13115 m/sec, 9066716 t fired, . Pages in use: 29 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 30/2000 DLCflexbar-PT-4b-LTLFireability-09 4020843 m, 13273 m/sec, 9220568 t fired, . Pages in use: 30 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 30/2000 DLCflexbar-PT-4b-LTLFireability-09 4086349 m, 13101 m/sec, 9372253 t fired, . Pages in use: 30 16 for DLCflexbar-PT-4b-LTLFireability-09 (local timeout) CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 1 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 31 16 for 53 DLCflexbar-PT-4b-LTLFireability-15 for 27 DLCflexbar-PT-4b-LTLFireability-09 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/5 DLCflexbar-PT-4b-LTLFireability-09 19078 m, -813454 m/sec, 58802 t fired, . 3/2000 DLCflexbar-PT-4b-LTLFireability-15 81098 m, 16219 m/sec, 95590 t fired, . Pages in use: 35 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/5 DLCflexbar-PT-4b-LTLFireability-09 39629 m, 4110 m/sec, 124239 t fired, . 5/2000 DLCflexbar-PT-4b-LTLFireability-15 160916 m, 15963 m/sec, 192687 t fired, . Pages in use: 37 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/5 DLCflexbar-PT-4b-LTLFireability-09 60357 m, 4145 m/sec, 192954 t fired, . 7/2000 DLCflexbar-PT-4b-LTLFireability-15 240125 m, 15841 m/sec, 288906 t fired, . Pages in use: 39 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/5 DLCflexbar-PT-4b-LTLFireability-09 80899 m, 4108 m/sec, 257182 t fired, . 9/2000 DLCflexbar-PT-4b-LTLFireability-15 317996 m, 15574 m/sec, 385242 t fired, . Pages in use: 41 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 2/5 DLCflexbar-PT-4b-LTLFireability-09 143060 m, 12432 m/sec, 393744 t fired, . 11/2000 DLCflexbar-PT-4b-LTLFireability-15 396919 m, 15784 m/sec, 480882 t fired, . Pages in use: 44 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 2/5 DLCflexbar-PT-4b-LTLFireability-09 207979 m, 12983 m/sec, 543927 t fired, . 13/2000 DLCflexbar-PT-4b-LTLFireability-15 475786 m, 15773 m/sec, 576543 t fired, . Pages in use: 46 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 3/5 DLCflexbar-PT-4b-LTLFireability-09 269116 m, 12227 m/sec, 679651 t fired, . 15/2000 DLCflexbar-PT-4b-LTLFireability-15 554454 m, 15733 m/sec, 671954 t fired, . Pages in use: 49 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 3/5 DLCflexbar-PT-4b-LTLFireability-09 331377 m, 12452 m/sec, 818814 t fired, . 17/2000 DLCflexbar-PT-4b-LTLFireability-15 632119 m, 15533 m/sec, 768057 t fired, . Pages in use: 51 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 4/5 DLCflexbar-PT-4b-LTLFireability-09 394421 m, 12608 m/sec, 959776 t fired, . 19/2000 DLCflexbar-PT-4b-LTLFireability-15 710893 m, 15754 m/sec, 863551 t fired, . Pages in use: 54 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 4/5 DLCflexbar-PT-4b-LTLFireability-09 461082 m, 13332 m/sec, 1108395 t fired, . 21/2000 DLCflexbar-PT-4b-LTLFireability-15 792624 m, 16346 m/sec, 962671 t fired, . Pages in use: 56 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 5/5 DLCflexbar-PT-4b-LTLFireability-09 528872 m, 13558 m/sec, 1260908 t fired, . 23/2000 DLCflexbar-PT-4b-LTLFireability-15 874637 m, 16402 m/sec, 1063485 t fired, . Pages in use: 59 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 5/5 DLCflexbar-PT-4b-LTLFireability-09 594399 m, 13105 m/sec, 1407734 t fired, . 25/2000 DLCflexbar-PT-4b-LTLFireability-15 953086 m, 15689 m/sec, 1165567 t fired, . Pages in use: 61 16 for DLCflexbar-PT-4b-LTLFireability-09 (memory limit exceeded) CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 26/2000 DLCflexbar-PT-4b-LTLFireability-15 1028441 m, 15071 m/sec, 1269181 t fired, . Pages in use: 61 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 27/2000 DLCflexbar-PT-4b-LTLFireability-15 1106409 m, 15593 m/sec, 1369834 t fired, . Pages in use: 61 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 29/2000 DLCflexbar-PT-4b-LTLFireability-15 1187597 m, 16237 m/sec, 1470148 t fired, . Pages in use: 61 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 31/2000 DLCflexbar-PT-4b-LTLFireability-15 1266594 m, 15799 m/sec, 1572857 t fired, . Pages in use: 62 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 33/2000 DLCflexbar-PT-4b-LTLFireability-15 1348010 m, 16283 m/sec, 1673529 t fired, . Pages in use: 64 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 34/2000 DLCflexbar-PT-4b-LTLFireability-15 1430519 m, 16501 m/sec, 1773558 t fired, . Pages in use: 65 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 36/2000 DLCflexbar-PT-4b-LTLFireability-15 1512691 m, 16434 m/sec, 1873716 t fired, . Pages in use: 67 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 38/2000 DLCflexbar-PT-4b-LTLFireability-15 1592983 m, 16058 m/sec, 1975551 t fired, . Pages in use: 69 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 39/2000 DLCflexbar-PT-4b-LTLFireability-15 1674950 m, 16393 m/sec, 2075991 t fired, . Pages in use: 70 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 41/2000 DLCflexbar-PT-4b-LTLFireability-15 1757251 m, 16460 m/sec, 2175773 t fired, . Pages in use: 72 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 42/2000 DLCflexbar-PT-4b-LTLFireability-15 1839185 m, 16386 m/sec, 2275324 t fired, . Pages in use: 73 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 44/2000 DLCflexbar-PT-4b-LTLFireability-15 1916261 m, 15415 m/sec, 2373135 t fired, . Pages in use: 75 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 45/2000 DLCflexbar-PT-4b-LTLFireability-15 1991709 m, 15089 m/sec, 2470949 t fired, . Pages in use: 76 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 47/2000 DLCflexbar-PT-4b-LTLFireability-15 2073341 m, 16326 m/sec, 2570254 t fired, . Pages in use: 78 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 48/2000 DLCflexbar-PT-4b-LTLFireability-15 2154948 m, 16321 m/sec, 2669646 t fired, . Pages in use: 79 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 50/2000 DLCflexbar-PT-4b-LTLFireability-15 2236536 m, 16317 m/sec, 2768666 t fired, . Pages in use: 81 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 51/2000 DLCflexbar-PT-4b-LTLFireability-15 2316251 m, 15943 m/sec, 2865573 t fired, . Pages in use: 82 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 53/2000 DLCflexbar-PT-4b-LTLFireability-15 2393785 m, 15506 m/sec, 2959851 t fired, . Pages in use: 84 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 54/2000 DLCflexbar-PT-4b-LTLFireability-15 2474235 m, 16090 m/sec, 3058130 t fired, . Pages in use: 85 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 55/2000 DLCflexbar-PT-4b-LTLFireability-15 2552619 m, 15676 m/sec, 3153472 t fired, . Pages in use: 86 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 57/2000 DLCflexbar-PT-4b-LTLFireability-15 2629840 m, 15444 m/sec, 3247285 t fired, . Pages in use: 88 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 58/2000 DLCflexbar-PT-4b-LTLFireability-15 2707237 m, 15479 m/sec, 3341906 t fired, . Pages in use: 89 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 60/2000 DLCflexbar-PT-4b-LTLFireability-15 2786976 m, 15947 m/sec, 3438438 t fired, . Pages in use: 91 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 61/2000 DLCflexbar-PT-4b-LTLFireability-15 2864315 m, 15467 m/sec, 3532412 t fired, . Pages in use: 92 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 62/2000 DLCflexbar-PT-4b-LTLFireability-15 2941729 m, 15482 m/sec, 3626694 t fired, . Pages in use: 93 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 64/2000 DLCflexbar-PT-4b-LTLFireability-15 3018452 m, 15344 m/sec, 3722169 t fired, . Pages in use: 95 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 65/2000 DLCflexbar-PT-4b-LTLFireability-15 3095259 m, 15361 m/sec, 3817216 t fired, . Pages in use: 96 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 67/2000 DLCflexbar-PT-4b-LTLFireability-15 3170317 m, 15011 m/sec, 3915143 t fired, . Pages in use: 98 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 68/2000 DLCflexbar-PT-4b-LTLFireability-15 3246501 m, 15236 m/sec, 4013936 t fired, . Pages in use: 99 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 69/2000 DLCflexbar-PT-4b-LTLFireability-15 3321639 m, 15027 m/sec, 4111982 t fired, . Pages in use: 100 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 71/2000 DLCflexbar-PT-4b-LTLFireability-15 3400887 m, 15849 m/sec, 4211454 t fired, . Pages in use: 102 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 72/2000 DLCflexbar-PT-4b-LTLFireability-15 3481304 m, 16083 m/sec, 4309888 t fired, . Pages in use: 103 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 73/2000 DLCflexbar-PT-4b-LTLFireability-15 3560466 m, 15832 m/sec, 4406217 t fired, . Pages in use: 104 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 74/2000 DLCflexbar-PT-4b-LTLFireability-15 3641160 m, 16138 m/sec, 4503946 t fired, . Pages in use: 105 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 75/2000 DLCflexbar-PT-4b-LTLFireability-15 3720713 m, 15910 m/sec, 4601015 t fired, . Pages in use: 106 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 77/2000 DLCflexbar-PT-4b-LTLFireability-15 3797808 m, 15419 m/sec, 4695706 t fired, . Pages in use: 108 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 78/2000 DLCflexbar-PT-4b-LTLFireability-15 3875889 m, 15616 m/sec, 4790610 t fired, . Pages in use: 109 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 80/2000 DLCflexbar-PT-4b-LTLFireability-15 3952278 m, 15277 m/sec, 4884980 t fired, . Pages in use: 111 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 81/2000 DLCflexbar-PT-4b-LTLFireability-15 4029190 m, 15382 m/sec, 4979592 t fired, . Pages in use: 112 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 83/2000 DLCflexbar-PT-4b-LTLFireability-15 4108643 m, 15890 m/sec, 5076044 t fired, . Pages in use: 114 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 84/2000 DLCflexbar-PT-4b-LTLFireability-15 4186616 m, 15594 m/sec, 5170925 t fired, . Pages in use: 115 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 85/2000 DLCflexbar-PT-4b-LTLFireability-15 4263277 m, 15332 m/sec, 5266941 t fired, . Pages in use: 116 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 87/2000 DLCflexbar-PT-4b-LTLFireability-15 4341983 m, 15741 m/sec, 5362320 t fired, . Pages in use: 118 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 88/2000 DLCflexbar-PT-4b-LTLFireability-15 4417228 m, 15049 m/sec, 5457968 t fired, . Pages in use: 119 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 89/2000 DLCflexbar-PT-4b-LTLFireability-15 4494586 m, 15471 m/sec, 5552851 t fired, . Pages in use: 120 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 91/2000 DLCflexbar-PT-4b-LTLFireability-15 4573500 m, 15782 m/sec, 5648971 t fired, . Pages in use: 122 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 92/2000 DLCflexbar-PT-4b-LTLFireability-15 4650708 m, 15441 m/sec, 5743691 t fired, . Pages in use: 123 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 93/2000 DLCflexbar-PT-4b-LTLFireability-15 4727453 m, 15349 m/sec, 5839632 t fired, . Pages in use: 124 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 95/2000 DLCflexbar-PT-4b-LTLFireability-15 4805520 m, 15613 m/sec, 5934620 t fired, . Pages in use: 126 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 96/2000 DLCflexbar-PT-4b-LTLFireability-15 4883162 m, 15528 m/sec, 6029509 t fired, . Pages in use: 127 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 97/2000 DLCflexbar-PT-4b-LTLFireability-15 4959252 m, 15218 m/sec, 6123890 t fired, . Pages in use: 128 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 98/2000 DLCflexbar-PT-4b-LTLFireability-15 5036874 m, 15524 m/sec, 6218221 t fired, . Pages in use: 129 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 99/2000 DLCflexbar-PT-4b-LTLFireability-15 5112415 m, 15108 m/sec, 6313417 t fired, . Pages in use: 130 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 101/2000 DLCflexbar-PT-4b-LTLFireability-15 5192357 m, 15988 m/sec, 6410783 t fired, . Pages in use: 132 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 102/2000 DLCflexbar-PT-4b-LTLFireability-15 5269037 m, 15336 m/sec, 6509105 t fired, . Pages in use: 133 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 104/2000 DLCflexbar-PT-4b-LTLFireability-15 5349693 m, 16131 m/sec, 6607353 t fired, . Pages in use: 135 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 105/2000 DLCflexbar-PT-4b-LTLFireability-15 5423032 m, 14667 m/sec, 6707589 t fired, . Pages in use: 136 16 for DLCflexbar-PT-4b-LTLFireability-15 (local timeout) CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 1 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 137 16 for 47 DLCflexbar-PT-4b-LTLFireability-13 for 53 DLCflexbar-PT-4b-LTLFireability-15 for DLCflexbar-PT-4b-LTLFireability-13 51 51 0 1 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 3/5 DLCflexbar-PT-4b-LTLFireability-15 81001 m, -1068406 m/sec, 95480 t fired, . Pages in use: 142 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 5/5 DLCflexbar-PT-4b-LTLFireability-15 161380 m, 16075 m/sec, 193250 t fired, . Pages in use: 145 16 for DLCflexbar-PT-4b-LTLFireability-15 (memory limit exceeded) CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 146 16 for 24 DLCflexbar-PT-4b-LTLFireability-08 for DLCflexbar-PT-4b-LTLFireability-08 2 1 0 1 for 15 DLCflexbar-PT-4b-LTLFireability-05 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 3/2000 DLCflexbar-PT-4b-LTLFireability-05 80586 m, 16117 m/sec, 95046 t fired, . Pages in use: 146 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 5/2000 DLCflexbar-PT-4b-LTLFireability-05 159790 m, 15840 m/sec, 191313 t fired, . Pages in use: 149 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 7/2000 DLCflexbar-PT-4b-LTLFireability-05 238521 m, 15746 m/sec, 286937 t fired, . Pages in use: 153 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 9/2000 DLCflexbar-PT-4b-LTLFireability-05 316384 m, 15572 m/sec, 383272 t fired, . Pages in use: 156 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 11/2000 DLCflexbar-PT-4b-LTLFireability-05 395321 m, 15787 m/sec, 478971 t fired, . Pages in use: 159 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 13/2000 DLCflexbar-PT-4b-LTLFireability-05 473804 m, 15696 m/sec, 574159 t fired, . Pages in use: 163 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 15/2000 DLCflexbar-PT-4b-LTLFireability-05 552312 m, 15701 m/sec, 669326 t fired, . Pages in use: 166 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 17/2000 DLCflexbar-PT-4b-LTLFireability-05 630020 m, 15541 m/sec, 765488 t fired, . Pages in use: 169 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 19/2000 DLCflexbar-PT-4b-LTLFireability-05 708315 m, 15659 m/sec, 860428 t fired, . Pages in use: 173 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 21/2000 DLCflexbar-PT-4b-LTLFireability-05 787158 m, 15768 m/sec, 956019 t fired, . Pages in use: 176 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 23/2000 DLCflexbar-PT-4b-LTLFireability-05 865788 m, 15726 m/sec, 1051431 t fired, . Pages in use: 179 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 25/2000 DLCflexbar-PT-4b-LTLFireability-05 941363 m, 15115 m/sec, 1148362 t fired, . Pages in use: 183 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 26/2000 DLCflexbar-PT-4b-LTLFireability-05 1012701 m, 14267 m/sec, 1247037 t fired, . Pages in use: 185 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 27/2000 DLCflexbar-PT-4b-LTLFireability-05 1085946 m, 14649 m/sec, 1344429 t fired, . Pages in use: 188 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 29/2000 DLCflexbar-PT-4b-LTLFireability-05 1163114 m, 15433 m/sec, 1440385 t fired, . Pages in use: 191 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 31/2000 DLCflexbar-PT-4b-LTLFireability-05 1241203 m, 15617 m/sec, 1535909 t fired, . Pages in use: 194 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 32/2000 DLCflexbar-PT-4b-LTLFireability-05 1315259 m, 14811 m/sec, 1633133 t fired, . Pages in use: 197 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 34/2000 DLCflexbar-PT-4b-LTLFireability-05 1393324 m, 15613 m/sec, 1728575 t fired, . Pages in use: 200 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 35/2000 DLCflexbar-PT-4b-LTLFireability-05 1471664 m, 15668 m/sec, 1823357 t fired, . Pages in use: 203 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 37/2000 DLCflexbar-PT-4b-LTLFireability-05 1549514 m, 15570 m/sec, 1918678 t fired, . Pages in use: 206 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 38/2000 DLCflexbar-PT-4b-LTLFireability-05 1624934 m, 15084 m/sec, 2015065 t fired, . Pages in use: 208 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 40/2000 DLCflexbar-PT-4b-LTLFireability-05 1702781 m, 15569 m/sec, 2109819 t fired, . Pages in use: 211 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 41/2000 DLCflexbar-PT-4b-LTLFireability-05 1780595 m, 15562 m/sec, 2204126 t fired, . Pages in use: 214 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 43/2000 DLCflexbar-PT-4b-LTLFireability-05 1856675 m, 15216 m/sec, 2299479 t fired, . Pages in use: 217 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 44/2000 DLCflexbar-PT-4b-LTLFireability-05 1933479 m, 15360 m/sec, 2394020 t fired, . Pages in use: 219 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 46/2000 DLCflexbar-PT-4b-LTLFireability-05 2007849 m, 14874 m/sec, 2490519 t fired, . Pages in use: 222 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 47/2000 DLCflexbar-PT-4b-LTLFireability-05 2085132 m, 15456 m/sec, 2584615 t fired, . Pages in use: 225 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 48/2000 DLCflexbar-PT-4b-LTLFireability-05 2162154 m, 15404 m/sec, 2678506 t fired, . Pages in use: 227 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 50/2000 DLCflexbar-PT-4b-LTLFireability-05 2239317 m, 15432 m/sec, 2772068 t fired, . Pages in use: 230 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 51/2000 DLCflexbar-PT-4b-LTLFireability-05 2315820 m, 15300 m/sec, 2865051 t fired, . Pages in use: 232 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 53/2000 DLCflexbar-PT-4b-LTLFireability-05 2392696 m, 15375 m/sec, 2958497 t fired, . Pages in use: 235 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 54/2000 DLCflexbar-PT-4b-LTLFireability-05 2469518 m, 15364 m/sec, 3052388 t fired, . Pages in use: 238 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 55/2000 DLCflexbar-PT-4b-LTLFireability-05 2545924 m, 15281 m/sec, 3145362 t fired, . Pages in use: 240 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 56/2000 DLCflexbar-PT-4b-LTLFireability-05 2622737 m, 15362 m/sec, 3238689 t fired, . Pages in use: 242 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 58/2000 DLCflexbar-PT-4b-LTLFireability-05 2699856 m, 15423 m/sec, 3332967 t fired, . Pages in use: 245 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 60/2000 DLCflexbar-PT-4b-LTLFireability-05 2777682 m, 15565 m/sec, 3427357 t fired, . Pages in use: 248 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 61/2000 DLCflexbar-PT-4b-LTLFireability-05 2854698 m, 15403 m/sec, 3520720 t fired, . Pages in use: 250 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 62/2000 DLCflexbar-PT-4b-LTLFireability-05 2931331 m, 15326 m/sec, 3614058 t fired, . Pages in use: 252 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 64/2000 DLCflexbar-PT-4b-LTLFireability-05 3008081 m, 15350 m/sec, 3709250 t fired, . Pages in use: 256 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 65/2000 DLCflexbar-PT-4b-LTLFireability-05 3084684 m, 15320 m/sec, 3803731 t fired, . Pages in use: 258 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 66/2000 DLCflexbar-PT-4b-LTLFireability-05 3157552 m, 14573 m/sec, 3899595 t fired, . Pages in use: 260 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 68/2000 DLCflexbar-PT-4b-LTLFireability-05 3231190 m, 14727 m/sec, 3994638 t fired, . Pages in use: 264 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 69/2000 DLCflexbar-PT-4b-LTLFireability-05 3304060 m, 14574 m/sec, 4089975 t fired, . Pages in use: 266 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 70/2000 DLCflexbar-PT-4b-LTLFireability-05 3379848 m, 15157 m/sec, 4183807 t fired, . Pages in use: 269 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 72/2000 DLCflexbar-PT-4b-LTLFireability-05 3454867 m, 15003 m/sec, 4277783 t fired, . Pages in use: 272 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 73/2000 DLCflexbar-PT-4b-LTLFireability-05 3531090 m, 15244 m/sec, 4370477 t fired, . Pages in use: 274 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 74/2000 DLCflexbar-PT-4b-LTLFireability-05 3607393 m, 15260 m/sec, 4463176 t fired, . Pages in use: 276 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 75/2000 DLCflexbar-PT-4b-LTLFireability-05 3684070 m, 15335 m/sec, 4556654 t fired, . Pages in use: 279 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 76/2000 DLCflexbar-PT-4b-LTLFireability-05 3761093 m, 15404 m/sec, 4650540 t fired, . Pages in use: 281 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 78/2000 DLCflexbar-PT-4b-LTLFireability-05 3837712 m, 15323 m/sec, 4744395 t fired, . Pages in use: 284 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 79/2000 DLCflexbar-PT-4b-LTLFireability-05 3914595 m, 15376 m/sec, 4837572 t fired, . Pages in use: 286 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 80/2000 DLCflexbar-PT-4b-LTLFireability-05 3990031 m, 15087 m/sec, 4932165 t fired, . Pages in use: 288 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 82/2000 DLCflexbar-PT-4b-LTLFireability-05 4067761 m, 15546 m/sec, 5026298 t fired, . Pages in use: 291 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 83/2000 DLCflexbar-PT-4b-LTLFireability-05 4145030 m, 15453 m/sec, 5120257 t fired, . Pages in use: 293 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 85/2000 DLCflexbar-PT-4b-LTLFireability-05 4221681 m, 15330 m/sec, 5215087 t fired, . Pages in use: 296 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 86/2000 DLCflexbar-PT-4b-LTLFireability-05 4298241 m, 15312 m/sec, 5309481 t fired, . Pages in use: 298 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 87/2000 DLCflexbar-PT-4b-LTLFireability-05 4375112 m, 15374 m/sec, 5404007 t fired, . Pages in use: 301 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 88/2000 DLCflexbar-PT-4b-LTLFireability-05 4450828 m, 15143 m/sec, 5499321 t fired, . Pages in use: 303 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 90/2000 DLCflexbar-PT-4b-LTLFireability-05 4527612 m, 15356 m/sec, 5593253 t fired, . Pages in use: 306 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 91/2000 DLCflexbar-PT-4b-LTLFireability-05 4603899 m, 15257 m/sec, 5687192 t fired, . Pages in use: 308 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 92/2000 DLCflexbar-PT-4b-LTLFireability-05 4680358 m, 15291 m/sec, 5781349 t fired, . Pages in use: 310 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 94/2000 DLCflexbar-PT-4b-LTLFireability-05 4757598 m, 15448 m/sec, 5876321 t fired, . Pages in use: 313 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 95/2000 DLCflexbar-PT-4b-LTLFireability-05 4835112 m, 15502 m/sec, 5970646 t fired, . Pages in use: 315 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 97/2000 DLCflexbar-PT-4b-LTLFireability-05 4911081 m, 15193 m/sec, 6064737 t fired, . Pages in use: 318 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 98/2000 DLCflexbar-PT-4b-LTLFireability-05 4986709 m, 15125 m/sec, 6157311 t fired, . Pages in use: 320 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 99/2000 DLCflexbar-PT-4b-LTLFireability-05 5062373 m, 15132 m/sec, 6249243 t fired, . Pages in use: 322 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 100/2000 DLCflexbar-PT-4b-LTLFireability-05 5135003 m, 14526 m/sec, 6340895 t fired, . Pages in use: 324 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 101/2000 DLCflexbar-PT-4b-LTLFireability-05 5210512 m, 15101 m/sec, 6432810 t fired, . Pages in use: 326 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 103/2000 DLCflexbar-PT-4b-LTLFireability-05 5284096 m, 14716 m/sec, 6527364 t fired, . Pages in use: 329 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 104/2000 DLCflexbar-PT-4b-LTLFireability-05 5360158 m, 15212 m/sec, 6620123 t fired, . Pages in use: 331 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 105/2000 DLCflexbar-PT-4b-LTLFireability-05 5429999 m, 13968 m/sec, 6716069 t fired, . Pages in use: 333 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 106/2000 DLCflexbar-PT-4b-LTLFireability-05 5501830 m, 14366 m/sec, 6810160 t fired, . Pages in use: 335 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 108/2000 DLCflexbar-PT-4b-LTLFireability-05 5577699 m, 15173 m/sec, 6902741 t fired, . Pages in use: 338 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 109/2000 DLCflexbar-PT-4b-LTLFireability-05 5649438 m, 14347 m/sec, 6998441 t fired, . Pages in use: 340 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 110/2000 DLCflexbar-PT-4b-LTLFireability-05 5723608 m, 14834 m/sec, 7092368 t fired, . Pages in use: 342 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 111/2000 DLCflexbar-PT-4b-LTLFireability-05 5795788 m, 14436 m/sec, 7186802 t fired, . Pages in use: 345 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 113/2000 DLCflexbar-PT-4b-LTLFireability-05 5868293 m, 14501 m/sec, 7281028 t fired, . Pages in use: 348 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 114/2000 DLCflexbar-PT-4b-LTLFireability-05 5943788 m, 15099 m/sec, 7373262 t fired, . Pages in use: 350 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 115/2000 DLCflexbar-PT-4b-LTLFireability-05 6019643 m, 15171 m/sec, 7465214 t fired, . Pages in use: 353 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 117/2000 DLCflexbar-PT-4b-LTLFireability-05 6095303 m, 15132 m/sec, 7556916 t fired, . Pages in use: 356 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 118/2000 DLCflexbar-PT-4b-LTLFireability-05 6170772 m, 15093 m/sec, 7648550 t fired, . Pages in use: 358 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 119/2000 DLCflexbar-PT-4b-LTLFireability-05 6243868 m, 14619 m/sec, 7741536 t fired, . Pages in use: 360 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 121/2000 DLCflexbar-PT-4b-LTLFireability-05 6315525 m, 14331 m/sec, 7835359 t fired, . Pages in use: 364 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 122/2000 DLCflexbar-PT-4b-LTLFireability-05 6385171 m, 13929 m/sec, 7930634 t fired, . Pages in use: 366 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 123/2000 DLCflexbar-PT-4b-LTLFireability-05 6456299 m, 14225 m/sec, 8025030 t fired, . Pages in use: 368 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 125/2000 DLCflexbar-PT-4b-LTLFireability-05 6531742 m, 15088 m/sec, 8117105 t fired, . Pages in use: 372 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 126/2000 DLCflexbar-PT-4b-LTLFireability-05 6604322 m, 14516 m/sec, 8210982 t fired, . Pages in use: 374 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 128/2000 DLCflexbar-PT-4b-LTLFireability-05 6680164 m, 15168 m/sec, 8303262 t fired, . Pages in use: 377 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 129/2000 DLCflexbar-PT-4b-LTLFireability-05 6756209 m, 15209 m/sec, 8395494 t fired, . Pages in use: 379 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 130/2000 DLCflexbar-PT-4b-LTLFireability-05 6831896 m, 15137 m/sec, 8487576 t fired, . Pages in use: 381 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 132/2000 DLCflexbar-PT-4b-LTLFireability-05 6903478 m, 14316 m/sec, 8581353 t fired, . Pages in use: 384 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 133/2000 DLCflexbar-PT-4b-LTLFireability-05 6978526 m, 15009 m/sec, 8674252 t fired, . Pages in use: 386 16 for DLCflexbar-PT-4b-LTLFireability-05 (local timeout) CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 1 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 388 16 for 12 DLCflexbar-PT-4b-LTLFireability-04 for 15 DLCflexbar-PT-4b-LTLFireability-05 for DLCflexbar-PT-4b-LTLFireability-04 3 2 0 1 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 3/5 DLCflexbar-PT-4b-LTLFireability-05 79922 m, -1379720 m/sec, 94246 t fired, . Pages in use: 392 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 5/5 DLCflexbar-PT-4b-LTLFireability-05 158410 m, 15697 m/sec, 189659 t fired, . Pages in use: 396 16 for DLCflexbar-PT-4b-LTLFireability-05 (memory limit exceeded) CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 396 16 for 6 DLCflexbar-PT-4b-LTLFireability-02 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 3/2000 DLCflexbar-PT-4b-LTLFireability-02 79266 m, 15853 m/sec, 93426 t fired, . Pages in use: 396 16 for DLCflexbar-PT-4b-LTLFireability-02 102507 121768 7 3 for 3 DLCflexbar-PT-4b-LTLFireability-01 for DLCflexbar-PT-4b-LTLFireability-01 53 55 0 1 for 0 DLCflexbar-PT-4b-LTLFireability-00 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 2/2000 DLCflexbar-PT-4b-LTLFireability-00 56327 m, 11265 m/sec, 65511 t fired, . Pages in use: 396 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 4/2000 DLCflexbar-PT-4b-LTLFireability-00 134656 m, 15665 m/sec, 160788 t fired, . Pages in use: 399 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 6/2000 DLCflexbar-PT-4b-LTLFireability-00 213008 m, 15670 m/sec, 255952 t fired, . Pages in use: 402 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 8/2000 DLCflexbar-PT-4b-LTLFireability-00 290940 m, 15586 m/sec, 350496 t fired, . Pages in use: 406 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 10/2000 DLCflexbar-PT-4b-LTLFireability-00 367568 m, 15325 m/sec, 445323 t fired, . Pages in use: 409 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 12/2000 DLCflexbar-PT-4b-LTLFireability-00 444424 m, 15371 m/sec, 538520 t fired, . Pages in use: 412 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 14/2000 DLCflexbar-PT-4b-LTLFireability-00 521793 m, 15473 m/sec, 632335 t fired, . Pages in use: 415 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 16/2000 DLCflexbar-PT-4b-LTLFireability-00 599260 m, 15493 m/sec, 726256 t fired, . Pages in use: 418 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 18/2000 DLCflexbar-PT-4b-LTLFireability-00 675807 m, 15309 m/sec, 821002 t fired, . Pages in use: 421 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 20/2000 DLCflexbar-PT-4b-LTLFireability-00 753792 m, 15597 m/sec, 915555 t fired, . Pages in use: 424 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 22/2000 DLCflexbar-PT-4b-LTLFireability-00 831840 m, 15609 m/sec, 1010208 t fired, . Pages in use: 427 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 24/2000 DLCflexbar-PT-4b-LTLFireability-00 906810 m, 14994 m/sec, 1105105 t fired, . Pages in use: 431 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 25/2000 DLCflexbar-PT-4b-LTLFireability-00 977686 m, 14175 m/sec, 1201531 t fired, . Pages in use: 433 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 27/2000 DLCflexbar-PT-4b-LTLFireability-00 1050552 m, 14573 m/sec, 1297177 t fired, . Pages in use: 436 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 28/2000 DLCflexbar-PT-4b-LTLFireability-00 1124148 m, 14719 m/sec, 1392477 t fired, . Pages in use: 438 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 30/2000 DLCflexbar-PT-4b-LTLFireability-00 1201326 m, 15435 m/sec, 1486812 t fired, . Pages in use: 442 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 31/2000 DLCflexbar-PT-4b-LTLFireability-00 1275229 m, 14780 m/sec, 1583383 t fired, . Pages in use: 444 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 33/2000 DLCflexbar-PT-4b-LTLFireability-00 1351777 m, 15309 m/sec, 1678085 t fired, . Pages in use: 447 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 34/2000 DLCflexbar-PT-4b-LTLFireability-00 1429487 m, 15542 m/sec, 1772305 t fired, . Pages in use: 450 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 36/2000 DLCflexbar-PT-4b-LTLFireability-00 1506613 m, 15425 m/sec, 1866415 t fired, . Pages in use: 453 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 38/2000 DLCflexbar-PT-4b-LTLFireability-00 1581842 m, 15045 m/sec, 1962021 t fired, . Pages in use: 456 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 39/2000 DLCflexbar-PT-4b-LTLFireability-00 1658836 m, 15398 m/sec, 2056411 t fired, . Pages in use: 459 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 41/2000 DLCflexbar-PT-4b-LTLFireability-00 1736286 m, 15490 m/sec, 2150322 t fired, . Pages in use: 462 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 42/2000 DLCflexbar-PT-4b-LTLFireability-00 1812942 m, 15331 m/sec, 2243080 t fired, . Pages in use: 464 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 43/2000 DLCflexbar-PT-4b-LTLFireability-00 1887483 m, 14908 m/sec, 2338015 t fired, . Pages in use: 467 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 45/2000 DLCflexbar-PT-4b-LTLFireability-00 1960771 m, 14657 m/sec, 2432746 t fired, . Pages in use: 470 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 46/2000 DLCflexbar-PT-4b-LTLFireability-00 2037172 m, 15280 m/sec, 2526336 t fired, . Pages in use: 472 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 48/2000 DLCflexbar-PT-4b-LTLFireability-00 2113334 m, 15232 m/sec, 2618880 t fired, . Pages in use: 476 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 49/2000 DLCflexbar-PT-4b-LTLFireability-00 2190284 m, 15390 m/sec, 2712607 t fired, . Pages in use: 478 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 50/2000 DLCflexbar-PT-4b-LTLFireability-00 2267584 m, 15460 m/sec, 2806452 t fired, . Pages in use: 480 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 52/2000 DLCflexbar-PT-4b-LTLFireability-00 2344683 m, 15419 m/sec, 2900131 t fired, . Pages in use: 483 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 53/2000 DLCflexbar-PT-4b-LTLFireability-00 2421842 m, 15431 m/sec, 2994212 t fired, . Pages in use: 485 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 55/2000 DLCflexbar-PT-4b-LTLFireability-00 2498911 m, 15413 m/sec, 3088119 t fired, . Pages in use: 488 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 56/2000 DLCflexbar-PT-4b-LTLFireability-00 2575884 m, 15394 m/sec, 3181759 t fired, . Pages in use: 490 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 57/2000 DLCflexbar-PT-4b-LTLFireability-00 2652896 m, 15402 m/sec, 3275304 t fired, . Pages in use: 492 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 58/2000 DLCflexbar-PT-4b-LTLFireability-00 2729860 m, 15392 m/sec, 3369338 t fired, . Pages in use: 494 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 60/2000 DLCflexbar-PT-4b-LTLFireability-00 2807589 m, 15545 m/sec, 3463492 t fired, . Pages in use: 497 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 61/2000 DLCflexbar-PT-4b-LTLFireability-00 2884013 m, 15284 m/sec, 3556340 t fired, . Pages in use: 499 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 63/2000 DLCflexbar-PT-4b-LTLFireability-00 2960340 m, 15265 m/sec, 3650638 t fired, . Pages in use: 502 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 64/2000 DLCflexbar-PT-4b-LTLFireability-00 3037735 m, 15479 m/sec, 3745661 t fired, . Pages in use: 504 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 66/2000 DLCflexbar-PT-4b-LTLFireability-00 3114205 m, 15294 m/sec, 3840232 t fired, . Pages in use: 507 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 67/2000 DLCflexbar-PT-4b-LTLFireability-00 3187725 m, 14704 m/sec, 3936329 t fired, . Pages in use: 509 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 68/2000 DLCflexbar-PT-4b-LTLFireability-00 3261231 m, 14701 m/sec, 4031817 t fired, . Pages in use: 511 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 69/2000 DLCflexbar-PT-4b-LTLFireability-00 3334282 m, 14610 m/sec, 4127368 t fired, . Pages in use: 513 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 71/2000 DLCflexbar-PT-4b-LTLFireability-00 3409404 m, 15024 m/sec, 4221786 t fired, . Pages in use: 516 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 72/2000 DLCflexbar-PT-4b-LTLFireability-00 3485846 m, 15288 m/sec, 4315421 t fired, . Pages in use: 519 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 73/2000 DLCflexbar-PT-4b-LTLFireability-00 3562218 m, 15274 m/sec, 4408339 t fired, . Pages in use: 521 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 74/2000 DLCflexbar-PT-4b-LTLFireability-00 3638740 m, 15304 m/sec, 4501108 t fired, . Pages in use: 523 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 75/2000 DLCflexbar-PT-4b-LTLFireability-00 3715533 m, 15358 m/sec, 4594790 t fired, . Pages in use: 525 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 77/2000 DLCflexbar-PT-4b-LTLFireability-00 3792420 m, 15377 m/sec, 4688551 t fired, . Pages in use: 529 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 78/2000 DLCflexbar-PT-4b-LTLFireability-00 3869094 m, 15334 m/sec, 4782453 t fired, . Pages in use: 531 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 80/2000 DLCflexbar-PT-4b-LTLFireability-00 3945151 m, 15211 m/sec, 4876343 t fired, . Pages in use: 534 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 81/2000 DLCflexbar-PT-4b-LTLFireability-00 4021546 m, 15279 m/sec, 4970293 t fired, . Pages in use: 537 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 83/2000 DLCflexbar-PT-4b-LTLFireability-00 4099159 m, 15522 m/sec, 5064541 t fired, . Pages in use: 540 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 84/2000 DLCflexbar-PT-4b-LTLFireability-00 4176013 m, 15370 m/sec, 5157900 t fired, . Pages in use: 543 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 85/2000 DLCflexbar-PT-4b-LTLFireability-00 4251602 m, 15117 m/sec, 5252578 t fired, . Pages in use: 545 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 86/2000 DLCflexbar-PT-4b-LTLFireability-00 4328702 m, 15420 m/sec, 5346216 t fired, . Pages in use: 547 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 88/2000 DLCflexbar-PT-4b-LTLFireability-00 4403861 m, 15031 m/sec, 5440151 t fired, . Pages in use: 550 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 89/2000 DLCflexbar-PT-4b-LTLFireability-00 4479486 m, 15125 m/sec, 5534457 t fired, . Pages in use: 552 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 90/2000 DLCflexbar-PT-4b-LTLFireability-00 4556199 m, 15342 m/sec, 5627960 t fired, . Pages in use: 555 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 92/2000 DLCflexbar-PT-4b-LTLFireability-00 4632517 m, 15263 m/sec, 5721603 t fired, . Pages in use: 558 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 93/2000 DLCflexbar-PT-4b-LTLFireability-00 4707996 m, 15095 m/sec, 5815960 t fired, . Pages in use: 560 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 95/2000 DLCflexbar-PT-4b-LTLFireability-00 4785203 m, 15441 m/sec, 5909960 t fired, . Pages in use: 563 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 96/2000 DLCflexbar-PT-4b-LTLFireability-00 4861859 m, 15331 m/sec, 6003637 t fired, . Pages in use: 565 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 97/2000 DLCflexbar-PT-4b-LTLFireability-00 4937579 m, 15144 m/sec, 6096902 t fired, . Pages in use: 567 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 98/2000 DLCflexbar-PT-4b-LTLFireability-00 5013677 m, 15219 m/sec, 6190069 t fired, . Pages in use: 569 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 99/2000 DLCflexbar-PT-4b-LTLFireability-00 5089547 m, 15174 m/sec, 6282200 t fired, . Pages in use: 571 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 100/2000 DLCflexbar-PT-4b-LTLFireability-00 5163103 m, 14711 m/sec, 6375034 t fired, . Pages in use: 573 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 102/2000 DLCflexbar-PT-4b-LTLFireability-00 5236373 m, 14654 m/sec, 6469601 t fired, . Pages in use: 576 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 103/2000 DLCflexbar-PT-4b-LTLFireability-00 5312716 m, 15268 m/sec, 6562166 t fired, . Pages in use: 579 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 104/2000 DLCflexbar-PT-4b-LTLFireability-00 5383790 m, 14214 m/sec, 6657194 t fired, . Pages in use: 581 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 105/2000 DLCflexbar-PT-4b-LTLFireability-00 5454214 m, 14084 m/sec, 6751524 t fired, . Pages in use: 583 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 107/2000 DLCflexbar-PT-4b-LTLFireability-00 5529244 m, 15006 m/sec, 6843395 t fired, . Pages in use: 586 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 108/2000 DLCflexbar-PT-4b-LTLFireability-00 5604892 m, 15129 m/sec, 6935792 t fired, . Pages in use: 589 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 109/2000 DLCflexbar-PT-4b-LTLFireability-00 5674763 m, 13974 m/sec, 7032420 t fired, . Pages in use: 591 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 111/2000 DLCflexbar-PT-4b-LTLFireability-00 5747174 m, 14482 m/sec, 7127148 t fired, . Pages in use: 594 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 112/2000 DLCflexbar-PT-4b-LTLFireability-00 5819591 m, 14483 m/sec, 7221286 t fired, . Pages in use: 596 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 113/2000 DLCflexbar-PT-4b-LTLFireability-00 5895219 m, 15125 m/sec, 7313624 t fired, . Pages in use: 599 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL false LTL model checker[0m AG false state space[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 115/2000 DLCflexbar-PT-4b-LTLFireability-00 5970906 m, 15137 m/sec, 7406002 t fired, . Pages in use: 602 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-4b"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is DLCflexbar-PT-4b, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r115-smll-171624276200044"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-4b.tgz
mv DLCflexbar-PT-4b execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;