fond
Model Checking Contest 2024
14th edition, Geneva, Switzerland, June 25, 2024
Execution of r115-smll-171624276200035
Last Updated
July 7, 2024

About the Execution of LoLA for DLCflexbar-PT-4a

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
16209.115 190891.00 137950.00 1116.60 [undef] Cannot compute

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r115-smll-171624276200035.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is DLCflexbar-PT-4a, examination is LTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r115-smll-171624276200035
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 2.1M
-rw-r--r-- 1 mcc users 6.8K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 73K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.5K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 52K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.3K Apr 22 14:37 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Apr 22 14:37 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Apr 22 14:37 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 22 14:37 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Apr 12 17:36 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 112K Apr 12 17:36 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.7K Apr 12 16:51 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 62K Apr 12 16:51 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 22 14:37 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Apr 22 14:37 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 3 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 1.7M May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCflexbar-PT-4a-LTLCardinality-00
FORMULA_NAME DLCflexbar-PT-4a-LTLCardinality-01
FORMULA_NAME DLCflexbar-PT-4a-LTLCardinality-02
FORMULA_NAME DLCflexbar-PT-4a-LTLCardinality-03
FORMULA_NAME DLCflexbar-PT-4a-LTLCardinality-04
FORMULA_NAME DLCflexbar-PT-4a-LTLCardinality-05
FORMULA_NAME DLCflexbar-PT-4a-LTLCardinality-06
FORMULA_NAME DLCflexbar-PT-4a-LTLCardinality-07
FORMULA_NAME DLCflexbar-PT-4a-LTLCardinality-08
FORMULA_NAME DLCflexbar-PT-4a-LTLCardinality-09
FORMULA_NAME DLCflexbar-PT-4a-LTLCardinality-10
FORMULA_NAME DLCflexbar-PT-4a-LTLCardinality-11
FORMULA_NAME DLCflexbar-PT-4a-LTLCardinality-12
FORMULA_NAME DLCflexbar-PT-4a-LTLCardinality-13
FORMULA_NAME DLCflexbar-PT-4a-LTLCardinality-14
FORMULA_NAME DLCflexbar-PT-4a-LTLCardinality-15

=== Now, execution of the tool begins

BK_START 1717014246764


BK_STOP 1717014437655

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains place/transition net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading formula.
[lola][I] Using XML format (--xmlformula)
[lola][I] reading XML formula
[lola][I] reading formula from LTLCardinality.xml
[lola][I] NOTDEADLOCKFREE
[lola][I] LAUNCH task # 52 (type SKEL/SRCH) for 12 DLCflexbar-PT-4a-LTLCardinality-04
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 52 (type SKEL/SRCH) for DLCflexbar-PT-4a-LTLCardinality-04
[lola][I] result : false
[lola][I] markings : 6
[lola][I] fired transitions : 6
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] NOTDEADLOCKFREE
[lola][I] LAUNCH task # 53 (type SKEL/SRCH) for 3 DLCflexbar-PT-4a-LTLCardinality-01
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 53 (type SKEL/SRCH) for DLCflexbar-PT-4a-LTLCardinality-01
[lola][I] result : true
[lola][I] markings : 2
[lola][I] fired transitions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] Rule S: 0 transitions removed,0 places removed
[lola][I] NOTDEADLOCKFREE
[lola][I] NOTDEADLOCKFREE
[lola][I] NOTDEADLOCKFREE
[lola][I] LAUNCH task # 50 (type CNST) for 49 DLCflexbar-PT-4a-LTLCardinality-15
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] LAUNCH task # 54 (type SKEL/SRCH) for 9 DLCflexbar-PT-4a-LTLCardinality-03
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 50 (type CNST) for DLCflexbar-PT-4a-LTLCardinality-15
[lola][I] result : false
[lola][I] LAUNCH task # 55 (type SKEL/SRCH) for 6 DLCflexbar-PT-4a-LTLCardinality-02
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 54 (type SKEL/SRCH) for DLCflexbar-PT-4a-LTLCardinality-03
[lola][I] result : true
[lola][I] markings : 8
[lola][I] fired transitions : 11
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] FINISHED task # 55 (type SKEL/SRCH) for DLCflexbar-PT-4a-LTLCardinality-02
[lola][I] result : false
[lola][I] markings : 3
[lola][I] fired transitions : 3
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] NOTDEADLOCKFREE
[lola][I] planning for DLCflexbar-PT-4a-LTLCardinality-02 stopped (result already fixed).
[lola][I] planning for DLCflexbar-PT-4a-LTLCardinality-03 stopped (result already fixed).
[lola][I] LAUNCH task # 35 (type CNST) for 34 DLCflexbar-PT-4a-LTLCardinality-10
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] LAUNCH task # 56 (type SKEL/SRCH) for 0 DLCflexbar-PT-4a-LTLCardinality-00
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 35 (type CNST) for DLCflexbar-PT-4a-LTLCardinality-10
[lola][I] result : false
[lola][I] NOTDEADLOCKFREE
[lola][I] LAUNCH task # 25 (type CNST) for 24 DLCflexbar-PT-4a-LTLCardinality-08
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] LAUNCH task # 41 (type CNST) for 40 DLCflexbar-PT-4a-LTLCardinality-12
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] LAUNCH task # 47 (type CNST) for 46 DLCflexbar-PT-4a-LTLCardinality-14
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] FINISHED task # 41 (type CNST) for DLCflexbar-PT-4a-LTLCardinality-12
[lola][I] result : true
[lola][I] LAUNCH task # 57 (type SKEL/SRCH) for 18 DLCflexbar-PT-4a-LTLCardinality-06
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 57 (type SKEL/SRCH) for DLCflexbar-PT-4a-LTLCardinality-06
[lola][I] result : false
[lola][I] markings : 4
[lola][I] fired transitions : 4
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] FINISHED task # 25 (type CNST) for DLCflexbar-PT-4a-LTLCardinality-08
[lola][I] result : false
[lola][I] FINISHED task # 47 (type CNST) for DLCflexbar-PT-4a-LTLCardinality-14
[lola][I] result : true
[lola][I] NOTDEADLOCKFREE
[lola][I] NOTDEADLOCKFREE
[lola][I] NOTDEADLOCKFREE
[lola][I] LAUNCH task # 58 (type SKEL/SRCH) for 21 DLCflexbar-PT-4a-LTLCardinality-07
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 58 (type SKEL/SRCH) for DLCflexbar-PT-4a-LTLCardinality-07
[lola][I] result : true
[lola][I] markings : 35
[lola][I] fired transitions : 89
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] NOTDEADLOCKFREE
[lola][I] LAUNCH task # 59 (type SKEL/SRCH) for 27 DLCflexbar-PT-4a-LTLCardinality-09
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] NOTDEADLOCKFREE
[lola][I] LAUNCH task # 60 (type SKEL/SRCH) for 27 DLCflexbar-PT-4a-LTLCardinality-09
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 59 (type SKEL/SRCH) for DLCflexbar-PT-4a-LTLCardinality-09
[lola][I] result : false
[lola][I] markings : 4
[lola][I] fired transitions : 4
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] FINISHED task # 60 (type SKEL/SRCH) for DLCflexbar-PT-4a-LTLCardinality-09
[lola][I] result : true
[lola][I] markings : 2
[lola][I] fired transitions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] planning for DLCflexbar-PT-4a-LTLCardinality-07 stopped (result already fixed).
[lola][I] LAUNCH task # 38 (type EXCL) for 37 DLCflexbar-PT-4a-LTLCardinality-11
[lola][I] time limit : 399 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 38 (type EXCL) for DLCflexbar-PT-4a-LTLCardinality-11
[lola][I] result : false
[lola][I] markings : 3
[lola][I] fired transitions : 4
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 13 (type EXCL) for 12 DLCflexbar-PT-4a-LTLCardinality-04
[lola][I] time limit : 448 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 13 (type EXCL) for DLCflexbar-PT-4a-LTLCardinality-04
[lola][I] result : false
[lola][I] markings : 5
[lola][I] fired transitions : 5
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 44 (type EXCL) for 43 DLCflexbar-PT-4a-LTLCardinality-13
[lola][I] time limit : 513 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCflexbar-PT-4a-LTLCardinality-02: LTL/CTL false skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-03: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-04: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-07: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-08: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-10: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-11: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-12: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-14: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-15: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-4a-LTLCardinality-00: LTL 0 1 1 0 0 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-09: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 44 LTL EXCL 1/513 1/2000 DLCflexbar-PT-4a-LTLCardinality-13 11282 m, 2256 m/sec, 548275 t fired, .
[lola][.] 56 LTL SRCH 4/3594 1/5 DLCflexbar-PT-4a-LTLCardinality-00 180211 m, 36042 m/sec, 2051750 t fired, .
[lola][.]
[lola][.] Time elapsed: 10 secs. Pages in use: 2
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[lola][I] FINISHED task # 56 (type SKEL/SRCH) for DLCflexbar-PT-4a-LTLCardinality-00
[lola][I] result : false
[lola][I] markings : 180338
[lola][I] fired transitions : 2053526
[lola][I] time used : 4
[lola][I] memory pages used : 1
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCflexbar-PT-4a-LTLCardinality-02: LTL/CTL false skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-03: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-04: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-07: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-08: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-10: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-11: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-12: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-14: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-15: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-4a-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-09: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 44 LTL EXCL 6/513 1/2000 DLCflexbar-PT-4a-LTLCardinality-13 80950 m, 13933 m/sec, 3945118 t fired, .
[lola][.]
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[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCflexbar-PT-4a-LTLCardinality-02: LTL/CTL false skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-03: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-04: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-07: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-08: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-10: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-11: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-12: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-14: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-15: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-4a-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-09: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 44 LTL EXCL 11/513 2/2000 DLCflexbar-PT-4a-LTLCardinality-13 156655 m, 15141 m/sec, 7428775 t fired, .
[lola][.]
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[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCflexbar-PT-4a-LTLCardinality-02: LTL/CTL false skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-03: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-04: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-07: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-08: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-10: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-11: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-12: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-14: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-15: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-4a-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-09: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 44 LTL EXCL 16/513 2/2000 DLCflexbar-PT-4a-LTLCardinality-13 231963 m, 15061 m/sec, 10894671 t fired, .
[lola][.]
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[lola][.] DLCflexbar-PT-4a-LTLCardinality-02: LTL/CTL false skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-03: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-04: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-07: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-08: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-10: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-11: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-12: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-14: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-15: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-4a-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-09: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 44 LTL EXCL 21/513 2/2000 DLCflexbar-PT-4a-LTLCardinality-13 302282 m, 14063 m/sec, 14321831 t fired, .
[lola][.]
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[lola][.] DLCflexbar-PT-4a-LTLCardinality-02: LTL/CTL false skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-03: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-04: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-07: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-08: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-10: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-11: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-12: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-14: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-15: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-4a-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-09: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 44 LTL EXCL 26/513 3/2000 DLCflexbar-PT-4a-LTLCardinality-13 379841 m, 15511 m/sec, 17691282 t fired, .
[lola][.]
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[lola][.] DLCflexbar-PT-4a-LTLCardinality-02: LTL/CTL false skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-03: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-04: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-07: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-08: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-10: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-11: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-12: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-14: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-15: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-4a-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-09: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 44 LTL EXCL 31/513 3/2000 DLCflexbar-PT-4a-LTLCardinality-13 450329 m, 14097 m/sec, 21127354 t fired, .
[lola][.]
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[lola][.] DLCflexbar-PT-4a-LTLCardinality-02: LTL/CTL false skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-03: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-04: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-07: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-08: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-10: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-11: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-12: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-14: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-15: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-4a-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-09: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 44 LTL EXCL 36/513 4/2000 DLCflexbar-PT-4a-LTLCardinality-13 525559 m, 15046 m/sec, 24466530 t fired, .
[lola][.]
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[lola][.] DLCflexbar-PT-4a-LTLCardinality-02: LTL/CTL false skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-03: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-04: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-07: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-08: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-10: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-11: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-12: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-14: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-15: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-4a-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-09: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 44 LTL EXCL 41/513 4/2000 DLCflexbar-PT-4a-LTLCardinality-13 596649 m, 14218 m/sec, 27847168 t fired, .
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[lola][.] DLCflexbar-PT-4a-LTLCardinality-02: LTL/CTL false skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-03: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-04: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-07: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-08: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-10: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-11: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-12: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-14: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-15: INITIAL false preprocessing
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[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-4a-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-09: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 44 LTL EXCL 46/513 5/2000 DLCflexbar-PT-4a-LTLCardinality-13 664987 m, 13667 m/sec, 31178708 t fired, .
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[lola][.] DLCflexbar-PT-4a-LTLCardinality-02: LTL/CTL false skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-03: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-04: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-07: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-08: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-10: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-11: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-12: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-14: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-15: INITIAL false preprocessing
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[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-4a-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-09: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 44 LTL EXCL 51/513 5/2000 DLCflexbar-PT-4a-LTLCardinality-13 741397 m, 15282 m/sec, 34492491 t fired, .
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[lola][.] DLCflexbar-PT-4a-LTLCardinality-02: LTL/CTL false skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-03: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-04: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-07: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-08: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-10: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-11: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-12: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-14: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-15: INITIAL false preprocessing
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[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-4a-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-09: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 44 LTL EXCL 56/513 6/2000 DLCflexbar-PT-4a-LTLCardinality-13 810268 m, 13774 m/sec, 37847333 t fired, .
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[lola][.] DLCflexbar-PT-4a-LTLCardinality-02: LTL/CTL false skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-03: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-04: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-07: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-08: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-10: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-11: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-12: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-14: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-15: INITIAL false preprocessing
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[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-4a-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-09: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 44 LTL EXCL 61/513 6/2000 DLCflexbar-PT-4a-LTLCardinality-13 884687 m, 14883 m/sec, 41124368 t fired, .
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[lola][.] DLCflexbar-PT-4a-LTLCardinality-02: LTL/CTL false skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-03: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-04: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-07: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-08: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-10: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-11: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-12: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-14: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-15: INITIAL false preprocessing
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[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-4a-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-09: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 44 LTL EXCL 66/513 7/2000 DLCflexbar-PT-4a-LTLCardinality-13 953795 m, 13821 m/sec, 44437979 t fired, .
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[lola][.] DLCflexbar-PT-4a-LTLCardinality-02: LTL/CTL false skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-03: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-04: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-07: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-08: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-10: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-11: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-12: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-14: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-15: INITIAL false preprocessing
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[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-4a-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-09: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 44 LTL EXCL 71/513 7/2000 DLCflexbar-PT-4a-LTLCardinality-13 1021673 m, 13575 m/sec, 47745661 t fired, .
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[lola][.] DLCflexbar-PT-4a-LTLCardinality-02: LTL/CTL false skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-03: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-04: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-07: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-08: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-10: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-11: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-12: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-14: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-15: INITIAL false preprocessing
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[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-4a-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-09: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
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[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 44 LTL EXCL 76/513 8/2000 DLCflexbar-PT-4a-LTLCardinality-13 1097469 m, 15159 m/sec, 51038081 t fired, .
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[lola][.] DLCflexbar-PT-4a-LTLCardinality-02: LTL/CTL false skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-03: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-04: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-07: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-08: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-10: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-11: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-12: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-14: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-15: INITIAL false preprocessing
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[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-4a-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-09: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
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[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 44 LTL EXCL 81/513 8/2000 DLCflexbar-PT-4a-LTLCardinality-13 1167303 m, 13966 m/sec, 54440699 t fired, .
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[lola][.] DLCflexbar-PT-4a-LTLCardinality-02: LTL/CTL false skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-03: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-04: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-07: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-08: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-10: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-11: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-12: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-14: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-15: INITIAL false preprocessing
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[lola][.] DLCflexbar-PT-4a-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
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[lola][.] DLCflexbar-PT-4a-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-09: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
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[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 44 LTL EXCL 86/513 9/2000 DLCflexbar-PT-4a-LTLCardinality-13 1242953 m, 15130 m/sec, 57758028 t fired, .
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[lola][.] DLCflexbar-PT-4a-LTLCardinality-02: LTL/CTL false skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-03: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-04: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-07: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-08: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-10: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-11: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-12: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-14: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-15: INITIAL false preprocessing
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[lola][.] DLCflexbar-PT-4a-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-09: CONJ 0 2 0 0 2 0 0 0
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[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 44 LTL EXCL 91/513 9/2000 DLCflexbar-PT-4a-LTLCardinality-13 1312599 m, 13929 m/sec, 61112405 t fired, .
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[lola][.] DLCflexbar-PT-4a-LTLCardinality-02: LTL/CTL false skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-03: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-04: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-07: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-08: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-10: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-11: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-12: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-14: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-15: INITIAL false preprocessing
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[lola][.] DLCflexbar-PT-4a-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-09: CONJ 0 2 0 0 2 0 0 0
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[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 44 LTL EXCL 96/513 9/2000 DLCflexbar-PT-4a-LTLCardinality-13 1380593 m, 13598 m/sec, 64427316 t fired, .
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[lola][.] DLCflexbar-PT-4a-LTLCardinality-03: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-04: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-07: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-08: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-10: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-11: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-12: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-14: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-15: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-4a-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-09: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 44 LTL EXCL 101/513 10/2000 DLCflexbar-PT-4a-LTLCardinality-13 1456058 m, 15093 m/sec, 67691636 t fired, .
[lola][.]
[lola][.] Time elapsed: 110 secs. Pages in use: 10
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[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCflexbar-PT-4a-LTLCardinality-02: LTL/CTL false skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-03: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-04: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-07: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-08: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-10: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-11: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-12: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-14: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-15: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-4a-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-09: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 44 LTL EXCL 106/513 10/2000 DLCflexbar-PT-4a-LTLCardinality-13 1524299 m, 13648 m/sec, 71018849 t fired, .
[lola][.]
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[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DLCflexbar-PT-4a-LTLCardinality-02: LTL/CTL false skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-03: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-04: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-07: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-08: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-10: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-11: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-12: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-14: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-15: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-4a-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-09: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 44 LTL EXCL 111/513 11/2000 DLCflexbar-PT-4a-LTLCardinality-13 1598411 m, 14822 m/sec, 74268803 t fired, .
[lola][.]
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[lola][.] DLCflexbar-PT-4a-LTLCardinality-02: LTL/CTL false skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-03: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-04: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-07: LTL true skeleton: LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-08: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-10: INITIAL false preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-11: LTL false LTL model checker
[lola][.] DLCflexbar-PT-4a-LTLCardinality-12: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-14: INITIAL true preprocessing
[lola][.] DLCflexbar-PT-4a-LTLCardinality-15: INITIAL false preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DLCflexbar-PT-4a-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-01: LTL/CTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-09: CONJ 0 2 0 0 2 0 0 0
[lola][.] DLCflexbar-PT-4a-LTLCardinality-13: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 44 LTL EXCL 149/513 11/2000 DLCflexbar-PT-4a-LTLCardinality-13 1623227 m, 4963 m/sec, 75428612 t fired, .
[lola][.]
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/home/mcc/BenchKit/BenchKit_head.sh: line 23: 408 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-4a"
export BK_EXAMINATION="LTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is DLCflexbar-PT-4a, examination is LTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r115-smll-171624276200035"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-4a.tgz
mv DLCflexbar-PT-4a execution
cd execution
if [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "UpperBounds" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] || [ "LTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;