About the Execution of LoLA for DLCflexbar-PT-4a
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
16205.252 | 1062006.00 | 1077453.00 | 4192.80 | ???F?FFFT?FFT??? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r115-smll-171624276200033.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is DLCflexbar-PT-4a, examination is CTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r115-smll-171624276200033
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 2.1M
-rw-r--r-- 1 mcc users 6.8K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 73K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.5K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 52K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.3K Apr 22 14:37 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Apr 22 14:37 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Apr 22 14:37 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 22 14:37 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Apr 12 17:36 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 112K Apr 12 17:36 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.7K Apr 12 16:51 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 62K Apr 12 16:51 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 22 14:37 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Apr 22 14:37 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 3 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 1.7M May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCflexbar-PT-4a-CTLCardinality-2024-00
FORMULA_NAME DLCflexbar-PT-4a-CTLCardinality-2024-01
FORMULA_NAME DLCflexbar-PT-4a-CTLCardinality-2024-02
FORMULA_NAME DLCflexbar-PT-4a-CTLCardinality-2024-03
FORMULA_NAME DLCflexbar-PT-4a-CTLCardinality-2024-04
FORMULA_NAME DLCflexbar-PT-4a-CTLCardinality-2024-05
FORMULA_NAME DLCflexbar-PT-4a-CTLCardinality-2024-06
FORMULA_NAME DLCflexbar-PT-4a-CTLCardinality-2024-07
FORMULA_NAME DLCflexbar-PT-4a-CTLCardinality-2024-08
FORMULA_NAME DLCflexbar-PT-4a-CTLCardinality-2024-09
FORMULA_NAME DLCflexbar-PT-4a-CTLCardinality-2024-10
FORMULA_NAME DLCflexbar-PT-4a-CTLCardinality-2024-11
FORMULA_NAME DLCflexbar-PT-4a-CTLCardinality-2023-12
FORMULA_NAME DLCflexbar-PT-4a-CTLCardinality-2023-13
FORMULA_NAME DLCflexbar-PT-4a-CTLCardinality-2023-14
FORMULA_NAME DLCflexbar-PT-4a-CTLCardinality-2023-15
=== Now, execution of the tool begins
BK_START 1717012458051
FORMULA DLCflexbar-PT-4a-CTLCardinality-2024-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-4a-CTLCardinality-2024-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-4a-CTLCardinality-2024-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-4a-CTLCardinality-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-4a-CTLCardinality-2024-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-4a-CTLCardinality-2024-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-4a-CTLCardinality-2023-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-4a-CTLCardinality-2024-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717013520057
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLCardinality.xml[0m
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 10 (type CNST) for 9 DLCflexbar-PT-4a-CTLCardinality-2024-03
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 19 (type CNST) for 18 DLCflexbar-PT-4a-CTLCardinality-2024-06
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 22 (type CNST) for 21 DLCflexbar-PT-4a-CTLCardinality-2024-07
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 10 (type CNST) for DLCflexbar-PT-4a-CTLCardinality-2024-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 25 (type CNST) for 24 DLCflexbar-PT-4a-CTLCardinality-2024-08
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 22 (type CNST) for DLCflexbar-PT-4a-CTLCardinality-2024-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 19 (type CNST) for DLCflexbar-PT-4a-CTLCardinality-2024-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 25 (type CNST) for DLCflexbar-PT-4a-CTLCardinality-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 16 (type CNST) for 15 DLCflexbar-PT-4a-CTLCardinality-2024-05
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 31 (type CNST) for 30 DLCflexbar-PT-4a-CTLCardinality-2024-10
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 34 (type CNST) for 33 DLCflexbar-PT-4a-CTLCardinality-2024-11
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 34 (type CNST) for DLCflexbar-PT-4a-CTLCardinality-2024-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 31 (type CNST) for DLCflexbar-PT-4a-CTLCardinality-2024-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 37 (type CNST) for 36 DLCflexbar-PT-4a-CTLCardinality-2023-12
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 37 (type CNST) for DLCflexbar-PT-4a-CTLCardinality-2023-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 16 (type CNST) for DLCflexbar-PT-4a-CTLCardinality-2024-05
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 28 (type EXCL) for 27 DLCflexbar-PT-4a-CTLCardinality-2024-09
[[35mlola[0m][I] time limit : 448 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 52 (type EQUN) for 45 DLCflexbar-PT-4a-CTLCardinality-2023-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 54 (type EQUN) for 45 DLCflexbar-PT-4a-CTLCardinality-2023-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 54 (type EQUN) for DLCflexbar-PT-4a-CTLCardinality-2023-15
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 52 (type EQUN) for DLCflexbar-PT-4a-CTLCardinality-2023-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 1/448 1/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 4395 m, 879 m/sec, 166282 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 6/448 1/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 94484 m, 18017 m/sec, 3218691 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 11/448 1/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 186071 m, 18317 m/sec, 6293267 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 16/448 2/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 284281 m, 19642 m/sec, 9321578 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 21/448 3/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 379828 m, 19109 m/sec, 12329057 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 26/448 3/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 470960 m, 18226 m/sec, 15343229 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 31/448 4/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 562892 m, 18386 m/sec, 18344950 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 36/448 4/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 651466 m, 17714 m/sec, 21355671 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 41/448 5/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 749028 m, 19512 m/sec, 24367645 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 46/448 5/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 844929 m, 19180 m/sec, 27369904 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 51/448 6/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 940739 m, 19162 m/sec, 30354587 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 56/448 6/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 1035035 m, 18859 m/sec, 33344086 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 61/448 7/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 1131018 m, 19196 m/sec, 36318885 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 66/448 7/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 1222701 m, 18336 m/sec, 39314798 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 71/448 8/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 1320494 m, 19558 m/sec, 42324803 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 76/448 8/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 1416198 m, 19140 m/sec, 45348965 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 81/448 9/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 1520148 m, 20790 m/sec, 48335943 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 86/448 9/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 1622457 m, 20461 m/sec, 51321188 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 91/448 10/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 1714712 m, 18451 m/sec, 54189765 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 96/448 10/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 1813108 m, 19679 m/sec, 57198067 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 101/448 11/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 1913957 m, 20169 m/sec, 60207223 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 106/448 11/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 2010092 m, 19227 m/sec, 63198121 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 111/448 12/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 2110606 m, 20102 m/sec, 66162574 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 116/448 12/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 2203427 m, 18564 m/sec, 68991579 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 121/448 13/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 2293487 m, 18012 m/sec, 71779804 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 126/448 13/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 2386565 m, 18615 m/sec, 74713407 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 140 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 131/448 14/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 2479940 m, 18675 m/sec, 77637024 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 145 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 136/448 14/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 2570705 m, 18153 m/sec, 80552121 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 141/448 15/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 2666571 m, 19173 m/sec, 83464245 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 155 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 146/448 15/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 2754164 m, 17518 m/sec, 86397863 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 160 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 151/448 16/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 2842206 m, 17608 m/sec, 89329433 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 165 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 156/448 16/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 2939168 m, 19392 m/sec, 92240840 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 170 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 161/448 17/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 3027835 m, 17733 m/sec, 95170700 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 175 secs. Pages in use: 17
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 166/448 17/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 3135749 m, 21582 m/sec, 98153205 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 180 secs. Pages in use: 17
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 171/448 18/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 3226209 m, 18092 m/sec, 101131039 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 185 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 176/448 18/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 3316138 m, 17985 m/sec, 104097017 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 190 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 181/448 19/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 3408044 m, 18381 m/sec, 107024215 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 195 secs. Pages in use: 19
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 186/448 19/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 3499726 m, 18336 m/sec, 109951484 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 200 secs. Pages in use: 19
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 191/448 20/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 3588915 m, 17837 m/sec, 112885693 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 205 secs. Pages in use: 20
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 196/448 20/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 3679778 m, 18172 m/sec, 115822959 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 210 secs. Pages in use: 20
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 201/448 21/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 3782301 m, 20504 m/sec, 118737428 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 215 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 206/448 21/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 3877724 m, 19084 m/sec, 121663162 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 220 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 211/448 22/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 3956740 m, 15803 m/sec, 124362911 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 225 secs. Pages in use: 22
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 216/448 22/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 4046468 m, 17945 m/sec, 127261088 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 230 secs. Pages in use: 22
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 221/448 23/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 4136359 m, 17978 m/sec, 130160752 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 235 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 226/448 23/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 4223199 m, 17368 m/sec, 133087248 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 240 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 231/448 24/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 4309973 m, 17354 m/sec, 135989605 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 245 secs. Pages in use: 24
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 236/448 24/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 4419560 m, 21917 m/sec, 138902361 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 250 secs. Pages in use: 24
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 241/448 25/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 4529624 m, 22012 m/sec, 141788090 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 255 secs. Pages in use: 25
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 246/448 25/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 4625141 m, 19103 m/sec, 144687548 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 260 secs. Pages in use: 25
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 251/448 26/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 4719811 m, 18934 m/sec, 147589258 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 265 secs. Pages in use: 26
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 256/448 26/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 4813636 m, 18765 m/sec, 150496802 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 270 secs. Pages in use: 26
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 261/448 27/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 4902093 m, 17691 m/sec, 153408514 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 275 secs. Pages in use: 27
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 266/448 27/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 4993579 m, 18297 m/sec, 156330404 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 280 secs. Pages in use: 27
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 271/448 28/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 5082306 m, 17745 m/sec, 159228901 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 285 secs. Pages in use: 28
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 276/448 28/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 5192697 m, 22078 m/sec, 162123333 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 290 secs. Pages in use: 28
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 281/448 29/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 5282517 m, 17964 m/sec, 165013783 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 295 secs. Pages in use: 29
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 286/448 29/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 5389052 m, 21307 m/sec, 167893155 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 300 secs. Pages in use: 29
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 291/448 30/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 5477206 m, 17630 m/sec, 170813082 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 305 secs. Pages in use: 30
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 296/448 30/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 5574463 m, 19451 m/sec, 173705725 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 310 secs. Pages in use: 30
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 301/448 31/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 5673773 m, 19862 m/sec, 176595170 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 315 secs. Pages in use: 31
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 306/448 31/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 5768587 m, 18962 m/sec, 179495413 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 320 secs. Pages in use: 31
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 311/448 32/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 5872342 m, 20751 m/sec, 182386943 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 325 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 316/448 33/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 5973600 m, 20251 m/sec, 185286713 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 330 secs. Pages in use: 33
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 321/448 33/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 6062982 m, 17876 m/sec, 188218788 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 335 secs. Pages in use: 33
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 326/448 34/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 6159460 m, 19295 m/sec, 191132149 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 340 secs. Pages in use: 34
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 331/448 34/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 6260209 m, 20149 m/sec, 193920831 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 345 secs. Pages in use: 34
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 336/448 35/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 6356852 m, 19328 m/sec, 196804037 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 350 secs. Pages in use: 35
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 341/448 35/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 6448679 m, 18365 m/sec, 199690970 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 355 secs. Pages in use: 35
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 346/448 36/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 6542861 m, 18836 m/sec, 202576239 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 360 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 351/448 36/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 6634578 m, 18343 m/sec, 205485519 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 365 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 356/448 37/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 6732609 m, 19606 m/sec, 208363480 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 370 secs. Pages in use: 37
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 361/448 37/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 6825437 m, 18565 m/sec, 211253104 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 375 secs. Pages in use: 37
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 366/448 38/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 6917131 m, 18338 m/sec, 214003373 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 380 secs. Pages in use: 38
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 371/448 38/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 7011387 m, 18851 m/sec, 216910796 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 385 secs. Pages in use: 38
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 376/448 39/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 7106647 m, 19052 m/sec, 219794269 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 390 secs. Pages in use: 39
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 381/448 39/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 7195179 m, 17706 m/sec, 222693188 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 395 secs. Pages in use: 39
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 386/448 40/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 7287210 m, 18406 m/sec, 225571354 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 400 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 391/448 40/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 7385667 m, 19691 m/sec, 228444172 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 405 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 396/448 41/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 7478500 m, 18566 m/sec, 231337452 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 410 secs. Pages in use: 41
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 401/448 41/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 7570550 m, 18410 m/sec, 234227362 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 415 secs. Pages in use: 41
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 406/448 42/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 7669118 m, 19713 m/sec, 237085216 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 420 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 411/448 42/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 7764011 m, 18978 m/sec, 239968969 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 425 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 416/448 43/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 7861113 m, 19420 m/sec, 242849130 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 430 secs. Pages in use: 43
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 421/448 43/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 7956490 m, 19075 m/sec, 245730889 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 435 secs. Pages in use: 43
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 426/448 44/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 8053712 m, 19444 m/sec, 248606112 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 440 secs. Pages in use: 44
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 431/448 44/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 8158619 m, 20981 m/sec, 251464499 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 445 secs. Pages in use: 44
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 436/448 45/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 8256092 m, 19494 m/sec, 254342869 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 450 secs. Pages in use: 45
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 441/448 45/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 8350726 m, 18926 m/sec, 257223765 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 455 secs. Pages in use: 45
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 446/448 46/2000 DLCflexbar-PT-4a-CTLCardinality-2024-09 8447593 m, 19373 m/sec, 260098833 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 460 secs. Pages in use: 46
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 28 (type EXCL) for DLCflexbar-PT-4a-CTLCardinality-2024-09 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 465 secs. Pages in use: 46
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 43 (type EXCL) for 42 DLCflexbar-PT-4a-CTLCardinality-2023-14
[[35mlola[0m][I] time limit : 447 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 28 (type EXCL) for 27 DLCflexbar-PT-4a-CTLCardinality-2024-09
[[35mlola[0m][I] time limit : 3135 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 43 (type EXCL) for DLCflexbar-PT-4a-CTLCardinality-2023-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 5
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 4/447 1/5 DLCflexbar-PT-4a-CTLCardinality-2024-09 85535 m, -1672411 m/sec, 2896517 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 470 secs. Pages in use: 48
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 9/447 1/5 DLCflexbar-PT-4a-CTLCardinality-2024-09 177231 m, 18339 m/sec, 5978056 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 475 secs. Pages in use: 48
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 14/447 2/5 DLCflexbar-PT-4a-CTLCardinality-2024-09 274364 m, 19426 m/sec, 9020596 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 480 secs. Pages in use: 48
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 19/447 2/5 DLCflexbar-PT-4a-CTLCardinality-2024-09 370602 m, 19247 m/sec, 12042852 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 485 secs. Pages in use: 48
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 24/447 3/5 DLCflexbar-PT-4a-CTLCardinality-2024-09 462155 m, 18310 m/sec, 15067071 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 490 secs. Pages in use: 49
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 29/447 3/5 DLCflexbar-PT-4a-CTLCardinality-2024-09 554094 m, 18387 m/sec, 18076259 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 495 secs. Pages in use: 49
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 34/447 4/5 DLCflexbar-PT-4a-CTLCardinality-2024-09 642028 m, 17586 m/sec, 21087730 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 500 secs. Pages in use: 50
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 39/447 4/5 DLCflexbar-PT-4a-CTLCardinality-2024-09 741310 m, 19856 m/sec, 24095959 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 505 secs. Pages in use: 50
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 44/447 5/5 DLCflexbar-PT-4a-CTLCardinality-2024-09 837065 m, 19151 m/sec, 27105782 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 510 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 49/447 5/5 DLCflexbar-PT-4a-CTLCardinality-2024-09 930992 m, 18785 m/sec, 30090128 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 515 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 28 (type EXCL) for DLCflexbar-PT-4a-CTLCardinality-2024-09 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 520 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 13 (type EXCL) for 12 DLCflexbar-PT-4a-CTLCardinality-2024-04
[[35mlola[0m][I] time limit : 513 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 5/513 1/2000 DLCflexbar-PT-4a-CTLCardinality-2024-04 3 m, 0 m/sec, 3 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 525 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 10/513 1/2000 DLCflexbar-PT-4a-CTLCardinality-2024-04 4 m, 0 m/sec, 4 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 530 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 13 (type EXCL) for DLCflexbar-PT-4a-CTLCardinality-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 5
[[35mlola[0m][I] fired transitions : 6
[[35mlola[0m][I] time used : 15
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 DLCflexbar-PT-4a-CTLCardinality-2024-02
[[35mlola[0m][I] time limit : 613 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 0/613 1/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 2805 m, 561 m/sec, 117842 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 535 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 5/613 1/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 37456 m, 6930 m/sec, 3289360 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 540 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 10/613 1/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 71094 m, 6727 m/sec, 6396495 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 545 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 15/613 1/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 103319 m, 6445 m/sec, 9490765 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 550 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 20/613 1/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 136167 m, 6569 m/sec, 12577016 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 555 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 25/613 1/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 167998 m, 6366 m/sec, 15653680 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 560 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 30/613 2/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 200031 m, 6406 m/sec, 18721640 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 565 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 35/613 2/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 232192 m, 6432 m/sec, 21777495 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 570 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 40/613 2/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 264508 m, 6463 m/sec, 24837392 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 575 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 45/613 2/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 296114 m, 6321 m/sec, 27888286 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 580 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 50/613 2/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 327973 m, 6371 m/sec, 30942444 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 585 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 55/613 2/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 359827 m, 6370 m/sec, 33985397 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 590 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 60/613 3/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 392236 m, 6481 m/sec, 37044911 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 595 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 65/613 3/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 423761 m, 6305 m/sec, 40058566 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 600 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 70/613 3/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 455548 m, 6357 m/sec, 43103633 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 605 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 75/613 3/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 487042 m, 6298 m/sec, 46145632 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 610 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 80/613 3/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 518567 m, 6305 m/sec, 49192296 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 615 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 85/613 3/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 549996 m, 6285 m/sec, 52215865 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 620 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 90/613 4/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 581348 m, 6270 m/sec, 55251559 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 625 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 95/613 4/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 612029 m, 6136 m/sec, 58282294 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 630 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 100/613 4/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 643318 m, 6257 m/sec, 61313931 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 635 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 105/613 4/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 674857 m, 6307 m/sec, 64350863 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 640 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 110/613 4/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 705741 m, 6176 m/sec, 67380829 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 645 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 115/613 4/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 737272 m, 6306 m/sec, 70386658 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 650 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 120/613 5/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 768189 m, 6183 m/sec, 73419527 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 655 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 125/613 5/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 799683 m, 6298 m/sec, 76433305 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 660 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 130/613 5/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 831636 m, 6390 m/sec, 79442629 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 665 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 135/613 5/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 862486 m, 6170 m/sec, 82452516 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 670 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 140/613 5/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 893111 m, 6125 m/sec, 85469012 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 675 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 145/613 5/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 923848 m, 6147 m/sec, 88464310 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 680 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 150/613 6/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 954576 m, 6145 m/sec, 91467391 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 685 secs. Pages in use: 52
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 155/613 6/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 985118 m, 6108 m/sec, 94475432 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 690 secs. Pages in use: 52
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 160/613 6/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 1016590 m, 6294 m/sec, 97489928 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 695 secs. Pages in use: 52
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 165/613 6/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 1047451 m, 6172 m/sec, 100515573 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 700 secs. Pages in use: 52
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 170/613 6/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 1078141 m, 6138 m/sec, 103526549 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 705 secs. Pages in use: 52
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 175/613 6/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 1109527 m, 6277 m/sec, 106509967 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 710 secs. Pages in use: 52
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 180/613 7/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 1140384 m, 6171 m/sec, 109500629 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 715 secs. Pages in use: 53
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 185/613 7/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 1171636 m, 6250 m/sec, 112492865 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 720 secs. Pages in use: 53
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 190/613 7/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 1201953 m, 6063 m/sec, 115477360 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 725 secs. Pages in use: 53
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 195/613 7/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 1232635 m, 6136 m/sec, 118470070 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 730 secs. Pages in use: 53
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 200/613 7/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 1262591 m, 5991 m/sec, 121466181 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 735 secs. Pages in use: 53
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 205/613 7/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 1293248 m, 6131 m/sec, 124457042 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 740 secs. Pages in use: 53
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 210/613 8/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 1323911 m, 6132 m/sec, 127436505 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 745 secs. Pages in use: 54
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 215/613 8/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 1354292 m, 6076 m/sec, 130415079 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 750 secs. Pages in use: 54
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 220/613 8/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 1385455 m, 6232 m/sec, 133398263 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 755 secs. Pages in use: 54
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 225/613 8/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 1416125 m, 6134 m/sec, 136395779 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 760 secs. Pages in use: 54
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 230/613 8/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 1446388 m, 6052 m/sec, 139376386 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 765 secs. Pages in use: 54
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 235/613 8/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 1477188 m, 6160 m/sec, 142347144 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 770 secs. Pages in use: 54
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 240/613 9/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 1508403 m, 6243 m/sec, 145315115 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 775 secs. Pages in use: 55
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 245/613 9/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 1538633 m, 6046 m/sec, 148288666 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 780 secs. Pages in use: 55
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 250/613 9/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 1568644 m, 6002 m/sec, 151243324 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 785 secs. Pages in use: 55
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 255/613 9/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 1598763 m, 6023 m/sec, 154216535 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 790 secs. Pages in use: 55
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 260/613 9/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 1629357 m, 6118 m/sec, 157215568 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 795 secs. Pages in use: 55
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 265/613 9/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 1659658 m, 6060 m/sec, 160190226 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 800 secs. Pages in use: 55
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 270/613 10/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 1690591 m, 6186 m/sec, 163160746 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 805 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 275/613 10/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 1720554 m, 5992 m/sec, 166134937 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 810 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 280/613 10/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 1751985 m, 6286 m/sec, 169092503 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 815 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 285/613 10/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 1782338 m, 6070 m/sec, 172048546 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 820 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 290/613 10/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 1813011 m, 6134 m/sec, 175022879 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 825 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 295/613 10/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 1844325 m, 6262 m/sec, 178009923 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 830 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 300/613 11/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 1874337 m, 6002 m/sec, 180977695 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 835 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 305/613 11/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 1905006 m, 6133 m/sec, 183916012 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 840 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 310/613 11/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 1934899 m, 5978 m/sec, 186892064 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 845 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 315/613 11/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 1964905 m, 6001 m/sec, 189848328 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 850 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 320/613 11/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 1995600 m, 6139 m/sec, 192805874 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 855 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 325/613 11/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 2026137 m, 6107 m/sec, 195770192 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 860 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 330/613 12/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 2056713 m, 6115 m/sec, 198727804 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 865 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 335/613 12/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 2086897 m, 6036 m/sec, 201690492 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 870 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 340/613 12/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 2116843 m, 5989 m/sec, 204631774 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 875 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 345/613 12/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 2147072 m, 6045 m/sec, 207598240 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 880 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 350/613 12/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 2177423 m, 6070 m/sec, 210568416 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 885 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 355/613 12/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 2206762 m, 5867 m/sec, 213539396 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 890 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 360/613 12/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 2236947 m, 6037 m/sec, 216471885 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 895 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 365/613 13/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 2267387 m, 6088 m/sec, 219417969 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 900 secs. Pages in use: 59
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 370/613 13/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 2297528 m, 6028 m/sec, 222357459 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 905 secs. Pages in use: 59
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 375/613 13/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 2327740 m, 6042 m/sec, 225299360 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 910 secs. Pages in use: 59
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 380/613 13/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 2358350 m, 6122 m/sec, 228239098 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 915 secs. Pages in use: 59
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 385/613 13/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 2388107 m, 5951 m/sec, 231172789 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 920 secs. Pages in use: 59
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 390/613 13/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 2418484 m, 6075 m/sec, 234114248 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 925 secs. Pages in use: 59
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 395/613 14/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 2448926 m, 6088 m/sec, 237075510 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 930 secs. Pages in use: 60
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 400/613 14/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 2479363 m, 6087 m/sec, 240028061 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 935 secs. Pages in use: 60
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 405/613 14/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 2509067 m, 5940 m/sec, 242974989 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 940 secs. Pages in use: 60
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 410/613 14/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 2539583 m, 6103 m/sec, 245904823 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 945 secs. Pages in use: 60
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 415/613 14/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 2569438 m, 5971 m/sec, 248825292 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 950 secs. Pages in use: 60
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 420/613 14/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 2599477 m, 6007 m/sec, 251760092 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 955 secs. Pages in use: 60
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 425/613 15/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 2629516 m, 6007 m/sec, 254704291 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 960 secs. Pages in use: 61
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 430/613 15/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 2659637 m, 6024 m/sec, 257620555 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 965 secs. Pages in use: 61
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 435/613 15/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 2689810 m, 6034 m/sec, 260543660 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 970 secs. Pages in use: 61
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 440/613 15/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 2719532 m, 5944 m/sec, 263491255 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 975 secs. Pages in use: 61
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 445/613 15/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 2749210 m, 5935 m/sec, 266431432 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 980 secs. Pages in use: 61
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 450/613 15/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 2779130 m, 5984 m/sec, 269373834 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 985 secs. Pages in use: 61
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 455/613 16/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 2809159 m, 6005 m/sec, 272309061 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 990 secs. Pages in use: 62
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 460/613 16/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 2838580 m, 5884 m/sec, 275270350 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 995 secs. Pages in use: 62
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 465/613 16/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 2868698 m, 6023 m/sec, 278224173 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1000 secs. Pages in use: 62
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 470/613 16/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 2898586 m, 5977 m/sec, 281198776 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1005 secs. Pages in use: 62
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 475/613 16/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 2928765 m, 6035 m/sec, 284148599 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1010 secs. Pages in use: 62
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 480/613 16/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 2959090 m, 6065 m/sec, 287100143 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1015 secs. Pages in use: 62
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 485/613 17/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 2989538 m, 6089 m/sec, 290066421 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1020 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 490/613 17/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 3019405 m, 5973 m/sec, 293009427 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1025 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 495/613 17/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 3048941 m, 5907 m/sec, 295940667 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1030 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 500/613 17/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 3079069 m, 6025 m/sec, 298882525 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1035 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 505/613 17/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 3108615 m, 5909 m/sec, 301801962 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1040 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 510/613 17/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 3138697 m, 6016 m/sec, 304746433 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1045 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 515/613 17/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 3168862 m, 6033 m/sec, 307684755 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1050 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 520/613 18/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 3199101 m, 6047 m/sec, 310551104 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1055 secs. Pages in use: 64
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-03: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-05: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mDLCflexbar-PT-4a-CTLCardinality-2023-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDLCflexbar-PT-4a-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DLCflexbar-PT-4a-CTLCardinality-2023-15: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 525/613 18/2000 DLCflexbar-PT-4a-CTLCardinality-2024-02 3218689 m, 3917 m/sec, 312448843 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1060 secs. Pages in use: 64
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 406 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-4a"
export BK_EXAMINATION="CTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is DLCflexbar-PT-4a, examination is CTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r115-smll-171624276200033"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-4a.tgz
mv DLCflexbar-PT-4a execution
cd execution
if [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "UpperBounds" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] || [ "CTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;