MCC'2024- Execution of r115-smll-171624276200026

About the Execution of LoLA for DLCflexbar-PT-3b

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
0.000	929796.00	0.00	0.00	???T?????T??????	normal

Execution Chart

Sorry, for this execution, no execution chart could be reported.

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r115-smll-171624276200026.qcow2',
Waiting for the VM to be ready (probing ssh)
.............................................................
=======================================
Generated by BenchKit 2-5568
Executing tool lola
Input is DLCflexbar-PT-3b, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r115-smll-171624276200026
=============================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 3.0M
-rw-r--r-- 1 mcc users 6.8K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 71K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.9K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 43K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDef
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertiesVer
-rw-r--r-- 1 mcc users 3.9K Apr 22 14:37 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Apr 22 14:37 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K May 19 07:15 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K May 19 18:09 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Apr 12 13:00 ReachabilityCardinal
-rw-r--r-- 1 mcc users 138K Apr 12 13:00 ReachabilityCardinal
-rw-r--r-- 1 mcc users 8.3K Apr 12 12:59 ReachabilityFireabil
-rw-r--r-- 1 mcc users 70K Apr 12 12:59 ReachabilityFireabil
-rw-r--r-- 1 mcc users 1.6K Apr 22 14:37 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Apr 22 14:37 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 3 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 2.5M May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from
FORMULA_NAME DLCflexbar-PT-3b-CTLFireability-2024-00
FORMULA_NAME DLCflexbar-PT-3b-CTLFireability-2024-01
FORMULA_NAME DLCflexbar-PT-3b-CTLFireability-2024-02
FORMULA_NAME DLCflexbar-PT-3b-CTLFireability-2024-03
FORMULA_NAME DLCflexbar-PT-3b-CTLFireability-2024-04
FORMULA_NAME DLCflexbar-PT-3b-CTLFireability-2024-05
FORMULA_NAME DLCflexbar-PT-3b-CTLFireability-2024-06
FORMULA_NAME DLCflexbar-PT-3b-CTLFireability-2024-07
FORMULA_NAME DLCflexbar-PT-3b-CTLFireability-2024-08
FORMULA_NAME DLCflexbar-PT-3b-CTLFireability-2024-09
FORMULA_NAME DLCflexbar-PT-3b-CTLFireability-2024-10
FORMULA_NAME DLCflexbar-PT-3b-CTLFireability-2024-11
FORMULA_NAME DLCflexbar-PT-3b-CTLFireability-2023-12
FORMULA_NAME DLCflexbar-PT-3b-CTLFireability-2023-13
FORMULA_NAME DLCflexbar-PT-3b-CTLFireability-2023-14
FORMULA_NAME DLCflexbar-PT-3b-CTLFireability-2023-15

=== Now, execution of the tool begins

BK_START 1717009376313

FORMULA DLCflexbar-PT-3b-CTLFireability-2024-03
FORMULA DLCflexbar-PT-3b-CTLFireability-2024-09

BK_STOP 1717010306109

--------------------
content from stderr:

[[35mlola[0m][I] LoLA will run for 3600 seconds at
[[35mlola[0m][W] [1m[33munknown unit in memory specification:
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mm
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmo
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from
[[35mlola[0m][I] Rule S: 0 transitions removed,0
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] DLCflexbar-PT-3b-CTLFireability-2024-00:
[[35mlola[0m][.] DLCflexbar-PT-3b-CTLFireability-2024-01:
[[35mlola[0m][.] DLCflexbar-PT-3b-CTLFireability-2024-02:
[[35mlola[0m][.] DLCflexbar-PT-3b-CTLFireability-2024-03:
[[35mlola[0m][.] DLCflexbar-PT-3b-CTLFireability-2024-04:
[[35mlola[0m][.] DLCflexbar-PT-3b-CTLFireability-2024-05:
[[35mlola[0m][.] DLCflexbar-PT-3b-CTLFireability-2024-06:
[[35mlola[0m][.] DLCflexbar-PT-3b-CTLFireability-2024-07:
[[35mlola[0m][.] DLCflexbar-PT-3b-CTLFireability-2024-08:
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[[35mlola[0m][.] DLCflexbar-PT-3b-CTLFireability-2023-12:
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[[35mlola[0m][.]
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[[35mlola[0m][.] DLCflexbar-PT-3b-CTLFireability-2023-12:
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[[35mlola[0m][I] LAUNCH task # 14 (type EXCL) for
[[35mlola[0m][I] time limit : 181 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 55 (type EQUN) for
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 57 (type EQUN) for
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 14 (type EXCL)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 22
[[35mlola[0m][I] fired transitions : 88
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
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[[35mlola[0m][I] time limit : 191 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 52 (type EXCL)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 322
[[35mlola[0m][I] fired transitions : 322
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 55 (type EQUN)
[[35mlola[0m][W] CANCELED task # 57 (type EQUN)
[[35mlola[0m][I] LAUNCH task # 5 (type EXCL) for
[[35mlola[0m][I] time limit : 202 sec
[[35mlola[0m][I] memory limit: 2000 pages
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[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
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[[35mlola[0m][I] result : true
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[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA:
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[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 22
[[35mlola[0m][I] fired transitions : 22
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fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16 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.................................................................................................................... ============================== ======== inition.xml dict.xml ity.txt ity.xml ity.txt ity.xml template) text file) TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT most ([1m[36m--timelimit[0m) using default[0m odel.pnml[0m ) del.pnml[0m [0m) [4m[34mCTLFireability.xml[0m places removed CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m DISJ 0 0 0 0 2 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 EFEG 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m in use: 0 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m DISJ 0 0 0 0 2 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 EFEG 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m in use: 0 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m DISJ 0 0 0 0 2 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 EFEG 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m in use: 0 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m DISJ 0 0 0 0 2 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 EFEG 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m in use: 0 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m DISJ 0 0 0 0 2 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 EFEG 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m in use: 0 13 DLCflexbar-PT-3b-CTLFireability-2024-03 31 DLCflexbar-PT-3b-CTLFireability-2024-09 31 DLCflexbar-PT-3b-CTLFireability-2024-09 for DLCflexbar-PT-3b-CTLFireability-2024-03 31 DLCflexbar-PT-3b-CTLFireability-2024-09 for DLCflexbar-PT-3b-CTLFireability-2024-09 for DLCflexbar-PT-3b-CTLFireability-2024-09 (obsolete) for DLCflexbar-PT-3b-CTLFireability-2024-09 (obsolete) 0 DLCflexbar-PT-3b-CTLFireability-2024-00 DLCflexbar-PT-3b-CTLFireability-2024-00 for DLCflexbar-PT-3b-CTLFireability-2024-09 for DLCflexbar-PT-3b-CTLFireability-2024-09 CATEGORY VALUE PRODUCED BY[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m DISJ 0 0 0 0 3 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m in use: 1 0 DLCflexbar-PT-3b-CTLFireability-2024-00 DLCflexbar-PT-3b-CTLFireability-2024-00 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m in use: 1 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m in use: 1 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m in use: 1 16 DLCflexbar-PT-3b-CTLFireability-2024-04 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 1 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 0/2000 DLCflexbar-PT-3b-CTLFireability-2024-04 -- in use: 1 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 1 0 0 0 1 0 0 0 CTL 1 0 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 3/2000 DLCflexbar-PT-3b-CTLFireability-2024-04 73577 m, 14715 m/sec, 78932 t fired, . in use: 3 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 7/2000 DLCflexbar-PT-3b-CTLFireability-2024-04 207185 m, 26721 m/sec, 223711 t fired, . in use: 7 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 8/2000 DLCflexbar-PT-3b-CTLFireability-2024-04 341944 m, 26951 m/sec, 369929 t fired, . in use: 8 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 12/2000 DLCflexbar-PT-3b-CTLFireability-2024-04 476731 m, 26957 m/sec, 516243 t fired, . in use: 12 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 15/2000 DLCflexbar-PT-3b-CTLFireability-2024-04 611454 m, 26944 m/sec, 662042 t fired, . in use: 15 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 18/2000 DLCflexbar-PT-3b-CTLFireability-2024-04 745205 m, 26750 m/sec, 807299 t fired, . in use: 18 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 19/2000 DLCflexbar-PT-3b-CTLFireability-2024-04 874101 m, 25779 m/sec, 946565 t fired, . in use: 19 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 21/2000 DLCflexbar-PT-3b-CTLFireability-2024-04 1008922 m, 26964 m/sec, 1093347 t fired, . in use: 21 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 25/2000 DLCflexbar-PT-3b-CTLFireability-2024-04 1136175 m, 25450 m/sec, 1231428 t fired, . in use: 25 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 29/2000 DLCflexbar-PT-3b-CTLFireability-2024-04 1270924 m, 26949 m/sec, 1377016 t fired, . in use: 29 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 32/2000 DLCflexbar-PT-3b-CTLFireability-2024-04 1405387 m, 26892 m/sec, 1523482 t fired, . in use: 32 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 35/2000 DLCflexbar-PT-3b-CTLFireability-2024-04 1539376 m, 26797 m/sec, 1668749 t fired, . in use: 35 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 36/2000 DLCflexbar-PT-3b-CTLFireability-2024-04 1672709 m, 26666 m/sec, 1813170 t fired, . in use: 36 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 38/2000 DLCflexbar-PT-3b-CTLFireability-2024-04 1806363 m, 26730 m/sec, 1958470 t fired, . in use: 38 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 41/2000 DLCflexbar-PT-3b-CTLFireability-2024-04 1939436 m, 26614 m/sec, 2103092 t fired, . in use: 41 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 45/2000 DLCflexbar-PT-3b-CTLFireability-2024-04 2072380 m, 26588 m/sec, 2247471 t fired, . in use: 45 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 49/2000 DLCflexbar-PT-3b-CTLFireability-2024-04 2206030 m, 26730 m/sec, 2392740 t fired, . in use: 49 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 53/2000 DLCflexbar-PT-3b-CTLFireability-2024-04 2339159 m, 26625 m/sec, 2537322 t fired, . in use: 53 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 58/2000 DLCflexbar-PT-3b-CTLFireability-2024-04 2472703 m, 26708 m/sec, 2682294 t fired, . in use: 58 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 62/2000 DLCflexbar-PT-3b-CTLFireability-2024-04 2606542 m, 26767 m/sec, 2827473 t fired, . in use: 62 for DLCflexbar-PT-3b-CTLFireability-2024-04 49 DLCflexbar-PT-3b-CTLFireability-2023-15 for DLCflexbar-PT-3b-CTLFireability-2023-15 46 DLCflexbar-PT-3b-CTLFireability-2023-14 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 2/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 35485 m, 7097 m/sec, 38300 t fired, . in use: 64 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 7/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 135229 m, 19948 m/sec, 149467 t fired, . in use: 64 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 12/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 234793 m, 19912 m/sec, 260504 t fired, . in use: 64 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 17/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 333727 m, 19786 m/sec, 372267 t fired, . in use: 64 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 22/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 432594 m, 19773 m/sec, 483421 t fired, . in use: 64 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 27/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 531705 m, 19822 m/sec, 594024 t fired, . in use: 64 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 32/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 630466 m, 19752 m/sec, 703972 t fired, . in use: 64 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 37/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 730108 m, 19928 m/sec, 814391 t fired, . in use: 64 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 42/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 828974 m, 19773 m/sec, 926022 t fired, . in use: 64 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 47/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 928427 m, 19890 m/sec, 1036879 t fired, . in use: 64 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 52/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 1027097 m, 19734 m/sec, 1148181 t fired, . in use: 64 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 56/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 1125737 m, 19728 m/sec, 1258616 t fired, . in use: 64 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 62/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 1225677 m, 19988 m/sec, 1369501 t fired, . in use: 64 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 67/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 1325535 m, 19971 m/sec, 1481386 t fired, . in use: 67 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 72/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 1425280 m, 19949 m/sec, 1592981 t fired, . in use: 72 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 77/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 1525019 m, 19947 m/sec, 1704882 t fired, . in use: 77 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 82/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 1624201 m, 19836 m/sec, 1816688 t fired, . in use: 82 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 87/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 1723598 m, 19879 m/sec, 1927533 t fired, . in use: 87 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 91/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 1823102 m, 19900 m/sec, 2038166 t fired, . in use: 91 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 97/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 1922751 m, 19929 m/sec, 2149874 t fired, . in use: 97 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 101/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 2021581 m, 19766 m/sec, 2260725 t fired, . in use: 101 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 106/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 2120756 m, 19835 m/sec, 2372213 t fired, . in use: 106 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 111/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 2219472 m, 19743 m/sec, 2483140 t fired, . in use: 111 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 116/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 2319589 m, 20023 m/sec, 2594256 t fired, . in use: 116 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 121/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 2417318 m, 19545 m/sec, 2705071 t fired, . in use: 121 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 126/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 2514363 m, 19409 m/sec, 2812764 t fired, . in use: 126 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 131/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 2610743 m, 19276 m/sec, 2921454 t fired, . in use: 131 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 136/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 2707539 m, 19359 m/sec, 3029961 t fired, . in use: 136 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 141/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 2804338 m, 19359 m/sec, 3138581 t fired, . in use: 141 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 146/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 2901383 m, 19409 m/sec, 3246521 t fired, . in use: 146 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 150/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 2998617 m, 19446 m/sec, 3355165 t fired, . in use: 150 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 155/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 3094973 m, 19271 m/sec, 3464156 t fired, . in use: 155 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 160/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 3192429 m, 19491 m/sec, 3573002 t fired, . in use: 160 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 165/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 3288418 m, 19197 m/sec, 3682063 t fired, . in use: 165 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 170/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 3386107 m, 19537 m/sec, 3790147 t fired, . in use: 170 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 175/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 3483463 m, 19471 m/sec, 3898855 t fired, . in use: 175 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 180/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 3579893 m, 19286 m/sec, 4007423 t fired, . in use: 180 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 184/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 3676377 m, 19296 m/sec, 4116325 t fired, . in use: 184 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 189/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 3772686 m, 19261 m/sec, 4224627 t fired, . in use: 189 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 194/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 3869221 m, 19307 m/sec, 4332395 t fired, . in use: 194 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 199/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 3965207 m, 19197 m/sec, 4440018 t fired, . in use: 199 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 204/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 4061968 m, 19352 m/sec, 4547725 t fired, . in use: 204 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 209/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 4158032 m, 19212 m/sec, 4656308 t fired, . in use: 209 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 213/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 4254423 m, 19278 m/sec, 4764119 t fired, . in use: 213 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 218/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 4349898 m, 19095 m/sec, 4872319 t fired, . in use: 218 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 223/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 4445971 m, 19214 m/sec, 4980179 t fired, . in use: 223 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 228/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 4543107 m, 19427 m/sec, 5087562 t fired, . in use: 228 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 232/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 4638974 m, 19173 m/sec, 5196362 t fired, . in use: 232 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 237/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 4735127 m, 19230 m/sec, 5304894 t fired, . in use: 237 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 242/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 4831325 m, 19239 m/sec, 5413265 t fired, . in use: 242 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 247/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 4926917 m, 19118 m/sec, 5520900 t fired, . in use: 247 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 252/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 5023160 m, 19248 m/sec, 5627774 t fired, . in use: 252 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 257/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 5119249 m, 19217 m/sec, 5734998 t fired, . in use: 257 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 262/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 5214102 m, 18970 m/sec, 5841892 t fired, . in use: 262 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 266/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 5309102 m, 19000 m/sec, 5948049 t fired, . in use: 266 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 271/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 5403965 m, 18972 m/sec, 6055066 t fired, . in use: 271 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 276/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 5499177 m, 19042 m/sec, 6161812 t fired, . in use: 276 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 281/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 5593256 m, 18815 m/sec, 6269401 t fired, . in use: 281 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 286/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 5688418 m, 19032 m/sec, 6375983 t fired, . in use: 286 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 291/2000 DLCflexbar-PT-3b-CTLFireability-2023-14 5783583 m, 19033 m/sec, 6482878 t fired, . in use: 291 for DLCflexbar-PT-3b-CTLFireability-2023-14 (local timeout) CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 1 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m in use: 295 43 DLCflexbar-PT-3b-CTLFireability-2023-13 46 DLCflexbar-PT-3b-CTLFireability-2023-14 for DLCflexbar-PT-3b-CTLFireability-2023-13 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS[0m 4/5 DLCflexbar-PT-3b-CTLFireability-2023-14 84239 m, -1139868 m/sec, 91976 t fired, . in use: 299 for DLCflexbar-PT-3b-CTLFireability-2023-14 (memory limit exceeded) CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m in use: 300 40 DLCflexbar-PT-3b-CTLFireability-2023-12 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 5/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 173084 m, 34616 m/sec, 174922 t fired, . in use: 300 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 13/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 347178 m, 34818 m/sec, 349631 t fired, . in use: 308 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 20/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 512481 m, 33060 m/sec, 515696 t fired, . in use: 315 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 27/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 681903 m, 33884 m/sec, 685740 t fired, . in use: 322 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 34/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 858945 m, 35408 m/sec, 863443 t fired, . in use: 329 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 40/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 1034384 m, 35087 m/sec, 1041151 t fired, . in use: 335 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 45/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 1193921 m, 31907 m/sec, 1201736 t fired, . in use: 340 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 53/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 1360487 m, 33313 m/sec, 1370478 t fired, . in use: 348 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 58/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 1529565 m, 33815 m/sec, 1543466 t fired, . in use: 353 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 62/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 1703131 m, 34713 m/sec, 1721715 t fired, . in use: 357 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 65/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 1879636 m, 35301 m/sec, 1906005 t fired, . in use: 360 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 70/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 2053249 m, 34722 m/sec, 2084841 t fired, . in use: 365 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 75/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 2228535 m, 35057 m/sec, 2267023 t fired, . in use: 370 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 79/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 2402621 m, 34817 m/sec, 2447007 t fired, . in use: 374 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 83/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 2579797 m, 35435 m/sec, 2634606 t fired, . in use: 378 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 88/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 2756392 m, 35319 m/sec, 2820918 t fired, . in use: 383 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 92/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 2931806 m, 35082 m/sec, 3005426 t fired, . in use: 387 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 97/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 3109245 m, 35487 m/sec, 3194254 t fired, . in use: 392 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 101/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 3283284 m, 34807 m/sec, 3373824 t fired, . in use: 396 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 105/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 3455534 m, 34450 m/sec, 3550772 t fired, . in use: 400 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 112/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 3631060 m, 35105 m/sec, 3733592 t fired, . in use: 407 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 120/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 3808705 m, 35529 m/sec, 3920395 t fired, . in use: 415 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 128/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 3987664 m, 35791 m/sec, 4110095 t fired, . in use: 423 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 135/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 4163435 m, 35154 m/sec, 4291873 t fired, . in use: 430 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 143/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 4340842 m, 35481 m/sec, 4478446 t fired, . in use: 438 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 150/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 4516523 m, 35136 m/sec, 4661392 t fired, . in use: 445 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 156/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 4693832 m, 35461 m/sec, 4845006 t fired, . in use: 451 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 161/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 4867779 m, 34789 m/sec, 5023118 t fired, . in use: 456 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 168/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 5043684 m, 35181 m/sec, 5203637 t fired, . in use: 463 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 176/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 5219200 m, 35103 m/sec, 5386120 t fired, . in use: 471 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 184/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 5394076 m, 34975 m/sec, 5568798 t fired, . in use: 479 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 191/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 5568689 m, 34922 m/sec, 5748887 t fired, . in use: 486 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 199/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 5744865 m, 35235 m/sec, 5933392 t fired, . in use: 494 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 207/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 5918351 m, 34697 m/sec, 6114449 t fired, . in use: 502 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 214/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 6090502 m, 34430 m/sec, 6293416 t fired, . in use: 509 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 221/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 6262250 m, 34349 m/sec, 6471383 t fired, . in use: 516 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 228/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 6436567 m, 34863 m/sec, 6652090 t fired, . in use: 523 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 236/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 6611835 m, 35053 m/sec, 6834802 t fired, . in use: 531 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 244/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 6788180 m, 35269 m/sec, 7018679 t fired, . in use: 539 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 249/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 6964308 m, 35225 m/sec, 7200261 t fired, . in use: 544 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 254/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 7137865 m, 34711 m/sec, 7377975 t fired, . in use: 549 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 261/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 7312769 m, 34980 m/sec, 7557404 t fired, . in use: 556 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 270/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 7488530 m, 35152 m/sec, 7741624 t fired, . in use: 565 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 279/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 7666448 m, 35583 m/sec, 7929156 t fired, . in use: 574 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 287/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 7842048 m, 35120 m/sec, 8113413 t fired, . in use: 582 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 294/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 8015690 m, 34728 m/sec, 8292853 t fired, . in use: 589 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 303/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 8190640 m, 34990 m/sec, 8477360 t fired, . in use: 598 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 312/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 8366697 m, 35211 m/sec, 8663774 t fired, . in use: 607 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 320/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 8543045 m, 35269 m/sec, 8849377 t fired, . in use: 615 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 327/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 8717379 m, 34866 m/sec, 9029833 t fired, . in use: 622 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 334/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 8889853 m, 34494 m/sec, 9208124 t fired, . in use: 629 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 342/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 9065147 m, 35058 m/sec, 9391113 t fired, . in use: 637 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 350/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 9241246 m, 35219 m/sec, 9575488 t fired, . in use: 645 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 359/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 9415634 m, 34877 m/sec, 9760142 t fired, . in use: 654 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 368/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 9591399 m, 35153 m/sec, 9946251 t fired, . in use: 663 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 377/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 9769450 m, 35610 m/sec, 10134395 t fired, . in use: 672 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 385/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 9945272 m, 35164 m/sec, 10318782 t fired, . in use: 680 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 394/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 10122593 m, 35464 m/sec, 10506535 t fired, . in use: 689 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 403/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 10297497 m, 34980 m/sec, 10692144 t fired, . in use: 698 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 411/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 10472351 m, 34970 m/sec, 10877744 t fired, . in use: 706 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 420/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 10651297 m, 35789 m/sec, 11067833 t fired, . in use: 715 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 429/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 10829941 m, 35728 m/sec, 11256353 t fired, . in use: 724 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 436/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 11011047 m, 36221 m/sec, 11448131 t fired, . in use: 731 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 445/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 11191504 m, 36091 m/sec, 11639442 t fired, . in use: 740 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 454/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 11368589 m, 35417 m/sec, 11827468 t fired, . in use: 749 CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m 464/2000 DLCflexbar-PT-3b-CTLFireability-2023-12 11547648 m, 35811 m/sec, 12017632 t fired, . in use: 759 for DLCflexbar-PT-3b-CTLFireability-2023-12 (local timeout) CATEGORY VALUE PRODUCED BY[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL true CTL model checker[0m EFEG true state space /EFEG[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 1 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS[0m in use: 767 37 DLCflexbar-PT-3b-CTLFireability-2024-11 $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-3b"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is DLCflexbar-PT-3b, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r115-smll-171624276200026"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-3b.tgz
mv DLCflexbar-PT-3b execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;