MCC'2024- Execution of r071-tall-171620506900291

About the Execution of LoLA for CircadianClock-PT-000100

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
16208.075	262349.00	139538.00	2047.40	[undef]	Cannot compute

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r071-tall-171620506900291.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is CircadianClock-PT-000100, examination is LTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r071-tall-171620506900291
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 428K
-rw-r--r-- 1 mcc users 5.7K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 57K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.2K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 53K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.2K May 19 07:07 LTLCardinality.txt
-rw-r--r-- 1 mcc users 22K May 19 15:35 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Apr 22 14:32 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Apr 22 14:32 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.1K Apr 12 03:26 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 91K Apr 12 03:26 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 10K Apr 12 03:24 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 80K Apr 12 03:24 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 22 14:32 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Apr 22 14:32 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 7 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 11K May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME CircadianClock-PT-000100-LTLCardinality-00
FORMULA_NAME CircadianClock-PT-000100-LTLCardinality-01
FORMULA_NAME CircadianClock-PT-000100-LTLCardinality-02
FORMULA_NAME CircadianClock-PT-000100-LTLCardinality-03
FORMULA_NAME CircadianClock-PT-000100-LTLCardinality-04
FORMULA_NAME CircadianClock-PT-000100-LTLCardinality-05
FORMULA_NAME CircadianClock-PT-000100-LTLCardinality-06
FORMULA_NAME CircadianClock-PT-000100-LTLCardinality-07
FORMULA_NAME CircadianClock-PT-000100-LTLCardinality-08
FORMULA_NAME CircadianClock-PT-000100-LTLCardinality-09
FORMULA_NAME CircadianClock-PT-000100-LTLCardinality-10
FORMULA_NAME CircadianClock-PT-000100-LTLCardinality-11
FORMULA_NAME CircadianClock-PT-000100-LTLCardinality-12
FORMULA_NAME CircadianClock-PT-000100-LTLCardinality-13
FORMULA_NAME CircadianClock-PT-000100-LTLCardinality-14
FORMULA_NAME CircadianClock-PT-000100-LTLCardinality-15

=== Now, execution of the tool begins

BK_START 1717039616255

BK_STOP 1717039878604

--------------------
content from stderr:

[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLCardinality.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 21 (type CNST) for 18 CircadianClock-PT-000100-LTLCardinality-06
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 21 (type CNST) for CircadianClock-PT-000100-LTLCardinality-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 36 (type EXCL) for 35 CircadianClock-PT-000100-LTLCardinality-09
[[35mlola[0m][I] time limit : 171 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 36 (type EXCL) for CircadianClock-PT-000100-LTLCardinality-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 102
[[35mlola[0m][I] fired transitions : 102
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 33 (type EXCL) for 32 CircadianClock-PT-000100-LTLCardinality-08
[[35mlola[0m][I] time limit : 180 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 33 (type EXCL) for CircadianClock-PT-000100-LTLCardinality-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 102
[[35mlola[0m][I] fired transitions : 102
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 39 (type CNST) for 38 CircadianClock-PT-000100-LTLCardinality-10
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 25 (type EXCL) for 18 CircadianClock-PT-000100-LTLCardinality-06
[[35mlola[0m][I] time limit : 240 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 25 (type EXCL) for CircadianClock-PT-000100-LTLCardinality-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 3
[[35mlola[0m][I] fired transitions : 2
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] FINISHED task # 39 (type CNST) for CircadianClock-PT-000100-LTLCardinality-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 51 (type EXCL) for 50 CircadianClock-PT-000100-LTLCardinality-14
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 51 (type EXCL) for CircadianClock-PT-000100-LTLCardinality-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 102
[[35mlola[0m][I] fired transitions : 102
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 54 (type EXCL) for 53 CircadianClock-PT-000100-LTLCardinality-15
[[35mlola[0m][I] time limit : 300 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-06: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 5/300 25/2000 CircadianClock-PT-000100-LTLCardinality-15 3790891 m, 758178 m/sec, 6658347 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 25
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-06: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 10/300 48/2000 CircadianClock-PT-000100-LTLCardinality-15 7341133 m, 710048 m/sec, 13288000 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 48
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-06: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 15/300 69/2000 CircadianClock-PT-000100-LTLCardinality-15 10572276 m, 646228 m/sec, 19536762 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 69
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-06: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 20/300 90/2000 CircadianClock-PT-000100-LTLCardinality-15 13817899 m, 649124 m/sec, 25846345 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 90
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-06: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 25/300 111/2000 CircadianClock-PT-000100-LTLCardinality-15 17001018 m, 636623 m/sec, 32020523 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 111
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-06: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 30/300 132/2000 CircadianClock-PT-000100-LTLCardinality-15 20246178 m, 649032 m/sec, 38279360 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 132
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-06: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 35/300 152/2000 CircadianClock-PT-000100-LTLCardinality-15 23340557 m, 618875 m/sec, 44463503 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 152
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-06: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 40/300 172/2000 CircadianClock-PT-000100-LTLCardinality-15 26511066 m, 634101 m/sec, 50717237 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 172
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-06: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 45/300 193/2000 CircadianClock-PT-000100-LTLCardinality-15 29638363 m, 625459 m/sec, 56983489 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 193
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-06: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 50/300 213/2000 CircadianClock-PT-000100-LTLCardinality-15 32758786 m, 624084 m/sec, 63164285 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 213
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-06: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 55/300 233/2000 CircadianClock-PT-000100-LTLCardinality-15 35853646 m, 618972 m/sec, 69356609 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 233
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-06: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 60/300 253/2000 CircadianClock-PT-000100-LTLCardinality-15 38970941 m, 623459 m/sec, 75559667 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 253
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-06: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 65/300 273/2000 CircadianClock-PT-000100-LTLCardinality-15 42048984 m, 615608 m/sec, 81722440 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 273
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-06: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 70/300 293/2000 CircadianClock-PT-000100-LTLCardinality-15 45143887 m, 618980 m/sec, 87843328 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 293
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-06: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 75/300 313/2000 CircadianClock-PT-000100-LTLCardinality-15 48112165 m, 593655 m/sec, 93863688 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 313
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-06: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 80/300 332/2000 CircadianClock-PT-000100-LTLCardinality-15 51145816 m, 606730 m/sec, 100001687 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 332
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-06: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 85/300 352/2000 CircadianClock-PT-000100-LTLCardinality-15 54218406 m, 614518 m/sec, 106227077 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 352
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-06: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 90/300 372/2000 CircadianClock-PT-000100-LTLCardinality-15 57303904 m, 617099 m/sec, 112397451 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 372
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-06: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 95/300 392/2000 CircadianClock-PT-000100-LTLCardinality-15 60323365 m, 603892 m/sec, 118507650 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 392
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-06: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 100/300 412/2000 CircadianClock-PT-000100-LTLCardinality-15 63397704 m, 614867 m/sec, 124637331 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 412
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-06: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 105/300 432/2000 CircadianClock-PT-000100-LTLCardinality-15 66493024 m, 619064 m/sec, 130763572 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-06: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 110/300 452/2000 CircadianClock-PT-000100-LTLCardinality-15 69547624 m, 610920 m/sec, 136917485 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 452
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-06: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 115/300 471/2000 CircadianClock-PT-000100-LTLCardinality-15 72608832 m, 612241 m/sec, 143100197 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 471
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-06: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 120/300 491/2000 CircadianClock-PT-000100-LTLCardinality-15 75624713 m, 603176 m/sec, 149244888 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 491
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-06: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 134/300 508/2000 CircadianClock-PT-000100-LTLCardinality-15 78265148 m, 528087 m/sec, 154584370 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 136 secs. Pages in use: 508
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-06: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 150/300 508/2000 CircadianClock-PT-000100-LTLCardinality-15 78265381 m, 46 m/sec, 154584879 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 508
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-06: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 165/300 508/2000 CircadianClock-PT-000100-LTLCardinality-15 78265661 m, 56 m/sec, 154585395 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 166 secs. Pages in use: 508
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-06: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 187/300 508/2000 CircadianClock-PT-000100-LTLCardinality-15 78266107 m, 89 m/sec, 154586312 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 188 secs. Pages in use: 508
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-06: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 211/300 508/2000 CircadianClock-PT-000100-LTLCardinality-15 78271199 m, 1018 m/sec, 154596680 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 212 secs. Pages in use: 508
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mCircadianClock-PT-000100-LTLCardinality-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-06: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CircadianClock-PT-000100-LTLCardinality-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 237/300 508/2000 CircadianClock-PT-000100-LTLCardinality-15 78271470 m, 54 m/sec, 154597247 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 238 secs. Pages in use: 508
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 406 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="CircadianClock-PT-000100"
export BK_EXAMINATION="LTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is CircadianClock-PT-000100, examination is LTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r071-tall-171620506900291"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/CircadianClock-PT-000100.tgz
mv CircadianClock-PT-000100 execution
cd execution
if [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "UpperBounds" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] || [ "LTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;