About the Execution of LoLA for CANInsertWithFailure-PT-050
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 10242.147 | 809738.00 | 1796436.00 | 2056.80 | FFFFTFT?FFF?FTTF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r071-tall-171620506600132.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is CANInsertWithFailure-PT-050, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r071-tall-171620506600132
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 16M
-rw-r--r-- 1 mcc users 9.5K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 84K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.4K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 44K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.8K May 19 07:07 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K May 19 15:33 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.1K Apr 22 14:32 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Apr 22 14:32 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K May 14 13:22 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 84K May 14 13:22 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K May 14 13:22 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 69K May 14 13:22 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K May 19 07:10 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K May 19 15:24 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 4 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 16M May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME CANInsertWithFailure-PT-050-LTLFireability-00
FORMULA_NAME CANInsertWithFailure-PT-050-LTLFireability-01
FORMULA_NAME CANInsertWithFailure-PT-050-LTLFireability-02
FORMULA_NAME CANInsertWithFailure-PT-050-LTLFireability-03
FORMULA_NAME CANInsertWithFailure-PT-050-LTLFireability-04
FORMULA_NAME CANInsertWithFailure-PT-050-LTLFireability-05
FORMULA_NAME CANInsertWithFailure-PT-050-LTLFireability-06
FORMULA_NAME CANInsertWithFailure-PT-050-LTLFireability-07
FORMULA_NAME CANInsertWithFailure-PT-050-LTLFireability-08
FORMULA_NAME CANInsertWithFailure-PT-050-LTLFireability-09
FORMULA_NAME CANInsertWithFailure-PT-050-LTLFireability-10
FORMULA_NAME CANInsertWithFailure-PT-050-LTLFireability-11
FORMULA_NAME CANInsertWithFailure-PT-050-LTLFireability-12
FORMULA_NAME CANInsertWithFailure-PT-050-LTLFireability-13
FORMULA_NAME CANInsertWithFailure-PT-050-LTLFireability-14
FORMULA_NAME CANInsertWithFailure-PT-050-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717022364295
FORMULA CANInsertWithFailure-PT-050-LTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CANInsertWithFailure-PT-050-LTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CANInsertWithFailure-PT-050-LTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CANInsertWithFailure-PT-050-LTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CANInsertWithFailure-PT-050-LTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CANInsertWithFailure-PT-050-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CANInsertWithFailure-PT-050-LTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CANInsertWithFailure-PT-050-LTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CANInsertWithFailure-PT-050-LTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CANInsertWithFailure-PT-050-LTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CANInsertWithFailure-PT-050-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CANInsertWithFailure-PT-050-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CANInsertWithFailure-PT-050-LTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CANInsertWithFailure-PT-050-LTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-04: LTL true LTL model checker[0m
[[35mlola[0m] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m] [1m[33mCANInsertWithFailure-PT-050-LTLFireability-07: LTL unknown AGGR[0m
[[35mlola[0m] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m] [1m[33mCANInsertWithFailure-PT-050-LTLFireability-11: LTL unknown AGGR[0m
[[35mlola[0m] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 809 secs. Pages in use: 279
BK_STOP 1717023174033
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 58 (type SKEL/FNDP) for 44 CANInsertWithFailure-PT-050-LTLFireability-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 59 (type SKEL/EQUN) for 44 CANInsertWithFailure-PT-050-LTLFireability-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 60 (type SKEL/SRCH) for 44 CANInsertWithFailure-PT-050-LTLFireability-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 58 (type SKEL/FNDP) for CANInsertWithFailure-PT-050-LTLFireability-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 59 (type EQUN) for CANInsertWithFailure-PT-050-LTLFireability-12 (obsolete)
[[35mlola[0m][W] CANCELED task # 60 (type SRCH) for CANInsertWithFailure-PT-050-LTLFireability-12 (obsolete)
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-12: AG 0 0 0 0 1 0 0 2
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-15: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 44 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-12: AG 0 0 0 0 1 0 0 2
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-15: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 49 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-12: AG 0 0 0 0 1 0 0 2
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-15: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 54 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-12: AG 0 0 0 0 1 0 0 2
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-15: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 59 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-12: AG 0 0 0 0 1 0 0 2
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-15: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 64 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-12: AG 0 0 0 0 1 0 0 2
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-15: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 69 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-12: AG 0 0 0 0 1 0 0 2
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-15: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 74 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-12: AG 0 0 0 0 1 0 0 2
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-15: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 79 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-12: AG 0 0 0 0 1 0 0 2
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-15: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 84 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-12: AG 0 0 0 0 1 0 0 2
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-15: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 89 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 39 (type EXCL) for 38 CANInsertWithFailure-PT-050-LTLFireability-10
[[35mlola[0m][I] time limit : 194 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 39 (type EXCL) for CANInsertWithFailure-PT-050-LTLFireability-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 65
[[35mlola[0m][I] fired transitions : 67
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-12: AG 0 0 0 0 1 0 0 2
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-15: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 94 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 62 (type EXCL) for 53 CANInsertWithFailure-PT-050-LTLFireability-15
[[35mlola[0m][I] time limit : 206 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 65 (type EQUN) for 53 CANInsertWithFailure-PT-050-LTLFireability-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-12: AG 0 0 0 0 1 0 0 2
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-15: F 0 0 2 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 EG EXCL 5/206 0/2000 CANInsertWithFailure-PT-050-LTLFireability-15 --
[[35mlola[0m][.] 65 EF STEQ 5/3506 0/5 CANInsertWithFailure-PT-050-LTLFireability-15 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 99 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-12: AG 0 0 0 0 1 0 0 2
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-15: F 0 0 2 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 EG EXCL 10/206 0/2000 CANInsertWithFailure-PT-050-LTLFireability-15 --
[[35mlola[0m][.] 65 EF STEQ 10/3506 0/5 CANInsertWithFailure-PT-050-LTLFireability-15 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 104 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 62 (type EXCL) for CANInsertWithFailure-PT-050-LTLFireability-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 59
[[35mlola[0m][I] fired transitions : 59
[[35mlola[0m][I] time used : 11
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 65 (type EQUN) for CANInsertWithFailure-PT-050-LTLFireability-15 (obsolete)
[[35mlola[0m][I] LAUNCH task # 16 (type EXCL) for 15 CANInsertWithFailure-PT-050-LTLFireability-05
[[35mlola[0m][I] time limit : 218 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 16 (type EXCL) for CANInsertWithFailure-PT-050-LTLFireability-05
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 60
[[35mlola[0m][I] fired transitions : 61
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 69 (type EXCL) for 44 CANInsertWithFailure-PT-050-LTLFireability-12
[[35mlola[0m][I] time limit : 232 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 67 (type FNDP) for 44 CANInsertWithFailure-PT-050-LTLFireability-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 68 (type EQUN) for 44 CANInsertWithFailure-PT-050-LTLFireability-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-12: AG 0 0 3 0 1 0 0 2
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 67 EF FNDP 2/3493 0/5 CANInsertWithFailure-PT-050-LTLFireability-12 --
[[35mlola[0m][.] 68 EF STEQ 2/3493 0/5 CANInsertWithFailure-PT-050-LTLFireability-12 sara not yet started (preprocessing).
[[35mlola[0m][.] 69 EF EXCL 2/232 1/2000 CANInsertWithFailure-PT-050-LTLFireability-12 --
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 109 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 65 (type EQUN) for CANInsertWithFailure-PT-050-LTLFireability-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 74 (type EQUN) for 47 CANInsertWithFailure-PT-050-LTLFireability-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 69 (type EXCL) for CANInsertWithFailure-PT-050-LTLFireability-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 5
[[35mlola[0m][I] fired transitions : 4
[[35mlola[0m][I] time used : 6
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 67 (type FNDP) for CANInsertWithFailure-PT-050-LTLFireability-12 (obsolete)
[[35mlola[0m][W] CANCELED task # 68 (type EQUN) for CANInsertWithFailure-PT-050-LTLFireability-12 (obsolete)
[[35mlola[0m][I] LAUNCH task # 51 (type EXCL) for 50 CANInsertWithFailure-PT-050-LTLFireability-14
[[35mlola[0m][I] time limit : 249 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 51 (type EXCL) for CANInsertWithFailure-PT-050-LTLFireability-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 51
[[35mlola[0m][I] fired transitions : 50
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 42 (type EXCL) for 41 CANInsertWithFailure-PT-050-LTLFireability-11
[[35mlola[0m][I] time limit : 268 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 1/268 1/2000 CANInsertWithFailure-PT-050-LTLFireability-11 3958 m, 791 m/sec, 5887 t fired, .
[[35mlola[0m][.] 74 EF STEQ 1/3487 0/5 CANInsertWithFailure-PT-050-LTLFireability-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 114 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 67 (type FNDP) for CANInsertWithFailure-PT-050-LTLFireability-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 7
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] FINISHED task # 74 (type EQUN) for CANInsertWithFailure-PT-050-LTLFireability-13
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 6/268 5/2000 CANInsertWithFailure-PT-050-LTLFireability-11 68941 m, 12996 m/sec, 137542 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 119 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 11/268 7/2000 CANInsertWithFailure-PT-050-LTLFireability-11 124290 m, 11069 m/sec, 311502 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 124 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 59 (type SKEL/EQUN) for CANInsertWithFailure-PT-050-LTLFireability-12
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 16/268 9/2000 CANInsertWithFailure-PT-050-LTLFireability-11 165497 m, 8241 m/sec, 490419 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 129 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 21/268 10/2000 CANInsertWithFailure-PT-050-LTLFireability-11 195396 m, 5979 m/sec, 672275 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 134 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 26/268 12/2000 CANInsertWithFailure-PT-050-LTLFireability-11 231716 m, 7264 m/sec, 851884 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 139 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 31/268 14/2000 CANInsertWithFailure-PT-050-LTLFireability-11 270495 m, 7755 m/sec, 1029987 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 144 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 36/268 15/2000 CANInsertWithFailure-PT-050-LTLFireability-11 299420 m, 5785 m/sec, 1210891 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 149 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 41/268 16/2000 CANInsertWithFailure-PT-050-LTLFireability-11 338281 m, 7772 m/sec, 1387906 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 154 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 46/268 18/2000 CANInsertWithFailure-PT-050-LTLFireability-11 367213 m, 5786 m/sec, 1567645 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 159 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 51/268 19/2000 CANInsertWithFailure-PT-050-LTLFireability-11 396777 m, 5912 m/sec, 1746971 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 164 secs. Pages in use: 19
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 56/268 20/2000 CANInsertWithFailure-PT-050-LTLFireability-11 438611 m, 8366 m/sec, 1922481 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 169 secs. Pages in use: 20
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 61/268 22/2000 CANInsertWithFailure-PT-050-LTLFireability-11 470337 m, 6345 m/sec, 2100425 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 174 secs. Pages in use: 22
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 66/268 22/2000 CANInsertWithFailure-PT-050-LTLFireability-11 491113 m, 4155 m/sec, 2281409 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 179 secs. Pages in use: 22
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 71/268 23/2000 CANInsertWithFailure-PT-050-LTLFireability-11 512242 m, 4225 m/sec, 2464999 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 184 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 76/268 25/2000 CANInsertWithFailure-PT-050-LTLFireability-11 550429 m, 7637 m/sec, 2645671 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 189 secs. Pages in use: 25
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 81/268 27/2000 CANInsertWithFailure-PT-050-LTLFireability-11 584486 m, 6811 m/sec, 2828830 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 194 secs. Pages in use: 27
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 86/268 28/2000 CANInsertWithFailure-PT-050-LTLFireability-11 620218 m, 7146 m/sec, 3011202 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 199 secs. Pages in use: 28
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 91/268 30/2000 CANInsertWithFailure-PT-050-LTLFireability-11 656403 m, 7237 m/sec, 3192362 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 204 secs. Pages in use: 30
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 96/268 31/2000 CANInsertWithFailure-PT-050-LTLFireability-11 676326 m, 3984 m/sec, 3377738 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 209 secs. Pages in use: 31
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 101/268 32/2000 CANInsertWithFailure-PT-050-LTLFireability-11 710669 m, 6868 m/sec, 3559459 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 214 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 106/268 33/2000 CANInsertWithFailure-PT-050-LTLFireability-11 739458 m, 5757 m/sec, 3742715 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 219 secs. Pages in use: 33
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 111/268 35/2000 CANInsertWithFailure-PT-050-LTLFireability-11 771094 m, 6327 m/sec, 3926069 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 224 secs. Pages in use: 35
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 116/268 36/2000 CANInsertWithFailure-PT-050-LTLFireability-11 808200 m, 7421 m/sec, 4107983 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 229 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 121/268 38/2000 CANInsertWithFailure-PT-050-LTLFireability-11 844708 m, 7301 m/sec, 4288826 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 234 secs. Pages in use: 38
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 126/268 39/2000 CANInsertWithFailure-PT-050-LTLFireability-11 864715 m, 4001 m/sec, 4472395 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 239 secs. Pages in use: 39
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 131/268 40/2000 CANInsertWithFailure-PT-050-LTLFireability-11 898407 m, 6738 m/sec, 4654180 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 244 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 136/268 41/2000 CANInsertWithFailure-PT-050-LTLFireability-11 927732 m, 5865 m/sec, 4837049 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 249 secs. Pages in use: 41
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 141/268 43/2000 CANInsertWithFailure-PT-050-LTLFireability-11 958262 m, 6106 m/sec, 5020006 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 254 secs. Pages in use: 43
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 146/268 44/2000 CANInsertWithFailure-PT-050-LTLFireability-11 995410 m, 7429 m/sec, 5201411 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 259 secs. Pages in use: 44
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 151/268 45/2000 CANInsertWithFailure-PT-050-LTLFireability-11 1015551 m, 4028 m/sec, 5386475 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 264 secs. Pages in use: 45
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 156/268 46/2000 CANInsertWithFailure-PT-050-LTLFireability-11 1047738 m, 6437 m/sec, 5567862 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 269 secs. Pages in use: 46
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 161/268 47/2000 CANInsertWithFailure-PT-050-LTLFireability-11 1077176 m, 5887 m/sec, 5750250 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 274 secs. Pages in use: 47
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 166/268 48/2000 CANInsertWithFailure-PT-050-LTLFireability-11 1104927 m, 5550 m/sec, 5933242 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 279 secs. Pages in use: 48
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 171/268 50/2000 CANInsertWithFailure-PT-050-LTLFireability-11 1141962 m, 7407 m/sec, 6113581 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 284 secs. Pages in use: 50
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 176/268 51/2000 CANInsertWithFailure-PT-050-LTLFireability-11 1161293 m, 3866 m/sec, 6298631 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 289 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 181/268 52/2000 CANInsertWithFailure-PT-050-LTLFireability-11 1190552 m, 5851 m/sec, 6481381 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 294 secs. Pages in use: 52
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 186/268 53/2000 CANInsertWithFailure-PT-050-LTLFireability-11 1224524 m, 6794 m/sec, 6661910 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 299 secs. Pages in use: 53
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 191/268 54/2000 CANInsertWithFailure-PT-050-LTLFireability-11 1256946 m, 6484 m/sec, 6843116 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 304 secs. Pages in use: 54
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 196/268 55/2000 CANInsertWithFailure-PT-050-LTLFireability-11 1288220 m, 6254 m/sec, 7024178 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 309 secs. Pages in use: 55
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 201/268 56/2000 CANInsertWithFailure-PT-050-LTLFireability-11 1310626 m, 4481 m/sec, 7207902 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 314 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 206/268 58/2000 CANInsertWithFailure-PT-050-LTLFireability-11 1342809 m, 6436 m/sec, 7388981 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 319 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 211/268 59/2000 CANInsertWithFailure-PT-050-LTLFireability-11 1379370 m, 7312 m/sec, 7567840 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 324 secs. Pages in use: 59
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 216/268 60/2000 CANInsertWithFailure-PT-050-LTLFireability-11 1417361 m, 7598 m/sec, 7745399 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 329 secs. Pages in use: 60
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 221/268 61/2000 CANInsertWithFailure-PT-050-LTLFireability-11 1448563 m, 6240 m/sec, 7924361 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 334 secs. Pages in use: 61
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 226/268 62/2000 CANInsertWithFailure-PT-050-LTLFireability-11 1473472 m, 4981 m/sec, 8105670 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 339 secs. Pages in use: 62
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 231/268 63/2000 CANInsertWithFailure-PT-050-LTLFireability-11 1481586 m, 1622 m/sec, 8291666 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 344 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 236/268 63/2000 CANInsertWithFailure-PT-050-LTLFireability-11 1482026 m, 88 m/sec, 8479512 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 349 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 241/268 63/2000 CANInsertWithFailure-PT-050-LTLFireability-11 1482191 m, 33 m/sec, 8668241 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 354 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 246/268 64/2000 CANInsertWithFailure-PT-050-LTLFireability-11 1511249 m, 5811 m/sec, 8851241 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 359 secs. Pages in use: 64
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 251/268 66/2000 CANInsertWithFailure-PT-050-LTLFireability-11 1545375 m, 6825 m/sec, 9033192 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 364 secs. Pages in use: 66
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 256/268 67/2000 CANInsertWithFailure-PT-050-LTLFireability-11 1571644 m, 5253 m/sec, 9215826 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 369 secs. Pages in use: 67
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 261/268 68/2000 CANInsertWithFailure-PT-050-LTLFireability-11 1601378 m, 5946 m/sec, 9397486 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 374 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 266/268 69/2000 CANInsertWithFailure-PT-050-LTLFireability-11 1633362 m, 6396 m/sec, 9579891 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 379 secs. Pages in use: 69
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 42 (type EXCL) for CANInsertWithFailure-PT-050-LTLFireability-11 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 384 secs. Pages in use: 70
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 36 (type EXCL) for 35 CANInsertWithFailure-PT-050-LTLFireability-09
[[35mlola[0m][I] time limit : 268 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 42 (type EXCL) for 41 CANInsertWithFailure-PT-050-LTLFireability-11
[[35mlola[0m][I] time limit : 3216 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 36 (type EXCL) for CANInsertWithFailure-PT-050-LTLFireability-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 87
[[35mlola[0m][I] fired transitions : 88
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 42 LTL EXCL 5/268 5/5 CANInsertWithFailure-PT-050-LTLFireability-11 82035 m, -310265 m/sec, 160174 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 389 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 42 (type EXCL) for CANInsertWithFailure-PT-050-LTLFireability-11 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-08: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 394 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 33 (type EXCL) for 24 CANInsertWithFailure-PT-050-LTLFireability-08
[[35mlola[0m][I] time limit : 291 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 33 (type EXCL) for CANInsertWithFailure-PT-050-LTLFireability-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 78
[[35mlola[0m][I] fired transitions : 78
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 22 (type EXCL) for 21 CANInsertWithFailure-PT-050-LTLFireability-07
[[35mlola[0m][I] time limit : 400 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 5/400 5/2000 CANInsertWithFailure-PT-050-LTLFireability-07 85390 m, 17078 m/sec, 166090 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 399 secs. Pages in use: 79
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 10/400 8/2000 CANInsertWithFailure-PT-050-LTLFireability-07 132373 m, 9396 m/sec, 345585 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 404 secs. Pages in use: 83
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 15/400 10/2000 CANInsertWithFailure-PT-050-LTLFireability-07 172748 m, 8075 m/sec, 526192 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 409 secs. Pages in use: 86
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 20/400 11/2000 CANInsertWithFailure-PT-050-LTLFireability-07 203392 m, 6128 m/sec, 709036 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 414 secs. Pages in use: 88
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 25/400 12/2000 CANInsertWithFailure-PT-050-LTLFireability-07 240658 m, 7453 m/sec, 890336 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 419 secs. Pages in use: 90
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 30/400 14/2000 CANInsertWithFailure-PT-050-LTLFireability-07 272766 m, 6421 m/sec, 1072772 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 424 secs. Pages in use: 93
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 35/400 15/2000 CANInsertWithFailure-PT-050-LTLFireability-07 308359 m, 7118 m/sec, 1253687 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 429 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 40/400 17/2000 CANInsertWithFailure-PT-050-LTLFireability-07 343607 m, 7049 m/sec, 1434552 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 434 secs. Pages in use: 99
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 45/400 18/2000 CANInsertWithFailure-PT-050-LTLFireability-07 376157 m, 6510 m/sec, 1616163 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 439 secs. Pages in use: 101
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 50/400 19/2000 CANInsertWithFailure-PT-050-LTLFireability-07 405360 m, 5840 m/sec, 1798216 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 444 secs. Pages in use: 104
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 55/400 21/2000 CANInsertWithFailure-PT-050-LTLFireability-07 444865 m, 7901 m/sec, 1976752 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 449 secs. Pages in use: 107
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 60/400 22/2000 CANInsertWithFailure-PT-050-LTLFireability-07 482482 m, 7523 m/sec, 2155003 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 454 secs. Pages in use: 109
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 65/400 22/2000 CANInsertWithFailure-PT-050-LTLFireability-07 491194 m, 1742 m/sec, 2341955 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 459 secs. Pages in use: 111
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 70/400 24/2000 CANInsertWithFailure-PT-050-LTLFireability-07 524505 m, 6662 m/sec, 2524283 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 464 secs. Pages in use: 115
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 75/400 25/2000 CANInsertWithFailure-PT-050-LTLFireability-07 557465 m, 6592 m/sec, 2706598 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 469 secs. Pages in use: 116
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 80/400 27/2000 CANInsertWithFailure-PT-050-LTLFireability-07 594754 m, 7457 m/sec, 2887624 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 474 secs. Pages in use: 119
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 85/400 29/2000 CANInsertWithFailure-PT-050-LTLFireability-07 631420 m, 7333 m/sec, 3068596 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 479 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 68 (type EQUN) for CANInsertWithFailure-PT-050-LTLFireability-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 90/400 30/2000 CANInsertWithFailure-PT-050-LTLFireability-07 663893 m, 6494 m/sec, 3250563 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 484 secs. Pages in use: 125
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 95/400 31/2000 CANInsertWithFailure-PT-050-LTLFireability-07 687103 m, 4642 m/sec, 3436195 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 489 secs. Pages in use: 127
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 100/400 32/2000 CANInsertWithFailure-PT-050-LTLFireability-07 720959 m, 6771 m/sec, 3618005 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 494 secs. Pages in use: 130
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 105/400 34/2000 CANInsertWithFailure-PT-050-LTLFireability-07 752622 m, 6332 m/sec, 3801216 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 499 secs. Pages in use: 134
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 110/400 35/2000 CANInsertWithFailure-PT-050-LTLFireability-07 783612 m, 6198 m/sec, 3985211 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 504 secs. Pages in use: 136
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 115/400 37/2000 CANInsertWithFailure-PT-050-LTLFireability-07 819710 m, 7219 m/sec, 4167670 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 509 secs. Pages in use: 140
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 120/400 38/2000 CANInsertWithFailure-PT-050-LTLFireability-07 855383 m, 7134 m/sec, 4348698 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 514 secs. Pages in use: 142
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 125/400 39/2000 CANInsertWithFailure-PT-050-LTLFireability-07 876266 m, 4176 m/sec, 4534324 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 519 secs. Pages in use: 145
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 130/400 41/2000 CANInsertWithFailure-PT-050-LTLFireability-07 906270 m, 6000 m/sec, 4717843 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 524 secs. Pages in use: 148
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 135/400 42/2000 CANInsertWithFailure-PT-050-LTLFireability-07 939317 m, 6609 m/sec, 4900344 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 529 secs. Pages in use: 150
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 140/400 43/2000 CANInsertWithFailure-PT-050-LTLFireability-07 972439 m, 6624 m/sec, 5083621 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 534 secs. Pages in use: 152
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 145/400 44/2000 CANInsertWithFailure-PT-050-LTLFireability-07 1007007 m, 6913 m/sec, 5265506 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 539 secs. Pages in use: 154
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 150/400 45/2000 CANInsertWithFailure-PT-050-LTLFireability-07 1027183 m, 4035 m/sec, 5451141 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 544 secs. Pages in use: 156
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 155/400 46/2000 CANInsertWithFailure-PT-050-LTLFireability-07 1054387 m, 5440 m/sec, 5634865 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 549 secs. Pages in use: 159
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 160/400 48/2000 CANInsertWithFailure-PT-050-LTLFireability-07 1086839 m, 6490 m/sec, 5817763 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 554 secs. Pages in use: 162
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 165/400 49/2000 CANInsertWithFailure-PT-050-LTLFireability-07 1117290 m, 6090 m/sec, 6000929 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 559 secs. Pages in use: 164
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 170/400 50/2000 CANInsertWithFailure-PT-050-LTLFireability-07 1153224 m, 7186 m/sec, 6181444 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 564 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 175/400 51/2000 CANInsertWithFailure-PT-050-LTLFireability-07 1175226 m, 4400 m/sec, 6366773 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 569 secs. Pages in use: 168
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 180/400 52/2000 CANInsertWithFailure-PT-050-LTLFireability-07 1202084 m, 5371 m/sec, 6550692 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 574 secs. Pages in use: 171
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 185/400 54/2000 CANInsertWithFailure-PT-050-LTLFireability-07 1235155 m, 6614 m/sec, 6732815 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 579 secs. Pages in use: 174
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 190/400 55/2000 CANInsertWithFailure-PT-050-LTLFireability-07 1270190 m, 7007 m/sec, 6914231 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 584 secs. Pages in use: 177
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 195/400 56/2000 CANInsertWithFailure-PT-050-LTLFireability-07 1302726 m, 6507 m/sec, 7097381 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 589 secs. Pages in use: 179
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 200/400 57/2000 CANInsertWithFailure-PT-050-LTLFireability-07 1323757 m, 4206 m/sec, 7282538 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 594 secs. Pages in use: 181
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 205/400 58/2000 CANInsertWithFailure-PT-050-LTLFireability-07 1360808 m, 7410 m/sec, 7462811 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 599 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 210/400 60/2000 CANInsertWithFailure-PT-050-LTLFireability-07 1396386 m, 7115 m/sec, 7642190 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 604 secs. Pages in use: 184
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 215/400 61/2000 CANInsertWithFailure-PT-050-LTLFireability-07 1431193 m, 6961 m/sec, 7821528 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 609 secs. Pages in use: 185
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 220/400 62/2000 CANInsertWithFailure-PT-050-LTLFireability-07 1460606 m, 5882 m/sec, 8006622 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 614 secs. Pages in use: 187
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 225/400 63/2000 CANInsertWithFailure-PT-050-LTLFireability-07 1481129 m, 4104 m/sec, 8195606 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 619 secs. Pages in use: 190
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 230/400 63/2000 CANInsertWithFailure-PT-050-LTLFireability-07 1481882 m, 150 m/sec, 8388964 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 624 secs. Pages in use: 191
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 235/400 63/2000 CANInsertWithFailure-PT-050-LTLFireability-07 1482149 m, 53 m/sec, 8582892 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 629 secs. Pages in use: 192
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 240/400 63/2000 CANInsertWithFailure-PT-050-LTLFireability-07 1498490 m, 3268 m/sec, 8774248 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 634 secs. Pages in use: 193
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 245/400 65/2000 CANInsertWithFailure-PT-050-LTLFireability-07 1532370 m, 6776 m/sec, 8960851 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 639 secs. Pages in use: 196
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 250/400 67/2000 CANInsertWithFailure-PT-050-LTLFireability-07 1566573 m, 6840 m/sec, 9146793 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 644 secs. Pages in use: 199
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 255/400 68/2000 CANInsertWithFailure-PT-050-LTLFireability-07 1592789 m, 5243 m/sec, 9333675 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 649 secs. Pages in use: 201
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 260/400 69/2000 CANInsertWithFailure-PT-050-LTLFireability-07 1622449 m, 5932 m/sec, 9520280 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 654 secs. Pages in use: 203
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 265/400 70/2000 CANInsertWithFailure-PT-050-LTLFireability-07 1657483 m, 7006 m/sec, 9704144 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 659 secs. Pages in use: 205
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 270/400 71/2000 CANInsertWithFailure-PT-050-LTLFireability-07 1682420 m, 4987 m/sec, 9891010 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 664 secs. Pages in use: 207
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 275/400 73/2000 CANInsertWithFailure-PT-050-LTLFireability-07 1713284 m, 6172 m/sec, 10077305 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 669 secs. Pages in use: 210
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 280/400 74/2000 CANInsertWithFailure-PT-050-LTLFireability-07 1740224 m, 5388 m/sec, 10264478 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 674 secs. Pages in use: 213
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 285/400 75/2000 CANInsertWithFailure-PT-050-LTLFireability-07 1771324 m, 6220 m/sec, 10449955 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 679 secs. Pages in use: 215
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 290/400 76/2000 CANInsertWithFailure-PT-050-LTLFireability-07 1795788 m, 4892 m/sec, 10636009 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 684 secs. Pages in use: 217
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 295/400 77/2000 CANInsertWithFailure-PT-050-LTLFireability-07 1831386 m, 7119 m/sec, 10818584 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 689 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 300/400 78/2000 CANInsertWithFailure-PT-050-LTLFireability-07 1863895 m, 6501 m/sec, 11002434 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 694 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 305/400 79/2000 CANInsertWithFailure-PT-050-LTLFireability-07 1881649 m, 3550 m/sec, 11190402 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 699 secs. Pages in use: 224
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 310/400 80/2000 CANInsertWithFailure-PT-050-LTLFireability-07 1902307 m, 4131 m/sec, 11379344 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 704 secs. Pages in use: 226
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 315/400 82/2000 CANInsertWithFailure-PT-050-LTLFireability-07 1940376 m, 7613 m/sec, 11564375 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 709 secs. Pages in use: 229
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 320/400 83/2000 CANInsertWithFailure-PT-050-LTLFireability-07 1970206 m, 5966 m/sec, 11750768 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 714 secs. Pages in use: 231
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 325/400 85/2000 CANInsertWithFailure-PT-050-LTLFireability-07 2009444 m, 7847 m/sec, 11934731 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 719 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 330/400 86/2000 CANInsertWithFailure-PT-050-LTLFireability-07 2037681 m, 5647 m/sec, 12121432 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 724 secs. Pages in use: 237
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 335/400 88/2000 CANInsertWithFailure-PT-050-LTLFireability-07 2071153 m, 6694 m/sec, 12306584 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 729 secs. Pages in use: 240
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 340/400 89/2000 CANInsertWithFailure-PT-050-LTLFireability-07 2110979 m, 7965 m/sec, 12487077 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 734 secs. Pages in use: 242
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 345/400 91/2000 CANInsertWithFailure-PT-050-LTLFireability-07 2147023 m, 7208 m/sec, 12667273 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 739 secs. Pages in use: 245
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 350/400 91/2000 CANInsertWithFailure-PT-050-LTLFireability-07 2159096 m, 2414 m/sec, 12853918 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 744 secs. Pages in use: 247
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 355/400 93/2000 CANInsertWithFailure-PT-050-LTLFireability-07 2187703 m, 5721 m/sec, 13038220 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 749 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 360/400 94/2000 CANInsertWithFailure-PT-050-LTLFireability-07 2224384 m, 7336 m/sec, 13220173 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 754 secs. Pages in use: 252
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 365/400 95/2000 CANInsertWithFailure-PT-050-LTLFireability-07 2251286 m, 5380 m/sec, 13403364 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 759 secs. Pages in use: 254
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 370/400 97/2000 CANInsertWithFailure-PT-050-LTLFireability-07 2278986 m, 5540 m/sec, 13587237 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 764 secs. Pages in use: 257
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 375/400 98/2000 CANInsertWithFailure-PT-050-LTLFireability-07 2306808 m, 5564 m/sec, 13770598 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 769 secs. Pages in use: 260
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 380/400 100/2000 CANInsertWithFailure-PT-050-LTLFireability-07 2342534 m, 7145 m/sec, 13952234 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 774 secs. Pages in use: 263
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 385/400 102/2000 CANInsertWithFailure-PT-050-LTLFireability-07 2377393 m, 6971 m/sec, 14133756 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 779 secs. Pages in use: 267
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 390/400 103/2000 CANInsertWithFailure-PT-050-LTLFireability-07 2408051 m, 6131 m/sec, 14316020 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 784 secs. Pages in use: 269
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 395/400 104/2000 CANInsertWithFailure-PT-050-LTLFireability-07 2438633 m, 6116 m/sec, 14499538 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 789 secs. Pages in use: 270
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 400/400 106/2000 CANInsertWithFailure-PT-050-LTLFireability-07 2474611 m, 7195 m/sec, 14680386 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 794 secs. Pages in use: 272
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 22 (type EXCL) for CANInsertWithFailure-PT-050-LTLFireability-07 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 799 secs. Pages in use: 273
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 19 (type EXCL) for 18 CANInsertWithFailure-PT-050-LTLFireability-06
[[35mlola[0m][I] time limit : 400 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 22 (type EXCL) for 21 CANInsertWithFailure-PT-050-LTLFireability-07
[[35mlola[0m][I] time limit : 2801 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 19 (type EXCL) for CANInsertWithFailure-PT-050-LTLFireability-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 51
[[35mlola[0m][I] fired transitions : 50
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 5/400 5/5 CANInsertWithFailure-PT-050-LTLFireability-07 85938 m, -477734 m/sec, 167034 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 804 secs. Pages in use: 279
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 22 (type EXCL) for CANInsertWithFailure-PT-050-LTLFireability-07 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-12: AG false state space[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLFireability-15: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLFireability-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 809 secs. Pages in use: 279
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 13 (type EXCL) for 12 CANInsertWithFailure-PT-050-LTLFireability-04
[[35mlola[0m][I] time limit : 465 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 13 (type EXCL) for CANInsertWithFailure-PT-050-LTLFireability-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 CANInsertWithFailure-PT-050-LTLFireability-03
[[35mlola[0m][I] time limit : 558 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 10 (type EXCL) for CANInsertWithFailure-PT-050-LTLFireability-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 87
[[35mlola[0m][I] fired transitions : 87
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 CANInsertWithFailure-PT-050-LTLFireability-02
[[35mlola[0m][I] time limit : 697 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 7 (type EXCL) for CANInsertWithFailure-PT-050-LTLFireability-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 78
[[35mlola[0m][I] fired transitions : 78
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 CANInsertWithFailure-PT-050-LTLFireability-00
[[35mlola[0m][I] time limit : 930 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for CANInsertWithFailure-PT-050-LTLFireability-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 78
[[35mlola[0m][I] fired transitions : 78
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 71 (type EXCL) for 47 CANInsertWithFailure-PT-050-LTLFireability-13
[[35mlola[0m][I] time limit : 1395 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 71 (type EXCL) for CANInsertWithFailure-PT-050-LTLFireability-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 CANInsertWithFailure-PT-050-LTLFireability-01
[[35mlola[0m][I] time limit : 2791 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 4 (type EXCL) for CANInsertWithFailure-PT-050-LTLFireability-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 114
[[35mlola[0m][I] fired transitions : 115
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] Portfolio finished: no open tasks 16
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="CANInsertWithFailure-PT-050"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is CANInsertWithFailure-PT-050, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r071-tall-171620506600132"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/CANInsertWithFailure-PT-050.tgz
mv CANInsertWithFailure-PT-050 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;