About the Execution of LoLA for CANInsertWithFailure-PT-050
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16206.636 | 2391163.00 | 5057862.00 | 7063.80 | F?FFF??FF?F?FFFT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r071-tall-171620506600131.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is CANInsertWithFailure-PT-050, examination is LTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r071-tall-171620506600131
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 16M
-rw-r--r-- 1 mcc users 9.5K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 84K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.4K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 44K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.8K May 19 07:07 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K May 19 15:33 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.1K Apr 22 14:32 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Apr 22 14:32 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K May 14 13:22 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 84K May 14 13:22 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K May 14 13:22 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 69K May 14 13:22 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K May 19 07:10 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K May 19 15:24 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 4 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 16M May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME CANInsertWithFailure-PT-050-LTLCardinality-00
FORMULA_NAME CANInsertWithFailure-PT-050-LTLCardinality-01
FORMULA_NAME CANInsertWithFailure-PT-050-LTLCardinality-02
FORMULA_NAME CANInsertWithFailure-PT-050-LTLCardinality-03
FORMULA_NAME CANInsertWithFailure-PT-050-LTLCardinality-04
FORMULA_NAME CANInsertWithFailure-PT-050-LTLCardinality-05
FORMULA_NAME CANInsertWithFailure-PT-050-LTLCardinality-06
FORMULA_NAME CANInsertWithFailure-PT-050-LTLCardinality-07
FORMULA_NAME CANInsertWithFailure-PT-050-LTLCardinality-08
FORMULA_NAME CANInsertWithFailure-PT-050-LTLCardinality-09
FORMULA_NAME CANInsertWithFailure-PT-050-LTLCardinality-10
FORMULA_NAME CANInsertWithFailure-PT-050-LTLCardinality-11
FORMULA_NAME CANInsertWithFailure-PT-050-LTLCardinality-12
FORMULA_NAME CANInsertWithFailure-PT-050-LTLCardinality-13
FORMULA_NAME CANInsertWithFailure-PT-050-LTLCardinality-14
FORMULA_NAME CANInsertWithFailure-PT-050-LTLCardinality-15
=== Now, execution of the tool begins
BK_START 1717022339273
FORMULA CANInsertWithFailure-PT-050-LTLCardinality-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CANInsertWithFailure-PT-050-LTLCardinality-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CANInsertWithFailure-PT-050-LTLCardinality-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CANInsertWithFailure-PT-050-LTLCardinality-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CANInsertWithFailure-PT-050-LTLCardinality-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CANInsertWithFailure-PT-050-LTLCardinality-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CANInsertWithFailure-PT-050-LTLCardinality-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CANInsertWithFailure-PT-050-LTLCardinality-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CANInsertWithFailure-PT-050-LTLCardinality-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CANInsertWithFailure-PT-050-LTLCardinality-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA CANInsertWithFailure-PT-050-LTLCardinality-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717024730436
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLCardinality.xml[0m
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 72 (type SKEL/SRCH) for 25 CANInsertWithFailure-PT-050-LTLCardinality-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 73 (type SKEL/SRCH) for 38 CANInsertWithFailure-PT-050-LTLCardinality-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] FINISHED task # 73 (type SKEL/SRCH) for CANInsertWithFailure-PT-050-LTLCardinality-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 7
[[35mlola[0m][I] fired transitions : 6
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] FINISHED task # 72 (type SKEL/SRCH) for CANInsertWithFailure-PT-050-LTLCardinality-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 302
[[35mlola[0m][I] fired transitions : 302
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 74 (type SKEL/SRCH) for 12 CANInsertWithFailure-PT-050-LTLCardinality-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 74 (type SKEL/SRCH) for CANInsertWithFailure-PT-050-LTLCardinality-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 398
[[35mlola[0m][I] fired transitions : 398
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 75 (type SKEL/SRCH) for 49 CANInsertWithFailure-PT-050-LTLCardinality-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-10: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 75 LTL SRCH 1/2260 1/5 CANInsertWithFailure-PT-050-LTLCardinality-11 22860 m, 4572 m/sec, 60474 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1341 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 76 (type SKEL/SRCH) for 52 CANInsertWithFailure-PT-050-LTLCardinality-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 78 (type SKEL/SRCH) for 66 CANInsertWithFailure-PT-050-LTLCardinality-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 76 (type SKEL/SRCH) for CANInsertWithFailure-PT-050-LTLCardinality-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 6
[[35mlola[0m][I] fired transitions : 5
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] FINISHED task # 78 (type SKEL/SRCH) for CANInsertWithFailure-PT-050-LTLCardinality-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 198
[[35mlola[0m][I] fired transitions : 198
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-10: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 75 LTL SRCH 6/2260 1/5 CANInsertWithFailure-PT-050-LTLCardinality-11 76858 m, 10799 m/sec, 392824 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1346 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-10: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 75 LTL SRCH 11/2260 1/5 CANInsertWithFailure-PT-050-LTLCardinality-11 126583 m, 9945 m/sec, 754299 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1351 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-10: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 75 LTL SRCH 16/2260 1/5 CANInsertWithFailure-PT-050-LTLCardinality-11 166324 m, 7948 m/sec, 1055703 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1356 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-10: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 75 LTL SRCH 21/2260 1/5 CANInsertWithFailure-PT-050-LTLCardinality-11 210693 m, 8873 m/sec, 1367381 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1361 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-10: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 75 LTL SRCH 26/2260 1/5 CANInsertWithFailure-PT-050-LTLCardinality-11 260691 m, 9999 m/sec, 1706188 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1366 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-10: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 75 LTL SRCH 31/2260 1/5 CANInsertWithFailure-PT-050-LTLCardinality-11 287303 m, 5322 m/sec, 1983343 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1371 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-10: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 75 LTL SRCH 36/2260 1/5 CANInsertWithFailure-PT-050-LTLCardinality-11 315068 m, 5553 m/sec, 2218359 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1376 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-10: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 75 LTL SRCH 41/2260 1/5 CANInsertWithFailure-PT-050-LTLCardinality-11 353911 m, 7768 m/sec, 2534551 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1381 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-10: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 75 LTL SRCH 46/2260 1/5 CANInsertWithFailure-PT-050-LTLCardinality-11 400956 m, 9409 m/sec, 2856738 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1386 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-10: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 75 LTL SRCH 51/2260 1/5 CANInsertWithFailure-PT-050-LTLCardinality-11 431261 m, 6061 m/sec, 3178256 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1391 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[*** LOG ERROR #0001 ***] [2024-05-29 23:02:13] [status_logger] string pointer is null
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-10: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 75 LTL SRCH 56/2260 1/5 CANInsertWithFailure-PT-050-LTLCardinality-11 478108 m, 9369 m/sec, 3539909 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1396 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[*** LOG ERROR #0002 ***] [2024-05-29 23:02:16] [status_logger] string pointer is null
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-10: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 75 LTL SRCH 61/2260 1/5 CANInsertWithFailure-PT-050-LTLCardinality-11 593389 m, 23056 m/sec, 4409355 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1401 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-10: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 75 LTL SRCH 66/2260 1/5 CANInsertWithFailure-PT-050-LTLCardinality-11 715929 m, 24508 m/sec, 5253648 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1406 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-10: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 75 LTL SRCH 71/2260 1/5 CANInsertWithFailure-PT-050-LTLCardinality-11 852703 m, 27354 m/sec, 6670224 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1411 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 45 (type EXCL) for 38 CANInsertWithFailure-PT-050-LTLCardinality-10
[[35mlola[0m][I] time limit : 109 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 45 (type EXCL) for CANInsertWithFailure-PT-050-LTLCardinality-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 78
[[35mlola[0m][I] fired transitions : 78
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 20 (type EXCL) for 19 CANInsertWithFailure-PT-050-LTLCardinality-05
[[35mlola[0m][I] time limit : 128 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 2/128 1/2000 CANInsertWithFailure-PT-050-LTLCardinality-05 5933 m, 1186 m/sec, 14265 t fired, .
[[35mlola[0m][.] 75 LTL SRCH 76/2260 1/5 CANInsertWithFailure-PT-050-LTLCardinality-11 969720 m, 23403 m/sec, 7690222 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1416 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 1 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 7/128 2/2000 CANInsertWithFailure-PT-050-LTLCardinality-05 20647 m, 2942 m/sec, 52827 t fired, .
[[35mlola[0m][.] 75 LTL SRCH 81/2260 1/5 CANInsertWithFailure-PT-050-LTLCardinality-11 1061786 m, 18413 m/sec, 8475344 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1421 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 83 (type EQUN) for 59 CANInsertWithFailure-PT-050-LTLCardinality-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 88 (type EQUN) for 69 CANInsertWithFailure-PT-050-LTLCardinality-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 12/128 2/2000 CANInsertWithFailure-PT-050-LTLCardinality-05 33713 m, 2613 m/sec, 88304 t fired, .
[[35mlola[0m][.] 75 LTL SRCH 86/2260 1/5 CANInsertWithFailure-PT-050-LTLCardinality-11 1119666 m, 11576 m/sec, 9053070 t fired, .
[[35mlola[0m][.] 83 EF STEQ 4/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.] 88 EF STEQ 3/2177 0/5 CANInsertWithFailure-PT-050-LTLCardinality-15 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1426 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 4 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 88 (type EQUN) for CANInsertWithFailure-PT-050-LTLCardinality-15
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 17/128 3/2000 CANInsertWithFailure-PT-050-LTLCardinality-05 48198 m, 2897 m/sec, 128039 t fired, .
[[35mlola[0m][.] 75 LTL SRCH 91/2260 1/5 CANInsertWithFailure-PT-050-LTLCardinality-11 1276249 m, 31316 m/sec, 10518129 t fired, .
[[35mlola[0m][.] 83 EF STEQ 9/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1431 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 22/128 4/2000 CANInsertWithFailure-PT-050-LTLCardinality-05 65955 m, 3551 m/sec, 177216 t fired, .
[[35mlola[0m][.] 75 LTL SRCH 96/2260 1/5 CANInsertWithFailure-PT-050-LTLCardinality-11 1537760 m, 52302 m/sec, 12418418 t fired, .
[[35mlola[0m][.] 83 EF STEQ 14/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1436 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 27/128 5/2000 CANInsertWithFailure-PT-050-LTLCardinality-05 84405 m, 3690 m/sec, 229084 t fired, .
[[35mlola[0m][.] 75 LTL SRCH 101/2260 1/5 CANInsertWithFailure-PT-050-LTLCardinality-11 1759996 m, 44447 m/sec, 14328870 t fired, .
[[35mlola[0m][.] 83 EF STEQ 19/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1441 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 32/128 5/2000 CANInsertWithFailure-PT-050-LTLCardinality-05 100478 m, 3214 m/sec, 274803 t fired, .
[[35mlola[0m][.] 75 LTL SRCH 106/2260 1/5 CANInsertWithFailure-PT-050-LTLCardinality-11 2013334 m, 50667 m/sec, 16272856 t fired, .
[[35mlola[0m][.] 83 EF STEQ 24/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1446 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 37/128 6/2000 CANInsertWithFailure-PT-050-LTLCardinality-05 117801 m, 3464 m/sec, 322602 t fired, .
[[35mlola[0m][.] 75 LTL SRCH 111/2260 1/5 CANInsertWithFailure-PT-050-LTLCardinality-11 2146980 m, 26729 m/sec, 18305754 t fired, .
[[35mlola[0m][.] 83 EF STEQ 29/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1451 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 42/128 7/2000 CANInsertWithFailure-PT-050-LTLCardinality-05 136811 m, 3802 m/sec, 376060 t fired, .
[[35mlola[0m][.] 75 LTL SRCH 116/2260 1/5 CANInsertWithFailure-PT-050-LTLCardinality-11 2383880 m, 47380 m/sec, 20375893 t fired, .
[[35mlola[0m][.] 83 EF STEQ 34/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1456 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 47/128 8/2000 CANInsertWithFailure-PT-050-LTLCardinality-05 154315 m, 3500 m/sec, 423107 t fired, .
[[35mlola[0m][.] 75 LTL SRCH 121/2260 1/5 CANInsertWithFailure-PT-050-LTLCardinality-11 2589740 m, 41172 m/sec, 22403534 t fired, .
[[35mlola[0m][.] 83 EF STEQ 39/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1461 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 52/128 9/2000 CANInsertWithFailure-PT-050-LTLCardinality-05 172464 m, 3629 m/sec, 472576 t fired, .
[[35mlola[0m][.] 75 LTL SRCH 126/2260 1/5 CANInsertWithFailure-PT-050-LTLCardinality-11 2833735 m, 48799 m/sec, 24329308 t fired, .
[[35mlola[0m][.] 83 EF STEQ 44/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1466 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 57/128 10/2000 CANInsertWithFailure-PT-050-LTLCardinality-05 192407 m, 3988 m/sec, 527639 t fired, .
[[35mlola[0m][.] 75 LTL SRCH 131/2260 1/5 CANInsertWithFailure-PT-050-LTLCardinality-11 3026767 m, 38606 m/sec, 26244739 t fired, .
[[35mlola[0m][.] 83 EF STEQ 49/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1471 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 62/128 11/2000 CANInsertWithFailure-PT-050-LTLCardinality-05 212255 m, 3969 m/sec, 581838 t fired, .
[[35mlola[0m][.] 75 LTL SRCH 136/2260 1/5 CANInsertWithFailure-PT-050-LTLCardinality-11 3252928 m, 45232 m/sec, 28148136 t fired, .
[[35mlola[0m][.] 83 EF STEQ 54/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1476 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 67/128 12/2000 CANInsertWithFailure-PT-050-LTLCardinality-05 232136 m, 3976 m/sec, 637466 t fired, .
[[35mlola[0m][.] 75 LTL SRCH 141/2260 1/5 CANInsertWithFailure-PT-050-LTLCardinality-11 3365890 m, 22592 m/sec, 30066836 t fired, .
[[35mlola[0m][.] 83 EF STEQ 59/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1481 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 72/128 13/2000 CANInsertWithFailure-PT-050-LTLCardinality-05 252030 m, 3978 m/sec, 692757 t fired, .
[[35mlola[0m][.] 75 LTL SRCH 146/2260 1/5 CANInsertWithFailure-PT-050-LTLCardinality-11 3620400 m, 50902 m/sec, 32088850 t fired, .
[[35mlola[0m][.] 83 EF STEQ 64/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1486 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 77/128 13/2000 CANInsertWithFailure-PT-050-LTLCardinality-05 266663 m, 2926 m/sec, 734883 t fired, .
[[35mlola[0m][.] 75 LTL SRCH 151/2260 1/5 CANInsertWithFailure-PT-050-LTLCardinality-11 3833728 m, 42665 m/sec, 33932854 t fired, .
[[35mlola[0m][.] 83 EF STEQ 69/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1491 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 82/128 14/2000 CANInsertWithFailure-PT-050-LTLCardinality-05 282808 m, 3229 m/sec, 781068 t fired, .
[[35mlola[0m][.] 75 LTL SRCH 156/2260 1/5 CANInsertWithFailure-PT-050-LTLCardinality-11 4071450 m, 47544 m/sec, 35755837 t fired, .
[[35mlola[0m][.] 83 EF STEQ 74/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1496 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 87/128 14/2000 CANInsertWithFailure-PT-050-LTLCardinality-05 297513 m, 2941 m/sec, 825604 t fired, .
[[35mlola[0m][.] 75 LTL SRCH 161/2260 1/5 CANInsertWithFailure-PT-050-LTLCardinality-11 4183346 m, 22379 m/sec, 37594890 t fired, .
[[35mlola[0m][.] 83 EF STEQ 79/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1501 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 92/128 15/2000 CANInsertWithFailure-PT-050-LTLCardinality-05 313313 m, 3160 m/sec, 872402 t fired, .
[[35mlola[0m][.] 75 LTL SRCH 166/2260 1/5 CANInsertWithFailure-PT-050-LTLCardinality-11 4387402 m, 40811 m/sec, 39372860 t fired, .
[[35mlola[0m][.] 83 EF STEQ 84/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1506 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 97/128 16/2000 CANInsertWithFailure-PT-050-LTLCardinality-05 329507 m, 3238 m/sec, 920483 t fired, .
[[35mlola[0m][.] 75 LTL SRCH 171/2260 1/5 CANInsertWithFailure-PT-050-LTLCardinality-11 4674381 m, 57395 m/sec, 41161548 t fired, .
[[35mlola[0m][.] 83 EF STEQ 89/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1511 secs. Pages in use: 17
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 102/128 16/2000 CANInsertWithFailure-PT-050-LTLCardinality-05 347096 m, 3517 m/sec, 970784 t fired, .
[[35mlola[0m][.] 75 LTL SRCH 176/2260 1/5 CANInsertWithFailure-PT-050-LTLCardinality-11 4818447 m, 28813 m/sec, 42986477 t fired, .
[[35mlola[0m][.] 83 EF STEQ 94/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1516 secs. Pages in use: 17
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 107/128 17/2000 CANInsertWithFailure-PT-050-LTLCardinality-05 364273 m, 3435 m/sec, 1019666 t fired, .
[[35mlola[0m][.] 75 LTL SRCH 181/2260 1/5 CANInsertWithFailure-PT-050-LTLCardinality-11 5099006 m, 56111 m/sec, 44813086 t fired, .
[[35mlola[0m][.] 83 EF STEQ 99/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1521 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 112/128 18/2000 CANInsertWithFailure-PT-050-LTLCardinality-05 382165 m, 3578 m/sec, 1070617 t fired, .
[[35mlola[0m][.] 75 LTL SRCH 186/2260 1/5 CANInsertWithFailure-PT-050-LTLCardinality-11 5326051 m, 45409 m/sec, 46728424 t fired, .
[[35mlola[0m][.] 83 EF STEQ 104/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1526 secs. Pages in use: 19
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 117/128 19/2000 CANInsertWithFailure-PT-050-LTLCardinality-05 400734 m, 3713 m/sec, 1123204 t fired, .
[[35mlola[0m][.] 75 LTL SRCH 191/2260 1/5 CANInsertWithFailure-PT-050-LTLCardinality-11 5327015 m, 192 m/sec, 48535576 t fired, .
[[35mlola[0m][.] 83 EF STEQ 109/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1531 secs. Pages in use: 20
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 122/128 20/2000 CANInsertWithFailure-PT-050-LTLCardinality-05 420162 m, 3885 m/sec, 1176994 t fired, .
[[35mlola[0m][.] 75 LTL SRCH 196/2260 1/5 CANInsertWithFailure-PT-050-LTLCardinality-11 5527157 m, 40028 m/sec, 50663696 t fired, .
[[35mlola[0m][.] 83 EF STEQ 114/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1536 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 127/128 20/2000 CANInsertWithFailure-PT-050-LTLCardinality-05 440483 m, 4064 m/sec, 1233298 t fired, .
[[35mlola[0m][.] 75 LTL SRCH 201/2260 2/5 CANInsertWithFailure-PT-050-LTLCardinality-11 5771372 m, 48843 m/sec, 52640436 t fired, .
[[35mlola[0m][.] 83 EF STEQ 119/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1541 secs. Pages in use: 22
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 20 (type EXCL) for CANInsertWithFailure-PT-050-LTLCardinality-05 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 75 LTL SRCH 206/2260 4/5 CANInsertWithFailure-PT-050-LTLCardinality-11 5959058 m, 37537 m/sec, 54627618 t fired, .
[[35mlola[0m][.] 83 EF STEQ 124/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1546 secs. Pages in use: 25
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 67 (type EXCL) for 66 CANInsertWithFailure-PT-050-LTLCardinality-14
[[35mlola[0m][I] time limit : 128 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 20 (type EXCL) for 19 CANInsertWithFailure-PT-050-LTLCardinality-05
[[35mlola[0m][I] time limit : 2054 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 67 (type EXCL) for CANInsertWithFailure-PT-050-LTLCardinality-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 78
[[35mlola[0m][I] fired transitions : 78
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 5/128 1/5 CANInsertWithFailure-PT-050-LTLCardinality-05 9559 m, -86184 m/sec, 23778 t fired, .
[[35mlola[0m][.] 75 LTL SRCH 211/2260 5/5 CANInsertWithFailure-PT-050-LTLCardinality-11 6098456 m, 27879 m/sec, 55680819 t fired, .
[[35mlola[0m][.] 83 EF STEQ 129/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1551 secs. Pages in use: 28
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 75 (type SRCH) for CANInsertWithFailure-PT-050-LTLCardinality-11 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 1 0 0 0 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 10/128 2/5 CANInsertWithFailure-PT-050-LTLCardinality-05 27282 m, 3544 m/sec, 70387 t fired, .
[[35mlola[0m][.] 83 EF STEQ 134/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1556 secs. Pages in use: 28
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 1 0 0 0 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 15/128 3/5 CANInsertWithFailure-PT-050-LTLCardinality-05 42829 m, 3109 m/sec, 113600 t fired, .
[[35mlola[0m][.] 83 EF STEQ 139/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1561 secs. Pages in use: 28
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 1 0 0 0 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 20/128 3/5 CANInsertWithFailure-PT-050-LTLCardinality-05 59816 m, 3397 m/sec, 160222 t fired, .
[[35mlola[0m][.] 83 EF STEQ 144/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1566 secs. Pages in use: 28
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 1 0 0 0 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 25/128 4/5 CANInsertWithFailure-PT-050-LTLCardinality-05 77599 m, 3556 m/sec, 209471 t fired, .
[[35mlola[0m][.] 83 EF STEQ 149/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1571 secs. Pages in use: 29
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 1 0 0 0 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 30/128 5/5 CANInsertWithFailure-PT-050-LTLCardinality-05 93686 m, 3217 m/sec, 255186 t fired, .
[[35mlola[0m][.] 83 EF STEQ 154/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1576 secs. Pages in use: 31
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 20 (type EXCL) for CANInsertWithFailure-PT-050-LTLCardinality-05 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 1 0 0 0 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 83 EF STEQ 159/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1581 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 57 (type EXCL) for 52 CANInsertWithFailure-PT-050-LTLCardinality-12
[[35mlola[0m][I] time limit : 134 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 57 (type EXCL) for CANInsertWithFailure-PT-050-LTLCardinality-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 51
[[35mlola[0m][I] fired transitions : 50
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 55 (type EXCL) for 52 CANInsertWithFailure-PT-050-LTLCardinality-12
[[35mlola[0m][I] time limit : 144 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 55 (type EXCL) for CANInsertWithFailure-PT-050-LTLCardinality-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 79
[[35mlola[0m][I] fired transitions : 80
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 50 (type EXCL) for 49 CANInsertWithFailure-PT-050-LTLCardinality-11
[[35mlola[0m][I] time limit : 155 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 5/155 5/2000 CANInsertWithFailure-PT-050-LTLCardinality-11 84709 m, 16941 m/sec, 164860 t fired, .
[[35mlola[0m][.] 83 EF STEQ 164/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1586 secs. Pages in use: 33
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 10/155 8/2000 CANInsertWithFailure-PT-050-LTLCardinality-11 131994 m, 9457 m/sec, 344052 t fired, .
[[35mlola[0m][.] 83 EF STEQ 169/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1591 secs. Pages in use: 37
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 15/155 10/2000 CANInsertWithFailure-PT-050-LTLCardinality-11 172109 m, 8023 m/sec, 523818 t fired, .
[[35mlola[0m][.] 83 EF STEQ 174/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1596 secs. Pages in use: 39
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 20/155 11/2000 CANInsertWithFailure-PT-050-LTLCardinality-11 202809 m, 6140 m/sec, 705569 t fired, .
[[35mlola[0m][.] 83 EF STEQ 179/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1601 secs. Pages in use: 41
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 25/155 12/2000 CANInsertWithFailure-PT-050-LTLCardinality-11 238694 m, 7177 m/sec, 884508 t fired, .
[[35mlola[0m][.] 83 EF STEQ 184/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1606 secs. Pages in use: 43
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 30/155 14/2000 CANInsertWithFailure-PT-050-LTLCardinality-11 272753 m, 6811 m/sec, 1064918 t fired, .
[[35mlola[0m][.] 83 EF STEQ 189/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1611 secs. Pages in use: 46
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 35/155 15/2000 CANInsertWithFailure-PT-050-LTLCardinality-11 308006 m, 7050 m/sec, 1243897 t fired, .
[[35mlola[0m][.] 83 EF STEQ 194/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1616 secs. Pages in use: 47
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 40/155 17/2000 CANInsertWithFailure-PT-050-LTLCardinality-11 343516 m, 7102 m/sec, 1422998 t fired, .
[[35mlola[0m][.] 83 EF STEQ 199/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1621 secs. Pages in use: 50
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 45/155 18/2000 CANInsertWithFailure-PT-050-LTLCardinality-11 373218 m, 5940 m/sec, 1603400 t fired, .
[[35mlola[0m][.] 83 EF STEQ 204/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1626 secs. Pages in use: 52
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 50/155 19/2000 CANInsertWithFailure-PT-050-LTLCardinality-11 404634 m, 6283 m/sec, 1782962 t fired, .
[[35mlola[0m][.] 83 EF STEQ 209/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1631 secs. Pages in use: 54
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 55/155 21/2000 CANInsertWithFailure-PT-050-LTLCardinality-11 444735 m, 8020 m/sec, 1958911 t fired, .
[[35mlola[0m][.] 83 EF STEQ 214/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1636 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 60/155 22/2000 CANInsertWithFailure-PT-050-LTLCardinality-11 478758 m, 6804 m/sec, 2135850 t fired, .
[[35mlola[0m][.] 83 EF STEQ 219/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1641 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 65/155 22/2000 CANInsertWithFailure-PT-050-LTLCardinality-11 491184 m, 2485 m/sec, 2318813 t fired, .
[[35mlola[0m][.] 83 EF STEQ 224/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1646 secs. Pages in use: 59
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 70/155 24/2000 CANInsertWithFailure-PT-050-LTLCardinality-11 519323 m, 5627 m/sec, 2500543 t fired, .
[[35mlola[0m][.] 83 EF STEQ 229/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1651 secs. Pages in use: 62
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 75/155 25/2000 CANInsertWithFailure-PT-050-LTLCardinality-11 551222 m, 6379 m/sec, 2681498 t fired, .
[[35mlola[0m][.] 83 EF STEQ 234/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1656 secs. Pages in use: 64
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 80/155 27/2000 CANInsertWithFailure-PT-050-LTLCardinality-11 590200 m, 7795 m/sec, 2861596 t fired, .
[[35mlola[0m][.] 83 EF STEQ 239/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1661 secs. Pages in use: 67
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 85/155 29/2000 CANInsertWithFailure-PT-050-LTLCardinality-11 626154 m, 7190 m/sec, 3041381 t fired, .
[[35mlola[0m][.] 83 EF STEQ 244/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1666 secs. Pages in use: 69
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 90/155 30/2000 CANInsertWithFailure-PT-050-LTLCardinality-11 660640 m, 6897 m/sec, 3219311 t fired, .
[[35mlola[0m][.] 83 EF STEQ 249/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1671 secs. Pages in use: 71
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 95/155 31/2000 CANInsertWithFailure-PT-050-LTLCardinality-11 680733 m, 4018 m/sec, 3402956 t fired, .
[[35mlola[0m][.] 83 EF STEQ 254/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1676 secs. Pages in use: 73
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 100/155 32/2000 CANInsertWithFailure-PT-050-LTLCardinality-11 715082 m, 6869 m/sec, 3583504 t fired, .
[[35mlola[0m][.] 83 EF STEQ 259/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1681 secs. Pages in use: 75
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 105/155 33/2000 CANInsertWithFailure-PT-050-LTLCardinality-11 743617 m, 5707 m/sec, 3766342 t fired, .
[[35mlola[0m][.] 83 EF STEQ 264/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1686 secs. Pages in use: 76
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 110/155 35/2000 CANInsertWithFailure-PT-050-LTLCardinality-11 775394 m, 6355 m/sec, 3945952 t fired, .
[[35mlola[0m][.] 83 EF STEQ 269/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1691 secs. Pages in use: 79
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 115/155 36/2000 CANInsertWithFailure-PT-050-LTLCardinality-11 812269 m, 7375 m/sec, 4125676 t fired, .
[[35mlola[0m][.] 83 EF STEQ 274/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1696 secs. Pages in use: 81
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 120/155 38/2000 CANInsertWithFailure-PT-050-LTLCardinality-11 847842 m, 7114 m/sec, 4304387 t fired, .
[[35mlola[0m][.] 83 EF STEQ 279/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1701 secs. Pages in use: 84
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 125/155 39/2000 CANInsertWithFailure-PT-050-LTLCardinality-11 868343 m, 4100 m/sec, 4488067 t fired, .
[[35mlola[0m][.] 83 EF STEQ 284/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1706 secs. Pages in use: 86
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 130/155 40/2000 CANInsertWithFailure-PT-050-LTLCardinality-11 901049 m, 6541 m/sec, 4669810 t fired, .
[[35mlola[0m][.] 83 EF STEQ 289/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1711 secs. Pages in use: 88
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 135/155 42/2000 CANInsertWithFailure-PT-050-LTLCardinality-11 931768 m, 6143 m/sec, 4851461 t fired, .
[[35mlola[0m][.] 83 EF STEQ 294/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1716 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 140/155 43/2000 CANInsertWithFailure-PT-050-LTLCardinality-11 961792 m, 6004 m/sec, 5033454 t fired, .
[[35mlola[0m][.] 83 EF STEQ 299/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1721 secs. Pages in use: 93
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 145/155 44/2000 CANInsertWithFailure-PT-050-LTLCardinality-11 997903 m, 7222 m/sec, 5213965 t fired, .
[[35mlola[0m][.] 83 EF STEQ 304/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1726 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 150/155 45/2000 CANInsertWithFailure-PT-050-LTLCardinality-11 1017761 m, 3971 m/sec, 5398239 t fired, .
[[35mlola[0m][.] 83 EF STEQ 309/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1731 secs. Pages in use: 96
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 155/155 46/2000 CANInsertWithFailure-PT-050-LTLCardinality-11 1048188 m, 6085 m/sec, 5579043 t fired, .
[[35mlola[0m][.] 83 EF STEQ 314/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1736 secs. Pages in use: 98
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 50 (type EXCL) for CANInsertWithFailure-PT-050-LTLCardinality-11 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 1 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 83 EF STEQ 319/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1741 secs. Pages in use: 100
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 33 (type EXCL) for 32 CANInsertWithFailure-PT-050-LTLCardinality-08
[[35mlola[0m][I] time limit : 154 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 50 (type EXCL) for 49 CANInsertWithFailure-PT-050-LTLCardinality-11
[[35mlola[0m][I] time limit : 1859 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 33 (type EXCL) for CANInsertWithFailure-PT-050-LTLCardinality-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 78
[[35mlola[0m][I] fired transitions : 78
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 1 0 0 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 5/154 5/5 CANInsertWithFailure-PT-050-LTLCardinality-11 84318 m, -192774 m/sec, 164194 t fired, .
[[35mlola[0m][.] 83 EF STEQ 324/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1746 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 50 (type EXCL) for CANInsertWithFailure-PT-050-LTLCardinality-11 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 83 EF STEQ 329/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1751 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 23 (type EXCL) for 22 CANInsertWithFailure-PT-050-LTLCardinality-06
[[35mlola[0m][I] time limit : 168 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 LTL EXCL 5/168 5/2000 CANInsertWithFailure-PT-050-LTLCardinality-06 84534 m, 16906 m/sec, 164563 t fired, .
[[35mlola[0m][.] 83 EF STEQ 334/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1756 secs. Pages in use: 111
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 LTL EXCL 10/168 8/2000 CANInsertWithFailure-PT-050-LTLCardinality-06 131772 m, 9447 m/sec, 342961 t fired, .
[[35mlola[0m][.] 83 EF STEQ 339/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1761 secs. Pages in use: 116
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 LTL EXCL 15/168 10/2000 CANInsertWithFailure-PT-050-LTLCardinality-06 171867 m, 8019 m/sec, 522883 t fired, .
[[35mlola[0m][.] 83 EF STEQ 344/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1766 secs. Pages in use: 120
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 LTL EXCL 20/168 11/2000 CANInsertWithFailure-PT-050-LTLCardinality-06 202799 m, 6186 m/sec, 704433 t fired, .
[[35mlola[0m][.] 83 EF STEQ 349/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1771 secs. Pages in use: 124
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 LTL EXCL 25/168 12/2000 CANInsertWithFailure-PT-050-LTLCardinality-06 238850 m, 7210 m/sec, 884831 t fired, .
[[35mlola[0m][.] 83 EF STEQ 354/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1776 secs. Pages in use: 127
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 LTL EXCL 30/168 14/2000 CANInsertWithFailure-PT-050-LTLCardinality-06 272757 m, 6781 m/sec, 1065060 t fired, .
[[35mlola[0m][.] 83 EF STEQ 359/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1781 secs. Pages in use: 131
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 LTL EXCL 35/168 15/2000 CANInsertWithFailure-PT-050-LTLCardinality-06 308068 m, 7062 m/sec, 1244280 t fired, .
[[35mlola[0m][.] 83 EF STEQ 364/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1786 secs. Pages in use: 134
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 LTL EXCL 40/168 17/2000 CANInsertWithFailure-PT-050-LTLCardinality-06 343534 m, 7093 m/sec, 1424009 t fired, .
[[35mlola[0m][.] 83 EF STEQ 369/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1791 secs. Pages in use: 138
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 LTL EXCL 45/168 18/2000 CANInsertWithFailure-PT-050-LTLCardinality-06 373493 m, 5991 m/sec, 1605021 t fired, .
[[35mlola[0m][.] 83 EF STEQ 374/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1796 secs. Pages in use: 142
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 LTL EXCL 50/168 19/2000 CANInsertWithFailure-PT-050-LTLCardinality-06 404892 m, 6279 m/sec, 1784786 t fired, .
[[35mlola[0m][.] 83 EF STEQ 379/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1801 secs. Pages in use: 144
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 LTL EXCL 55/168 21/2000 CANInsertWithFailure-PT-050-LTLCardinality-06 444777 m, 7977 m/sec, 1961649 t fired, .
[[35mlola[0m][.] 83 EF STEQ 384/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1806 secs. Pages in use: 148
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 LTL EXCL 60/168 22/2000 CANInsertWithFailure-PT-050-LTLCardinality-06 479387 m, 6922 m/sec, 2139231 t fired, .
[[35mlola[0m][.] 83 EF STEQ 389/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1811 secs. Pages in use: 150
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 LTL EXCL 65/168 22/2000 CANInsertWithFailure-PT-050-LTLCardinality-06 491189 m, 2360 m/sec, 2322770 t fired, .
[[35mlola[0m][.] 83 EF STEQ 394/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1816 secs. Pages in use: 151
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 LTL EXCL 70/168 24/2000 CANInsertWithFailure-PT-050-LTLCardinality-06 520450 m, 5852 m/sec, 2504421 t fired, .
[[35mlola[0m][.] 83 EF STEQ 399/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1821 secs. Pages in use: 154
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 LTL EXCL 75/168 25/2000 CANInsertWithFailure-PT-050-LTLCardinality-06 551924 m, 6294 m/sec, 2685777 t fired, .
[[35mlola[0m][.] 83 EF STEQ 404/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1826 secs. Pages in use: 157
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 LTL EXCL 80/168 27/2000 CANInsertWithFailure-PT-050-LTLCardinality-06 590606 m, 7736 m/sec, 2865308 t fired, .
[[35mlola[0m][.] 83 EF STEQ 409/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1831 secs. Pages in use: 162
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 LTL EXCL 85/168 29/2000 CANInsertWithFailure-PT-050-LTLCardinality-06 627417 m, 7362 m/sec, 3045212 t fired, .
[[35mlola[0m][.] 83 EF STEQ 414/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1836 secs. Pages in use: 167
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 LTL EXCL 90/168 30/2000 CANInsertWithFailure-PT-050-LTLCardinality-06 661436 m, 6803 m/sec, 3225293 t fired, .
[[35mlola[0m][.] 83 EF STEQ 419/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1841 secs. Pages in use: 170
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 LTL EXCL 95/168 31/2000 CANInsertWithFailure-PT-050-LTLCardinality-06 682234 m, 4159 m/sec, 3408823 t fired, .
[[35mlola[0m][.] 83 EF STEQ 424/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1846 secs. Pages in use: 174
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 LTL EXCL 100/168 32/2000 CANInsertWithFailure-PT-050-LTLCardinality-06 715568 m, 6666 m/sec, 3588795 t fired, .
[[35mlola[0m][.] 83 EF STEQ 429/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1851 secs. Pages in use: 177
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 LTL EXCL 105/168 33/2000 CANInsertWithFailure-PT-050-LTLCardinality-06 745076 m, 5901 m/sec, 3770114 t fired, .
[[35mlola[0m][.] 83 EF STEQ 434/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1856 secs. Pages in use: 180
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 LTL EXCL 110/168 35/2000 CANInsertWithFailure-PT-050-LTLCardinality-06 777123 m, 6409 m/sec, 3952313 t fired, .
[[35mlola[0m][.] 83 EF STEQ 439/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1861 secs. Pages in use: 184
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 LTL EXCL 115/168 36/2000 CANInsertWithFailure-PT-050-LTLCardinality-06 813314 m, 7238 m/sec, 4132678 t fired, .
[[35mlola[0m][.] 83 EF STEQ 444/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1866 secs. Pages in use: 187
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 LTL EXCL 120/168 38/2000 CANInsertWithFailure-PT-050-LTLCardinality-06 849363 m, 7209 m/sec, 4312154 t fired, .
[[35mlola[0m][.] 83 EF STEQ 449/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1871 secs. Pages in use: 191
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 LTL EXCL 125/168 39/2000 CANInsertWithFailure-PT-050-LTLCardinality-06 869353 m, 3998 m/sec, 4496061 t fired, .
[[35mlola[0m][.] 83 EF STEQ 454/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1876 secs. Pages in use: 194
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 LTL EXCL 130/168 40/2000 CANInsertWithFailure-PT-050-LTLCardinality-06 902499 m, 6629 m/sec, 4677725 t fired, .
[[35mlola[0m][.] 83 EF STEQ 459/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1881 secs. Pages in use: 197
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 LTL EXCL 135/168 42/2000 CANInsertWithFailure-PT-050-LTLCardinality-06 933191 m, 6138 m/sec, 4859506 t fired, .
[[35mlola[0m][.] 83 EF STEQ 464/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1886 secs. Pages in use: 201
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 LTL EXCL 140/168 43/2000 CANInsertWithFailure-PT-050-LTLCardinality-06 963443 m, 6050 m/sec, 5041805 t fired, .
[[35mlola[0m][.] 83 EF STEQ 469/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1891 secs. Pages in use: 203
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 LTL EXCL 145/168 44/2000 CANInsertWithFailure-PT-050-LTLCardinality-06 999553 m, 7222 m/sec, 5222646 t fired, .
[[35mlola[0m][.] 83 EF STEQ 474/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1896 secs. Pages in use: 207
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 LTL EXCL 150/168 45/2000 CANInsertWithFailure-PT-050-LTLCardinality-06 1019557 m, 4000 m/sec, 5407051 t fired, .
[[35mlola[0m][.] 83 EF STEQ 479/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1901 secs. Pages in use: 210
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 LTL EXCL 155/168 46/2000 CANInsertWithFailure-PT-050-LTLCardinality-06 1048224 m, 5733 m/sec, 5588321 t fired, .
[[35mlola[0m][.] 83 EF STEQ 484/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1906 secs. Pages in use: 214
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 LTL EXCL 160/168 47/2000 CANInsertWithFailure-PT-050-LTLCardinality-06 1077259 m, 5807 m/sec, 5770386 t fired, .
[[35mlola[0m][.] 83 EF STEQ 489/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1911 secs. Pages in use: 217
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 LTL EXCL 165/168 48/2000 CANInsertWithFailure-PT-050-LTLCardinality-06 1107797 m, 6107 m/sec, 5951923 t fired, .
[[35mlola[0m][.] 83 EF STEQ 494/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1916 secs. Pages in use: 220
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 23 (type EXCL) for CANInsertWithFailure-PT-050-LTLCardinality-06 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 83 EF STEQ 499/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1921 secs. Pages in use: 225
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 17 (type EXCL) for 12 CANInsertWithFailure-PT-050-LTLCardinality-04
[[35mlola[0m][I] time limit : 167 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 23 (type EXCL) for 22 CANInsertWithFailure-PT-050-LTLCardinality-06
[[35mlola[0m][I] time limit : 1679 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 17 (type EXCL) for CANInsertWithFailure-PT-050-LTLCardinality-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 78
[[35mlola[0m][I] fired transitions : 78
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 LTL EXCL 5/186 5/5 CANInsertWithFailure-PT-050-LTLCardinality-06 84352 m, -204689 m/sec, 164263 t fired, .
[[35mlola[0m][.] 83 EF STEQ 504/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1926 secs. Pages in use: 233
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 23 (type EXCL) for CANInsertWithFailure-PT-050-LTLCardinality-06 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 83 EF STEQ 509/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1931 secs. Pages in use: 233
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 CANInsertWithFailure-PT-050-LTLCardinality-02
[[35mlola[0m][I] time limit : 208 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 7 (type EXCL) for CANInsertWithFailure-PT-050-LTLCardinality-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 78
[[35mlola[0m][I] fired transitions : 78
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 CANInsertWithFailure-PT-050-LTLCardinality-01
[[35mlola[0m][I] time limit : 238 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 5/238 5/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 85034 m, 17006 m/sec, 165433 t fired, .
[[35mlola[0m][.] 83 EF STEQ 514/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1936 secs. Pages in use: 236
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 10/238 8/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 132006 m, 9394 m/sec, 344208 t fired, .
[[35mlola[0m][.] 83 EF STEQ 519/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1941 secs. Pages in use: 241
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 15/238 10/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 172187 m, 8036 m/sec, 524035 t fired, .
[[35mlola[0m][.] 83 EF STEQ 524/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1946 secs. Pages in use: 246
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 20/238 11/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 202818 m, 6126 m/sec, 705104 t fired, .
[[35mlola[0m][.] 83 EF STEQ 529/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1951 secs. Pages in use: 249
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 25/238 12/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 239018 m, 7240 m/sec, 885110 t fired, .
[[35mlola[0m][.] 83 EF STEQ 534/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1956 secs. Pages in use: 252
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 30/238 14/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 272766 m, 6749 m/sec, 1065710 t fired, .
[[35mlola[0m][.] 83 EF STEQ 539/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1961 secs. Pages in use: 256
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 35/238 15/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 308221 m, 7091 m/sec, 1245310 t fired, .
[[35mlola[0m][.] 83 EF STEQ 544/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1966 secs. Pages in use: 260
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 40/238 17/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 343549 m, 7065 m/sec, 1425120 t fired, .
[[35mlola[0m][.] 83 EF STEQ 549/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1971 secs. Pages in use: 265
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 45/238 18/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 373555 m, 6001 m/sec, 1606265 t fired, .
[[35mlola[0m][.] 83 EF STEQ 554/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1976 secs. Pages in use: 267
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 50/238 19/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 405143 m, 6317 m/sec, 1786459 t fired, .
[[35mlola[0m][.] 83 EF STEQ 559/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1981 secs. Pages in use: 271
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 55/238 21/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 444789 m, 7929 m/sec, 1963894 t fired, .
[[35mlola[0m][.] 83 EF STEQ 564/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1986 secs. Pages in use: 275
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 60/238 22/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 479876 m, 7017 m/sec, 2141788 t fired, .
[[35mlola[0m][.] 83 EF STEQ 569/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1991 secs. Pages in use: 278
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 65/238 22/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 491198 m, 2264 m/sec, 2326686 t fired, .
[[35mlola[0m][.] 83 EF STEQ 574/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1996 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 70/238 24/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 521712 m, 6102 m/sec, 2508850 t fired, .
[[35mlola[0m][.] 83 EF STEQ 579/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2001 secs. Pages in use: 284
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 75/238 25/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 553361 m, 6329 m/sec, 2690210 t fired, .
[[35mlola[0m][.] 83 EF STEQ 584/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2006 secs. Pages in use: 287
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 80/238 27/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 591322 m, 7592 m/sec, 2870359 t fired, .
[[35mlola[0m][.] 83 EF STEQ 589/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2011 secs. Pages in use: 290
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 85/238 29/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 628589 m, 7453 m/sec, 3050002 t fired, .
[[35mlola[0m][.] 83 EF STEQ 594/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2016 secs. Pages in use: 294
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 90/238 30/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 661994 m, 6681 m/sec, 3229699 t fired, .
[[35mlola[0m][.] 83 EF STEQ 599/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2021 secs. Pages in use: 297
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 95/238 31/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 683226 m, 4246 m/sec, 3413364 t fired, .
[[35mlola[0m][.] 83 EF STEQ 604/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2026 secs. Pages in use: 300
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 100/238 32/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 716751 m, 6705 m/sec, 3594010 t fired, .
[[35mlola[0m][.] 83 EF STEQ 609/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2031 secs. Pages in use: 303
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 105/238 33/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 746123 m, 5874 m/sec, 3775889 t fired, .
[[35mlola[0m][.] 83 EF STEQ 614/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2036 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 110/238 35/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 778630 m, 6501 m/sec, 3957824 t fired, .
[[35mlola[0m][.] 83 EF STEQ 619/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2041 secs. Pages in use: 310
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 115/238 36/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 813995 m, 7073 m/sec, 4139324 t fired, .
[[35mlola[0m][.] 83 EF STEQ 624/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2046 secs. Pages in use: 313
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 120/238 38/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 850570 m, 7315 m/sec, 4318572 t fired, .
[[35mlola[0m][.] 83 EF STEQ 629/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2051 secs. Pages in use: 318
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 125/238 39/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 870312 m, 3948 m/sec, 4502635 t fired, .
[[35mlola[0m][.] 83 EF STEQ 634/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2056 secs. Pages in use: 320
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 130/238 40/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 903483 m, 6634 m/sec, 4683861 t fired, .
[[35mlola[0m][.] 83 EF STEQ 639/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2061 secs. Pages in use: 323
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 135/238 42/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 934509 m, 6205 m/sec, 4865588 t fired, .
[[35mlola[0m][.] 83 EF STEQ 644/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2066 secs. Pages in use: 326
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 140/238 43/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 964838 m, 6065 m/sec, 5047982 t fired, .
[[35mlola[0m][.] 83 EF STEQ 649/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2071 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 145/238 44/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 1001142 m, 7260 m/sec, 5228472 t fired, .
[[35mlola[0m][.] 83 EF STEQ 654/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2076 secs. Pages in use: 329
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 150/238 45/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 1020207 m, 3813 m/sec, 5413141 t fired, .
[[35mlola[0m][.] 83 EF STEQ 659/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2081 secs. Pages in use: 331
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 155/238 46/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 1048251 m, 5608 m/sec, 5594496 t fired, .
[[35mlola[0m][.] 83 EF STEQ 664/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2086 secs. Pages in use: 334
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 160/238 47/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 1077285 m, 5806 m/sec, 5776644 t fired, .
[[35mlola[0m][.] 83 EF STEQ 669/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2091 secs. Pages in use: 337
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 165/238 48/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 1108722 m, 6287 m/sec, 5958076 t fired, .
[[35mlola[0m][.] 83 EF STEQ 674/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2096 secs. Pages in use: 339
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 170/238 50/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 1146467 m, 7549 m/sec, 6136897 t fired, .
[[35mlola[0m][.] 83 EF STEQ 679/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2101 secs. Pages in use: 343
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 175/238 51/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 1164657 m, 3638 m/sec, 6321663 t fired, .
[[35mlola[0m][.] 83 EF STEQ 684/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2106 secs. Pages in use: 347
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 180/238 52/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 1195890 m, 6246 m/sec, 6502465 t fired, .
[[35mlola[0m][.] 83 EF STEQ 689/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2111 secs. Pages in use: 348
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 185/238 53/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 1227090 m, 6240 m/sec, 6682636 t fired, .
[[35mlola[0m][.] 83 EF STEQ 694/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2116 secs. Pages in use: 351
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 190/238 54/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 1257522 m, 6086 m/sec, 6863462 t fired, .
[[35mlola[0m][.] 83 EF STEQ 699/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2121 secs. Pages in use: 355
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 195/238 56/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 1292827 m, 7061 m/sec, 7041789 t fired, .
[[35mlola[0m][.] 83 EF STEQ 704/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2126 secs. Pages in use: 357
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 200/238 57/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 1311832 m, 3801 m/sec, 7225487 t fired, .
[[35mlola[0m][.] 83 EF STEQ 709/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2131 secs. Pages in use: 360
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 205/238 58/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 1347704 m, 7174 m/sec, 7404050 t fired, .
[[35mlola[0m][.] 83 EF STEQ 714/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2136 secs. Pages in use: 363
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 210/238 59/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 1382759 m, 7011 m/sec, 7582055 t fired, .
[[35mlola[0m][.] 83 EF STEQ 719/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2141 secs. Pages in use: 366
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 215/238 61/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 1419627 m, 7373 m/sec, 7758634 t fired, .
[[35mlola[0m][.] 83 EF STEQ 724/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2146 secs. Pages in use: 370
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 220/238 62/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 1450425 m, 6159 m/sec, 7936632 t fired, .
[[35mlola[0m][.] 83 EF STEQ 729/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2151 secs. Pages in use: 372
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 225/238 62/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 1475095 m, 4934 m/sec, 8117570 t fired, .
[[35mlola[0m][.] 83 EF STEQ 734/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2156 secs. Pages in use: 375
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 230/238 63/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 1481631 m, 1307 m/sec, 8303079 t fired, .
[[35mlola[0m][.] 83 EF STEQ 739/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2161 secs. Pages in use: 377
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 235/238 63/2000 CANInsertWithFailure-PT-050-LTLCardinality-01 1482049 m, 83 m/sec, 8489872 t fired, .
[[35mlola[0m][.] 83 EF STEQ 744/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2166 secs. Pages in use: 380
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 4 (type EXCL) for CANInsertWithFailure-PT-050-LTLCardinality-01 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 83 EF STEQ 749/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2171 secs. Pages in use: 381
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 CANInsertWithFailure-PT-050-LTLCardinality-00
[[35mlola[0m][I] time limit : 238 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 CANInsertWithFailure-PT-050-LTLCardinality-01
[[35mlola[0m][I] time limit : 1429 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for CANInsertWithFailure-PT-050-LTLCardinality-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 79
[[35mlola[0m][I] fired transitions : 79
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 5/238 4/5 CANInsertWithFailure-PT-050-LTLCardinality-01 64146 m, -283580 m/sec, 128710 t fired, .
[[35mlola[0m][.] 83 EF STEQ 754/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2176 secs. Pages in use: 389
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 4 (type EXCL) for CANInsertWithFailure-PT-050-LTLCardinality-01 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-13: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-15: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 83 EF STEQ 759/2178 0/5 CANInsertWithFailure-PT-050-LTLCardinality-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2181 secs. Pages in use: 390
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 80 (type EXCL) for 59 CANInsertWithFailure-PT-050-LTLCardinality-13
[[35mlola[0m][I] time limit : 283 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 80 (type EXCL) for CANInsertWithFailure-PT-050-LTLCardinality-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 87
[[35mlola[0m][I] fired transitions : 87
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 83 (type EQUN) for CANInsertWithFailure-PT-050-LTLCardinality-13 (obsolete)
[[35mlola[0m][I] LAUNCH task # 85 (type EXCL) for 69 CANInsertWithFailure-PT-050-LTLCardinality-15
[[35mlola[0m][I] time limit : 472 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 85 (type EXCL) for CANInsertWithFailure-PT-050-LTLCardinality-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 CANInsertWithFailure-PT-050-LTLCardinality-03
[[35mlola[0m][I] time limit : 709 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 10 (type EXCL) for CANInsertWithFailure-PT-050-LTLCardinality-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 61
[[35mlola[0m][I] fired transitions : 61
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 36 (type EXCL) for 35 CANInsertWithFailure-PT-050-LTLCardinality-09
[[35mlola[0m][I] time limit : 1418 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-13: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLCardinality-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 4/1418 1/2000 CANInsertWithFailure-PT-050-LTLCardinality-09 11277 m, 2255 m/sec, 28365 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2186 secs. Pages in use: 391
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-13: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLCardinality-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 9/1418 2/2000 CANInsertWithFailure-PT-050-LTLCardinality-09 25195 m, 2783 m/sec, 64957 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2191 secs. Pages in use: 394
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-13: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLCardinality-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 14/1418 2/2000 CANInsertWithFailure-PT-050-LTLCardinality-09 37328 m, 2426 m/sec, 98606 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2196 secs. Pages in use: 397
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-13: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLCardinality-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 19/1418 3/2000 CANInsertWithFailure-PT-050-LTLCardinality-09 51135 m, 2761 m/sec, 135927 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2201 secs. Pages in use: 400
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-13: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLCardinality-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 24/1418 4/2000 CANInsertWithFailure-PT-050-LTLCardinality-09 64429 m, 2658 m/sec, 172783 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2206 secs. Pages in use: 404
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-13: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLCardinality-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 29/1418 4/2000 CANInsertWithFailure-PT-050-LTLCardinality-09 77859 m, 2686 m/sec, 210251 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2211 secs. Pages in use: 406
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-13: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLCardinality-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 34/1418 5/2000 CANInsertWithFailure-PT-050-LTLCardinality-09 90112 m, 2450 m/sec, 245124 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2216 secs. Pages in use: 410
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-13: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLCardinality-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 39/1418 6/2000 CANInsertWithFailure-PT-050-LTLCardinality-09 102949 m, 2567 m/sec, 281253 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2221 secs. Pages in use: 414
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-13: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLCardinality-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 44/1418 6/2000 CANInsertWithFailure-PT-050-LTLCardinality-09 116713 m, 2752 m/sec, 319666 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2226 secs. Pages in use: 415
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-13: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLCardinality-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 49/1418 7/2000 CANInsertWithFailure-PT-050-LTLCardinality-09 131684 m, 2994 m/sec, 361499 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2231 secs. Pages in use: 418
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-13: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLCardinality-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 54/1418 8/2000 CANInsertWithFailure-PT-050-LTLCardinality-09 146998 m, 3062 m/sec, 404208 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2236 secs. Pages in use: 422
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-13: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLCardinality-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 59/1418 8/2000 CANInsertWithFailure-PT-050-LTLCardinality-09 161662 m, 2932 m/sec, 442831 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2241 secs. Pages in use: 424
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-13: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLCardinality-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 64/1418 9/2000 CANInsertWithFailure-PT-050-LTLCardinality-09 176723 m, 3012 m/sec, 484292 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2246 secs. Pages in use: 428
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-13: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLCardinality-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 69/1418 10/2000 CANInsertWithFailure-PT-050-LTLCardinality-09 192494 m, 3154 m/sec, 527903 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2251 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-13: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLCardinality-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 74/1418 11/2000 CANInsertWithFailure-PT-050-LTLCardinality-09 208303 m, 3161 m/sec, 570982 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2256 secs. Pages in use: 436
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-13: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLCardinality-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 79/1418 12/2000 CANInsertWithFailure-PT-050-LTLCardinality-09 224984 m, 3336 m/sec, 617337 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2261 secs. Pages in use: 439
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-13: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLCardinality-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 84/1418 12/2000 CANInsertWithFailure-PT-050-LTLCardinality-09 240624 m, 3128 m/sec, 660622 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2266 secs. Pages in use: 442
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-13: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLCardinality-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 89/1418 13/2000 CANInsertWithFailure-PT-050-LTLCardinality-09 254829 m, 2841 m/sec, 700599 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2271 secs. Pages in use: 447
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-13: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLCardinality-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 94/1418 13/2000 CANInsertWithFailure-PT-050-LTLCardinality-09 266724 m, 2379 m/sec, 735022 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2276 secs. Pages in use: 448
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-13: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLCardinality-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 99/1418 14/2000 CANInsertWithFailure-PT-050-LTLCardinality-09 279886 m, 2632 m/sec, 772246 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2281 secs. Pages in use: 452
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-13: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLCardinality-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 104/1418 14/2000 CANInsertWithFailure-PT-050-LTLCardinality-09 290846 m, 2192 m/sec, 805981 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2286 secs. Pages in use: 454
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-13: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLCardinality-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 109/1418 15/2000 CANInsertWithFailure-PT-050-LTLCardinality-09 303321 m, 2495 m/sec, 842028 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2291 secs. Pages in use: 456
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-13: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLCardinality-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 114/1418 15/2000 CANInsertWithFailure-PT-050-LTLCardinality-09 315588 m, 2453 m/sec, 878929 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2296 secs. Pages in use: 458
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-13: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLCardinality-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 119/1418 16/2000 CANInsertWithFailure-PT-050-LTLCardinality-09 328542 m, 2590 m/sec, 917593 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2301 secs. Pages in use: 462
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-13: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLCardinality-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 124/1418 16/2000 CANInsertWithFailure-PT-050-LTLCardinality-09 341943 m, 2680 m/sec, 956709 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2306 secs. Pages in use: 465
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-13: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLCardinality-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 129/1418 17/2000 CANInsertWithFailure-PT-050-LTLCardinality-09 356031 m, 2817 m/sec, 996208 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2311 secs. Pages in use: 469
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-13: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLCardinality-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 134/1418 18/2000 CANInsertWithFailure-PT-050-LTLCardinality-09 370343 m, 2862 m/sec, 1036754 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2316 secs. Pages in use: 471
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-13: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLCardinality-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 139/1418 18/2000 CANInsertWithFailure-PT-050-LTLCardinality-09 383556 m, 2642 m/sec, 1074928 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2321 secs. Pages in use: 473
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-13: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLCardinality-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 144/1418 19/2000 CANInsertWithFailure-PT-050-LTLCardinality-09 398236 m, 2936 m/sec, 1116118 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2326 secs. Pages in use: 478
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-13: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLCardinality-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 149/1418 19/2000 CANInsertWithFailure-PT-050-LTLCardinality-09 414070 m, 3166 m/sec, 1160619 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2331 secs. Pages in use: 481
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-13: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLCardinality-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 154/1418 20/2000 CANInsertWithFailure-PT-050-LTLCardinality-09 429876 m, 3161 m/sec, 1203454 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2336 secs. Pages in use: 483
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-13: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLCardinality-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 159/1418 21/2000 CANInsertWithFailure-PT-050-LTLCardinality-09 446007 m, 3226 m/sec, 1248938 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2341 secs. Pages in use: 488
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-13: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLCardinality-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 164/1418 21/2000 CANInsertWithFailure-PT-050-LTLCardinality-09 458202 m, 2439 m/sec, 1282918 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2346 secs. Pages in use: 490
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-13: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLCardinality-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 170/1418 21/2000 CANInsertWithFailure-PT-050-LTLCardinality-09 466300 m, 1619 m/sec, 1305316 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2352 secs. Pages in use: 490
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-07: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-13: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mCANInsertWithFailure-PT-050-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mCANInsertWithFailure-PT-050-LTLCardinality-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] CANInsertWithFailure-PT-050-LTLCardinality-11: LTL 0 0 0 0 0 0 2 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 LTL EXCL 202/1418 21/2000 CANInsertWithFailure-PT-050-LTLCardinality-09 466930 m, 126 m/sec, 1307271 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2384 secs. Pages in use: 490
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 409 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="CANInsertWithFailure-PT-050"
export BK_EXAMINATION="LTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is CANInsertWithFailure-PT-050, examination is LTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r071-tall-171620506600131"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/CANInsertWithFailure-PT-050.tgz
mv CANInsertWithFailure-PT-050 execution
cd execution
if [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "UpperBounds" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] || [ "LTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;