Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r069-tall-171620504200274.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool greatspnxred
Input is CircadianClock-PT-000001, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r069-tall-171620504200274
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 436K
-rw-r--r-- 1 mcc users 6.3K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 65K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.9K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 62K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Apr 22 14:32 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Apr 22 14:32 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Apr 22 14:32 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Apr 22 14:32 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.0K Apr 12 03:04 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 92K Apr 12 03:04 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.8K Apr 12 03:04 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 69K Apr 12 03:04 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 22 14:32 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Apr 22 14:32 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 7 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 12K May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME CircadianClock-PT-000001-CTLFireability-2024-00
FORMULA_NAME CircadianClock-PT-000001-CTLFireability-2024-01
FORMULA_NAME CircadianClock-PT-000001-CTLFireability-2024-02
FORMULA_NAME CircadianClock-PT-000001-CTLFireability-2024-03
FORMULA_NAME CircadianClock-PT-000001-CTLFireability-2024-04
FORMULA_NAME CircadianClock-PT-000001-CTLFireability-2024-05
FORMULA_NAME CircadianClock-PT-000001-CTLFireability-2024-06
FORMULA_NAME CircadianClock-PT-000001-CTLFireability-2024-07
FORMULA_NAME CircadianClock-PT-000001-CTLFireability-2024-08
FORMULA_NAME CircadianClock-PT-000001-CTLFireability-2024-09
FORMULA_NAME CircadianClock-PT-000001-CTLFireability-2024-10
FORMULA_NAME CircadianClock-PT-000001-CTLFireability-2024-11
FORMULA_NAME CircadianClock-PT-000001-CTLFireability-2023-12
FORMULA_NAME CircadianClock-PT-000001-CTLFireability-2023-13
FORMULA_NAME CircadianClock-PT-000001-CTLFireability-2023-14
FORMULA_NAME CircadianClock-PT-000001-CTLFireability-2023-15

=== Now, execution of the tool begins

BK_START 1716424952182

Invoking MCC driver with
BK_TOOL=greatspnxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=CircadianClock-PT-000001
BK_MEMORY_CONFINEMENT=16384
Applying reductions before tool greatspn
Invoking reducer
Running Version 202405141337
[2024-05-23 00:42:33] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2024-05-23 00:42:33] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2024-05-23 00:42:33] [INFO ] Load time of PNML (sax parser for PT used): 34 ms
[2024-05-23 00:42:33] [INFO ] Transformed 14 places.
[2024-05-23 00:42:33] [INFO ] Transformed 16 transitions.
[2024-05-23 00:42:33] [INFO ] Found NUPN structural information;
[2024-05-23 00:42:33] [INFO ] Parsed PT model containing 14 places and 16 transitions and 58 arcs in 123 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 16 ms.
Initial state reduction rules removed 2 formulas.
FORMULA CircadianClock-PT-000001-CTLFireability-2024-02 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA CircadianClock-PT-000001-CTLFireability-2023-14 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 14 out of 14 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 7 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
[2024-05-23 00:42:33] [INFO ] Flow matrix only has 14 transitions (discarded 2 similar events)
// Phase 1: matrix 14 rows 14 cols
[2024-05-23 00:42:33] [INFO ] Computed 7 invariants in 8 ms
[2024-05-23 00:42:33] [INFO ] Implicit Places using invariants in 121 ms returned []
[2024-05-23 00:42:33] [INFO ] Flow matrix only has 14 transitions (discarded 2 similar events)
[2024-05-23 00:42:33] [INFO ] Invariant cache hit.
[2024-05-23 00:42:33] [INFO ] State equation strengthened by 2 read => feed constraints.
[2024-05-23 00:42:33] [INFO ] Implicit Places using invariants and state equation in 44 ms returned []
Implicit Place search using SMT with State Equation took 192 ms to find 0 implicit places.
Running 14 sub problems to find dead transitions.
[2024-05-23 00:42:33] [INFO ] Flow matrix only has 14 transitions (discarded 2 similar events)
[2024-05-23 00:42:33] [INFO ] Invariant cache hit.
[2024-05-23 00:42:33] [INFO ] State equation strengthened by 2 read => feed constraints.
At refinement iteration 0 (INCLUDED_ONLY) 0/14 variables, 14/14 constraints. Problems are: Problem set: 0 solved, 14 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/14 variables, 7/21 constraints. Problems are: Problem set: 0 solved, 14 unsolved
At refinement iteration 2 (INCLUDED_ONLY) 0/14 variables, 0/21 constraints. Problems are: Problem set: 0 solved, 14 unsolved
At refinement iteration 3 (OVERLAPS) 14/28 variables, 14/35 constraints. Problems are: Problem set: 0 solved, 14 unsolved
At refinement iteration 4 (INCLUDED_ONLY) 0/28 variables, 2/37 constraints. Problems are: Problem set: 0 solved, 14 unsolved
At refinement iteration 5 (INCLUDED_ONLY) 0/28 variables, 0/37 constraints. Problems are: Problem set: 0 solved, 14 unsolved
At refinement iteration 6 (OVERLAPS) 0/28 variables, 0/37 constraints. Problems are: Problem set: 0 solved, 14 unsolved
No progress, stopping.
After SMT solving in domain Real declared 28/28 variables, and 37 constraints, problems are : Problem set: 0 solved, 14 unsolved in 173 ms.
Refiners :[Domain max(s): 14/14 constraints, Positive P Invariants (semi-flows): 7/7 constraints, State Equation: 14/14 constraints, ReadFeed: 2/2 constraints, PredecessorRefiner: 14/14 constraints, Known Traps: 0/0 constraints]
Escalating to Integer solving :Problem set: 0 solved, 14 unsolved
At refinement iteration 0 (INCLUDED_ONLY) 0/14 variables, 14/14 constraints. Problems are: Problem set: 0 solved, 14 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/14 variables, 7/21 constraints. Problems are: Problem set: 0 solved, 14 unsolved
At refinement iteration 2 (INCLUDED_ONLY) 0/14 variables, 0/21 constraints. Problems are: Problem set: 0 solved, 14 unsolved
At refinement iteration 3 (OVERLAPS) 14/28 variables, 14/35 constraints. Problems are: Problem set: 0 solved, 14 unsolved
At refinement iteration 4 (INCLUDED_ONLY) 0/28 variables, 2/37 constraints. Problems are: Problem set: 0 solved, 14 unsolved
At refinement iteration 5 (INCLUDED_ONLY) 0/28 variables, 14/51 constraints. Problems are: Problem set: 0 solved, 14 unsolved
At refinement iteration 6 (INCLUDED_ONLY) 0/28 variables, 0/51 constraints. Problems are: Problem set: 0 solved, 14 unsolved
At refinement iteration 7 (OVERLAPS) 0/28 variables, 0/51 constraints. Problems are: Problem set: 0 solved, 14 unsolved
No progress, stopping.
After SMT solving in domain Int declared 28/28 variables, and 51 constraints, problems are : Problem set: 0 solved, 14 unsolved in 144 ms.
Refiners :[Domain max(s): 14/14 constraints, Positive P Invariants (semi-flows): 7/7 constraints, State Equation: 14/14 constraints, ReadFeed: 2/2 constraints, PredecessorRefiner: 14/14 constraints, Known Traps: 0/0 constraints]
After SMT, in 344ms problems are : Problem set: 0 solved, 14 unsolved
Search for dead transitions found 0 dead transitions in 353ms
Finished structural reductions in LTL mode , in 1 iterations and 576 ms. Remains : 14/14 places, 16/16 transitions.
Support contains 14 out of 14 places after structural reductions.
[2024-05-23 00:42:34] [INFO ] Flatten gal took : 14 ms
[2024-05-23 00:42:34] [INFO ] Flatten gal took : 5 ms
[2024-05-23 00:42:34] [INFO ] Input system was already deterministic with 16 transitions.
Reduction of identical properties reduced properties to check from 42 to 35
RANDOM walk for 40000 steps (8 resets) in 1503 ms. (26 steps per ms) remains 5/35 properties
BEST_FIRST walk for 40003 steps (8 resets) in 242 ms. (164 steps per ms) remains 5/5 properties
BEST_FIRST walk for 40003 steps (8 resets) in 98 ms. (404 steps per ms) remains 5/5 properties
BEST_FIRST walk for 40003 steps (8 resets) in 99 ms. (400 steps per ms) remains 5/5 properties
BEST_FIRST walk for 40003 steps (8 resets) in 69 ms. (571 steps per ms) remains 5/5 properties
BEST_FIRST walk for 40003 steps (8 resets) in 84 ms. (470 steps per ms) remains 5/5 properties
[2024-05-23 00:42:35] [INFO ] Flow matrix only has 14 transitions (discarded 2 similar events)
[2024-05-23 00:42:35] [INFO ] Invariant cache hit.
[2024-05-23 00:42:35] [INFO ] State equation strengthened by 2 read => feed constraints.
Problem AtomicPropp37 is UNSAT
All remaining problems are real, not stopping.
At refinement iteration 0 (INCLUDED_ONLY) 0/14 variables, 14/14 constraints. Problems are: Problem set: 1 solved, 4 unsolved
Problem AtomicPropp2 is UNSAT
Problem AtomicPropp10 is UNSAT
Problem AtomicPropp20 is UNSAT
Problem AtomicPropp30 is UNSAT
After SMT solving in domain Real declared 14/28 variables, and 21 constraints, problems are : Problem set: 5 solved, 0 unsolved in 31 ms.
Refiners :[Domain max(s): 14/14 constraints, Positive P Invariants (semi-flows): 7/7 constraints, State Equation: 0/14 constraints, ReadFeed: 0/2 constraints, PredecessorRefiner: 5/5 constraints, Known Traps: 0/0 constraints]
After SMT, in 49ms problems are : Problem set: 5 solved, 0 unsolved
Skipping Parikh replay, no witness traces provided.
Successfully simplified 5 atomic propositions for a total of 14 simplifications.
[2024-05-23 00:42:35] [INFO ] Initial state reduction rules for CTL removed 2 formulas.
[2024-05-23 00:42:35] [INFO ] Flatten gal took : 4 ms
FORMULA CircadianClock-PT-000001-CTLFireability-2024-10 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA CircadianClock-PT-000001-CTLFireability-2024-03 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2024-05-23 00:42:35] [INFO ] Flatten gal took : 2 ms
[2024-05-23 00:42:35] [INFO ] Input system was already deterministic with 16 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 0 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 14/14 places, 16/16 transitions.
[2024-05-23 00:42:35] [INFO ] Flatten gal took : 1 ms
[2024-05-23 00:42:35] [INFO ] Flatten gal took : 1 ms
[2024-05-23 00:42:35] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 4 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5 ms. Remains : 14/14 places, 16/16 transitions.
[2024-05-23 00:42:35] [INFO ] Flatten gal took : 2 ms
[2024-05-23 00:42:35] [INFO ] Flatten gal took : 2 ms
[2024-05-23 00:42:35] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 1 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 14/14 places, 16/16 transitions.
[2024-05-23 00:42:35] [INFO ] Flatten gal took : 1 ms
[2024-05-23 00:42:35] [INFO ] Flatten gal took : 1 ms
[2024-05-23 00:42:35] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 0 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 14/14 places, 16/16 transitions.
[2024-05-23 00:42:35] [INFO ] Flatten gal took : 1 ms
[2024-05-23 00:42:35] [INFO ] Flatten gal took : 2 ms
[2024-05-23 00:42:35] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 0 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 14/14 places, 16/16 transitions.
[2024-05-23 00:42:35] [INFO ] Flatten gal took : 1 ms
[2024-05-23 00:42:35] [INFO ] Flatten gal took : 2 ms
[2024-05-23 00:42:35] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 1 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 14/14 places, 16/16 transitions.
[2024-05-23 00:42:35] [INFO ] Flatten gal took : 1 ms
[2024-05-23 00:42:35] [INFO ] Flatten gal took : 2 ms
[2024-05-23 00:42:35] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 2 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 14/14 places, 16/16 transitions.
[2024-05-23 00:42:35] [INFO ] Flatten gal took : 1 ms
[2024-05-23 00:42:35] [INFO ] Flatten gal took : 1 ms
[2024-05-23 00:42:35] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 0 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 14/14 places, 16/16 transitions.
[2024-05-23 00:42:35] [INFO ] Flatten gal took : 1 ms
[2024-05-23 00:42:35] [INFO ] Flatten gal took : 1 ms
[2024-05-23 00:42:35] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 1 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 14/14 places, 16/16 transitions.
[2024-05-23 00:42:35] [INFO ] Flatten gal took : 1 ms
[2024-05-23 00:42:35] [INFO ] Flatten gal took : 1 ms
[2024-05-23 00:42:35] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 0 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 14/14 places, 16/16 transitions.
[2024-05-23 00:42:35] [INFO ] Flatten gal took : 0 ms
[2024-05-23 00:42:35] [INFO ] Flatten gal took : 1 ms
[2024-05-23 00:42:35] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 1 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 14/14 places, 16/16 transitions.
[2024-05-23 00:42:35] [INFO ] Flatten gal took : 1 ms
[2024-05-23 00:42:35] [INFO ] Flatten gal took : 2 ms
[2024-05-23 00:42:35] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 0 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 0 ms. Remains : 14/14 places, 16/16 transitions.
[2024-05-23 00:42:35] [INFO ] Flatten gal took : 0 ms
[2024-05-23 00:42:35] [INFO ] Flatten gal took : 1 ms
[2024-05-23 00:42:35] [INFO ] Input system was already deterministic with 16 transitions.
[2024-05-23 00:42:35] [INFO ] Flatten gal took : 2 ms
[2024-05-23 00:42:35] [INFO ] Flatten gal took : 1 ms
[2024-05-23 00:42:35] [INFO ] Export to MCC of 12 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2024-05-23 00:42:35] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 14 places, 16 transitions and 58 arcs took 3 ms.
Total runtime 2028 ms.
There are residual formulas that ITS could not solve within timeout
----------------------------------------------------------------------
GreatSPN-meddly tool, MCC 2023
----------------------------------------------------------------------

Running CircadianClock-PT-000001

IS_COLORED=
IS_NUPN=

LOADING PETRI NET FILE /home/mcc/execution/412/model.pnml (PNML) ...
PNML VERSION 2009, P/T NET.
COLOR CLASSES: 0
CONSTANTS: 0
PLACES: 14
TRANSITIONS: 16
COLOR VARS: 0
MEASURES: 0
LOADING TIME: [User 0.000s, Sys 0.000s]


SAVING FILE /home/mcc/execution/412/model (.net / .def) ...
EXPORT TIME: [User 0.000s, Sys 0.000s]


----------------------------------------------------------------------
GreatSPN/Meddly.
Copyright (C) 1987-2022, University of Torino, Italy.
website: https://github.com/greatspn/SOURCES

Based on MEDDLY version 0.16.0
Copyright (C) 2009, Iowa State University Research Foundation, Inc.
website: http://meddly.sourceforge.net

Process ID: 535
MODEL NAME: /home/mcc/execution/412/model
14 places, 16 transitions.

Creating all event NSFs..
Creating all event NSFs..
Creating all event NSFs..
Split: SplitSubtract
Start RS construction.
Split: SplitSubtract
Start RS construction.
Creating all event NSFs..
Split: SplitSubtract
Start RS construction.
Building monolithic NSF...
FORMULA CircadianClock-PT-000001-CTLFireability-2024-00 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA CircadianClock-PT-000001-CTLFireability-2024-04 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA CircadianClock-PT-000001-CTLFireability-2024-01 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA CircadianClock-PT-000001-CTLFireability-2024-05 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA CircadianClock-PT-000001-CTLFireability-2024-07 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA CircadianClock-PT-000001-CTLFireability-2024-08 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA CircadianClock-PT-000001-CTLFireability-2024-06 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA CircadianClock-PT-000001-CTLFireability-2024-11 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA CircadianClock-PT-000001-CTLFireability-2023-12 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA CircadianClock-PT-000001-CTLFireability-2024-09 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA CircadianClock-PT-000001-CTLFireability-2023-13 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA CircadianClock-PT-000001-CTLFireability-2023-15 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
Ok.
EXITCODE: 0
----------------------------------------------------------------------

BK_STOP 1716424956064

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202405141337.jar
+ VERSION=202405141337
+ echo 'Running Version 202405141337'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="CircadianClock-PT-000001"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="greatspnxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool greatspnxred"
echo " Input is CircadianClock-PT-000001, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r069-tall-171620504200274"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/CircadianClock-PT-000001.tgz
mv CircadianClock-PT-000001 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;