About the Execution of LoLA for BridgeAndVehicles-PT-V50P50N50
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 0.000 | 2971336.00 | 0.00 | 0.00 | ?????????T??F??? | normal |
Execution Chart
Sorry, for this execution, no execution chart could be reported.
Trace from the execution
Formatting '/mnt/tpsp/fkordon/mcc2024-input.r049-tajo-171620400400266.qcow2', fmt=qcow2 size=4294967296 backing_file='/mnt/tpsp/fkordon/mcc2024-input.qcow2' backing_fmt='qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is BridgeAndVehicles-PT-V50P50N50, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r049-tajo-171620400400266
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 15M
-rw-r--r-- 1 mcc users 23K Apr 13 03:34 CTLCardinality.txt
-rw-r--r-- 1 mcc users 138K Apr 13 03:34 CTLCardinality.xml
-rw-r--r-- 1 mcc users 473K Apr 13 03:26 CTLFireability.txt
-rw-r--r-- 1 mcc users 1.8M Apr 13 03:26 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 8.6K Apr 22 14:30 LTLCardinality.txt
-rw-r--r-- 1 mcc users 37K Apr 22 14:30 LTLCardinality.xml
-rw-r--r-- 1 mcc users 189K Apr 22 14:30 LTLFireability.txt
-rw-r--r-- 1 mcc users 571K Apr 22 14:30 LTLFireability.xml
-rw-r--r-- 1 mcc users 36K Apr 13 05:53 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 196K Apr 13 05:53 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 1.4M Apr 13 05:48 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 5.1M Apr 13 05:48 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 4.6K Apr 22 14:30 UpperBounds.txt
-rw-r--r-- 1 mcc users 9.7K Apr 22 14:30 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 10 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 4.5M May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-00
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-01
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-02
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-03
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-04
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-05
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-06
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-07
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-08
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-09
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-10
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-11
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-12
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-13
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-14
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717014198202
FORMULA BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717017169538
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-01: DISJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-02: DISJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-05: DISJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-06: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-08: DISJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-09: AXAG 0 0 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-12: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-13: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 6 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-01: DISJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-02: DISJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-05: DISJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-06: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-08: DISJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-09: AXAG 0 0 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-12: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-13: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 11 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 69 (type CNST) for 68 BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-12
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 69 (type CNST) for BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-01: DISJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-02: DISJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-05: DISJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-06: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-08: DISJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-09: AXAG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-13: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 16 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 8 (type EXCL) for 3 BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 123 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-00: CTL 1 0 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-01: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-02: DISJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-05: DISJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-06: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-08: DISJ 0 0 0 0 4 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-09: AXAG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-13: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 8 CTL EXCL 1/127 1/2000 BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-01 15235 m, 3047 m/sec, 37403 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 21 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 84 (type EQUN) for 10 BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 86 (type EQUN) for 10 BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
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[[35mlola[0m][.] 63 CTL EXCL 35/188 12/2000 BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-10 2331745 m, 64917 m/sec, 10023514 t fired, .
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[[35mlola[0m][.] 63 CTL EXCL 70/188 24/2000 BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-10 4542149 m, 70128 m/sec, 20014451 t fired, .
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[[35mlola[0m][.] 63 CTL EXCL 110/188 36/2000 BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-10 7119621 m, 61567 m/sec, 31746624 t fired, .
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[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-14: CTL false CTL model checker[0m
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[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-01: DISJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-05: DISJ 0 1 0 0 3 1 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-06: CONJ 0 0 0 0 3 0 1 2
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-08: DISJ 0 1 0 0 11 0 0 4
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][I] LAUNCH task # 21 (type EXCL) for 20 BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 229 sec
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[[35mlola[0m][I] LAUNCH task # 28 (type EXCL) for 23 BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 2298 sec
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[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-14: CTL false CTL model checker[0m
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[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-01: DISJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-02: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-05: DISJ 0 1 1 0 3 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-06: CONJ 0 0 0 0 3 0 1 2
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-08: DISJ 0 1 0 0 11 0 0 4
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] 21 CTL EXCL 5/229 1/2000 BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-04 165046 m, 33009 m/sec, 482073 t fired, .
[[35mlola[0m][.] 28 CTL EXCL 4/2298 1/5 BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-05 113509 m, -1117338 m/sec, 518522 t fired, .
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[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-01: DISJ 0 1 0 0 2 0 1 0
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[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-05: DISJ 0 1 1 0 3 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-06: CONJ 0 0 0 0 3 0 1 2
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-08: DISJ 0 1 0 0 11 0 0 4
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[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] 21 CTL EXCL 10/229 2/2000 BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-04 356464 m, 38283 m/sec, 1086094 t fired, .
[[35mlola[0m][.] 28 CTL EXCL 9/208 2/5 BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-05 255007 m, 28299 m/sec, 1193044 t fired, .
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[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-06: CONJ 0 0 0 0 3 0 1 2
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] 21 CTL EXCL 15/229 3/2000 BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-04 547072 m, 38121 m/sec, 1696801 t fired, .
[[35mlola[0m][.] 28 CTL EXCL 14/208 3/5 BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-05 422751 m, 33548 m/sec, 1985018 t fired, .
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[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] 21 CTL EXCL 20/229 4/2000 BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-04 738621 m, 38309 m/sec, 2318274 t fired, .
[[35mlola[0m][.] 28 CTL EXCL 19/208 4/5 BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-05 582557 m, 31961 m/sec, 2730082 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 24/208 4/5 BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-05 711922 m, 25873 m/sec, 3318549 t fired, .
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[[35mlola[0m][.] 81 EFEG EXCL 9/339 2/2000 BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-02 211575 m, 16687 m/sec, 712037 t fired, .
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[[35mlola[0m][.] 81 EFEG EXCL 14/339 2/2000 BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-02 294904 m, 16665 m/sec, 1030699 t fired, .
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[[35mlola[0m][.] 81 EFEG EXCL 19/339 3/2000 BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-02 378715 m, 16762 m/sec, 1349925 t fired, .
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[[35mlola[0m][.] 81 EFEG EXCL 24/339 3/2000 BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-02 462974 m, 16851 m/sec, 1669928 t fired, .
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[[35mlola[0m][.] 81 EFEG EXCL 29/339 3/2000 BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-02 548121 m, 17029 m/sec, 1991530 t fired, .
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[[35mlola[0m][.] 81 EFEG EXCL 34/339 4/2000 BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-02 632940 m, 16963 m/sec, 2311378 t fired, .
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[[35mlola[0m][.] 81 EFEG EXCL 49/339 5/2000 BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-02 878167 m, 15115 m/sec, 3227580 t fired, .
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[[35mlola[0m][.] 81 EFEG EXCL 54/339 6/2000 BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-02 955830 m, 15532 m/sec, 3514652 t fired, .
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[[35mlola[0m][.] 81 EFEG EXCL 59/339 6/2000 BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-02 1035635 m, 15961 m/sec, 3808219 t fired, .
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[[35mlola[0m][.] 81 EFEG EXCL 64/339 6/2000 BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-02 1120769 m, 17026 m/sec, 4119962 t fired, .
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[[35mlola[0m][.] 81 EFEG EXCL 69/339 7/2000 BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-02 1200882 m, 16022 m/sec, 4411891 t fired, .
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[[35mlola[0m][.] 81 EFEG EXCL 74/339 7/2000 BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-02 1279064 m, 15636 m/sec, 4695040 t fired, .
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[[35mlola[0m][.] 81 EFEG EXCL 79/339 8/2000 BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-02 1356879 m, 15563 m/sec, 4975876 t fired, .
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[[35mlola[0m][.] 81 EFEG EXCL 84/339 8/2000 BridgeAndVehicles-PT-V50P50N50-CTLFireability-2024-02 1435427 m, 15709 m/sec, 5259210 t fired, .
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========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BridgeAndVehicles-PT-V50P50N50"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is BridgeAndVehicles-PT-V50P50N50, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r049-tajo-171620400400266"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/BridgeAndVehicles-PT-V50P50N50.tgz
mv BridgeAndVehicles-PT-V50P50N50 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;