About the Execution of LoLA for BridgeAndVehicles-PT-V50P50N10
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 7439.140 | 3600000.00 | 10823136.00 | 332.70 | FFFTT??TTFFFFFTF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/mnt/tpsp/fkordon/mcc2024-input.r049-tajo-171620400400254.qcow2', fmt=qcow2 size=4294967296 backing_file='/mnt/tpsp/fkordon/mcc2024-input.qcow2' backing_fmt='qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
..........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is BridgeAndVehicles-PT-V50P50N10, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r049-tajo-171620400400254
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 3.2M
-rw-r--r-- 1 mcc users 18K Apr 13 02:30 CTLCardinality.txt
-rw-r--r-- 1 mcc users 107K Apr 13 02:30 CTLCardinality.xml
-rw-r--r-- 1 mcc users 129K Apr 13 02:26 CTLFireability.txt
-rw-r--r-- 1 mcc users 529K Apr 13 02:26 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 7.4K Apr 22 14:30 LTLCardinality.txt
-rw-r--r-- 1 mcc users 34K Apr 22 14:30 LTLCardinality.xml
-rw-r--r-- 1 mcc users 77K Apr 22 14:30 LTLFireability.txt
-rw-r--r-- 1 mcc users 227K Apr 22 14:30 LTLFireability.xml
-rw-r--r-- 1 mcc users 44K Apr 13 02:47 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 264K Apr 13 02:47 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 133K Apr 13 02:42 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 514K Apr 13 02:42 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 3.7K Apr 22 14:30 UpperBounds.txt
-rw-r--r-- 1 mcc users 7.7K Apr 22 14:30 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 10 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 1.1M May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00
FORMULA_NAME BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01
FORMULA_NAME BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02
FORMULA_NAME BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03
FORMULA_NAME BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04
FORMULA_NAME BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05
FORMULA_NAME BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06
FORMULA_NAME BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07
FORMULA_NAME BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08
FORMULA_NAME BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09
FORMULA_NAME BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10
FORMULA_NAME BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11
FORMULA_NAME BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12
FORMULA_NAME BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13
FORMULA_NAME BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14
FORMULA_NAME BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15
=== Now, execution of the tool begins
BK_START 1717012303702
FORMULA BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mReachabilityCardinality.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 13 (type CNST) for 12 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 40 (type CNST) for 39 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 25 (type CNST) for 24 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 40 (type CNST) for BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 13 (type CNST) for BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 28 (type CNST) for 27 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 25 (type CNST) for BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 1 (type CNST) for 0 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 4 (type CNST) for 3 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 22 (type CNST) for 21 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 37 (type CNST) for 36 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 22 (type CNST) for BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 1 (type CNST) for BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 4 (type CNST) for BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 10 (type CNST) for 9 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 28 (type CNST) for BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 37 (type CNST) for BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 10 (type CNST) for BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 46 (type CNST) for 45 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 46 (type CNST) for BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 34 (type CNST) for 33 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 34 (type CNST) for BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 43 (type CNST) for 42 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 43 (type CNST) for BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 51 (type EXCL) for 6 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02
[[35mlola[0m][I] time limit : 895 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 49 (type FNDP) for 6 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 50 (type EQUN) for 6 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 53 (type FNDP) for 15 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 51 (type EXCL) for BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 77
[[35mlola[0m][I] fired transitions : 76
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 49 (type FNDP) for BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02 (obsolete)
[[35mlola[0m][W] CANCELED task # 50 (type EQUN) for BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02 (obsolete)
[[35mlola[0m][I] LAUNCH task # 55 (type EXCL) for 15 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05
[[35mlola[0m][I] time limit : 1194 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 54 (type EQUN) for 15 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 49 (type FNDP) for BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] tried executions : 2
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] LAUNCH task # 56 (type FNDP) for 18 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 50 (type EQUN) for BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 54 (type EQUN) for BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 60 (type FNDP) for 30 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 60 (type FNDP) for BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 37
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] LAUNCH task # 57 (type EQUN) for 18 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 57 (type EQUN) for BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 5/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 427 attempts, .
[[35mlola[0m][.] 55 EF EXCL 5/1791 1/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 148115 m, 29623 m/sec, 418400 t fired, .
[[35mlola[0m][.] 56 EF FNDP 5/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 429 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 23 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 10/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 930 attempts, .
[[35mlola[0m][.] 55 EF EXCL 10/1791 2/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 337012 m, 37779 m/sec, 978581 t fired, .
[[35mlola[0m][.] 56 EF FNDP 10/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 865 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 28 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 15/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 1421 attempts, .
[[35mlola[0m][.] 55 EF EXCL 15/1791 3/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 530252 m, 38648 m/sec, 1557000 t fired, .
[[35mlola[0m][.] 56 EF FNDP 15/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 1348 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 33 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 20/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 1900 attempts, .
[[35mlola[0m][.] 55 EF EXCL 20/1791 4/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 727072 m, 39364 m/sec, 2149399 t fired, .
[[35mlola[0m][.] 56 EF FNDP 20/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 1779 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 38 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 25/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 2372 attempts, .
[[35mlola[0m][.] 55 EF EXCL 25/1791 4/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 926346 m, 39854 m/sec, 2746824 t fired, .
[[35mlola[0m][.] 56 EF FNDP 25/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 2255 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 43 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 30/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 2840 attempts, .
[[35mlola[0m][.] 55 EF EXCL 30/1791 5/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 1126696 m, 40070 m/sec, 3350901 t fired, .
[[35mlola[0m][.] 56 EF FNDP 30/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 2729 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 48 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 35/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 3304 attempts, .
[[35mlola[0m][.] 55 EF EXCL 35/1791 6/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 1319201 m, 38501 m/sec, 3921812 t fired, .
[[35mlola[0m][.] 56 EF FNDP 35/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 3203 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 53 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 40/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 3764 attempts, .
[[35mlola[0m][.] 55 EF EXCL 40/1791 7/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 1514361 m, 39032 m/sec, 4504148 t fired, .
[[35mlola[0m][.] 56 EF FNDP 40/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 3673 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 58 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 45/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 4220 attempts, .
[[35mlola[0m][.] 55 EF EXCL 45/1791 8/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 1712705 m, 39668 m/sec, 5096096 t fired, .
[[35mlola[0m][.] 56 EF FNDP 45/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 4146 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 63 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 50/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 4675 attempts, .
[[35mlola[0m][.] 55 EF EXCL 50/1791 9/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 1904909 m, 38440 m/sec, 5662194 t fired, .
[[35mlola[0m][.] 56 EF FNDP 50/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 4616 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 68 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 55/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 5127 attempts, .
[[35mlola[0m][.] 55 EF EXCL 55/1791 10/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 2100434 m, 39105 m/sec, 6246362 t fired, .
[[35mlola[0m][.] 56 EF FNDP 55/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 5085 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 73 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 60/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 5578 attempts, .
[[35mlola[0m][.] 55 EF EXCL 60/1791 10/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 2292445 m, 38402 m/sec, 6816321 t fired, .
[[35mlola[0m][.] 56 EF FNDP 60/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 5554 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 78 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 65/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 6025 attempts, .
[[35mlola[0m][.] 55 EF EXCL 65/1791 11/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 2485592 m, 38629 m/sec, 7392160 t fired, .
[[35mlola[0m][.] 56 EF FNDP 65/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 6023 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 83 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 70/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 6469 attempts, .
[[35mlola[0m][.] 55 EF EXCL 70/1791 12/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 2682855 m, 39452 m/sec, 7982663 t fired, .
[[35mlola[0m][.] 56 EF FNDP 70/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 6492 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 88 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 75/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 6914 attempts, .
[[35mlola[0m][.] 55 EF EXCL 75/1791 13/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 2870258 m, 37480 m/sec, 8537089 t fired, .
[[35mlola[0m][.] 56 EF FNDP 75/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 6959 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 93 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 80/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 7360 attempts, .
[[35mlola[0m][.] 55 EF EXCL 80/1791 14/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 3064052 m, 38758 m/sec, 9115552 t fired, .
[[35mlola[0m][.] 56 EF FNDP 80/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 7426 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 98 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 85/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 7804 attempts, .
[[35mlola[0m][.] 55 EF EXCL 85/1791 15/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 3252126 m, 37614 m/sec, 9674915 t fired, .
[[35mlola[0m][.] 56 EF FNDP 85/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 7893 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 103 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 90/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 8247 attempts, .
[[35mlola[0m][.] 55 EF EXCL 90/1791 15/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 3447062 m, 38987 m/sec, 10261031 t fired, .
[[35mlola[0m][.] 56 EF FNDP 90/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 8359 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 108 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 95/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 8690 attempts, .
[[35mlola[0m][.] 55 EF EXCL 95/1791 16/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 3639160 m, 38419 m/sec, 10835240 t fired, .
[[35mlola[0m][.] 56 EF FNDP 95/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 8826 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 113 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 100/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 9130 attempts, .
[[35mlola[0m][.] 55 EF EXCL 100/1791 17/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 3826551 m, 37478 m/sec, 11391650 t fired, .
[[35mlola[0m][.] 56 EF FNDP 100/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 9247 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 118 secs. Pages in use: 17
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 105/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 9572 attempts, .
[[35mlola[0m][.] 55 EF EXCL 105/1791 18/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 4018603 m, 38410 m/sec, 11970304 t fired, .
[[35mlola[0m][.] 56 EF FNDP 105/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 9704 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 123 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 110/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 10011 attempts, .
[[35mlola[0m][.] 55 EF EXCL 110/1791 19/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 4210083 m, 38296 m/sec, 12544114 t fired, .
[[35mlola[0m][.] 56 EF FNDP 110/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 10169 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 128 secs. Pages in use: 19
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 115/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 10450 attempts, .
[[35mlola[0m][.] 55 EF EXCL 115/1791 20/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 4395596 m, 37102 m/sec, 13094496 t fired, .
[[35mlola[0m][.] 56 EF FNDP 115/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 10634 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 133 secs. Pages in use: 20
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 120/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 10888 attempts, .
[[35mlola[0m][.] 55 EF EXCL 120/1791 20/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 4587112 m, 38303 m/sec, 13674356 t fired, .
[[35mlola[0m][.] 56 EF FNDP 120/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 11098 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 138 secs. Pages in use: 20
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 125/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 11324 attempts, .
[[35mlola[0m][.] 55 EF EXCL 125/1791 21/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 4781492 m, 38876 m/sec, 14262277 t fired, .
[[35mlola[0m][.] 56 EF FNDP 125/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 11562 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 143 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 130/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 11762 attempts, .
[[35mlola[0m][.] 55 EF EXCL 130/1791 22/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 4965772 m, 36856 m/sec, 14812454 t fired, .
[[35mlola[0m][.] 56 EF FNDP 130/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 12026 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 148 secs. Pages in use: 22
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 135/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 12197 attempts, .
[[35mlola[0m][.] 55 EF EXCL 135/1791 23/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 5153217 m, 37489 m/sec, 15375127 t fired, .
[[35mlola[0m][.] 56 EF FNDP 135/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 12490 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 153 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 140/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 12631 attempts, .
[[35mlola[0m][.] 55 EF EXCL 140/1791 24/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 5345993 m, 38555 m/sec, 15958185 t fired, .
[[35mlola[0m][.] 56 EF FNDP 140/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 12953 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 158 secs. Pages in use: 24
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 145/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 13065 attempts, .
[[35mlola[0m][.] 55 EF EXCL 145/1791 25/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 5538597 m, 38520 m/sec, 16541533 t fired, .
[[35mlola[0m][.] 56 EF FNDP 145/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 13416 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 163 secs. Pages in use: 25
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 150/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 13498 attempts, .
[[35mlola[0m][.] 55 EF EXCL 150/1791 25/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 5728769 m, 38034 m/sec, 17109958 t fired, .
[[35mlola[0m][.] 56 EF FNDP 150/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 13879 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 168 secs. Pages in use: 25
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 155/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 13933 attempts, .
[[35mlola[0m][.] 55 EF EXCL 155/1791 26/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 5942227 m, 42691 m/sec, 17750215 t fired, .
[[35mlola[0m][.] 56 EF FNDP 155/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 14344 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 173 secs. Pages in use: 26
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 160/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 14319 attempts, .
[[35mlola[0m][.] 55 EF EXCL 160/1791 27/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 6117335 m, 35021 m/sec, 18274641 t fired, .
[[35mlola[0m][.] 56 EF FNDP 160/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 14769 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 178 secs. Pages in use: 27
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 165/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 14744 attempts, .
[[35mlola[0m][.] 55 EF EXCL 165/1791 28/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 6298834 m, 36299 m/sec, 18818381 t fired, .
[[35mlola[0m][.] 56 EF FNDP 165/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 15222 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 183 secs. Pages in use: 28
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 170/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 15155 attempts, .
[[35mlola[0m][.] 55 EF EXCL 170/1791 29/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 6496471 m, 39527 m/sec, 19419498 t fired, .
[[35mlola[0m][.] 56 EF FNDP 170/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 15666 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 188 secs. Pages in use: 29
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 175/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 15589 attempts, .
[[35mlola[0m][.] 55 EF EXCL 175/1791 29/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 6697786 m, 40263 m/sec, 20024002 t fired, .
[[35mlola[0m][.] 56 EF FNDP 175/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 16129 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 193 secs. Pages in use: 29
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 180/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 16017 attempts, .
[[35mlola[0m][.] 55 EF EXCL 180/1791 30/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 6891254 m, 38693 m/sec, 20601640 t fired, .
[[35mlola[0m][.] 56 EF FNDP 180/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 16593 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 198 secs. Pages in use: 30
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 185/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 16447 attempts, .
[[35mlola[0m][.] 55 EF EXCL 185/1791 31/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 7081183 m, 37985 m/sec, 21174618 t fired, .
[[35mlola[0m][.] 56 EF FNDP 185/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 17057 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 203 secs. Pages in use: 31
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 190/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 16878 attempts, .
[[35mlola[0m][.] 55 EF EXCL 190/1791 32/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 7285161 m, 40795 m/sec, 21792424 t fired, .
[[35mlola[0m][.] 56 EF FNDP 190/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 17520 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 208 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 195/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 17309 attempts, .
[[35mlola[0m][.] 55 EF EXCL 195/1791 33/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 7486228 m, 40213 m/sec, 22400398 t fired, .
[[35mlola[0m][.] 56 EF FNDP 195/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 17984 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 213 secs. Pages in use: 33
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 200/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 17742 attempts, .
[[35mlola[0m][.] 55 EF EXCL 200/1791 34/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 7682711 m, 39296 m/sec, 22985946 t fired, .
[[35mlola[0m][.] 56 EF FNDP 200/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 18447 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 218 secs. Pages in use: 34
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 205/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 18171 attempts, .
[[35mlola[0m][.] 55 EF EXCL 205/1791 35/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 7869727 m, 37403 m/sec, 23544905 t fired, .
[[35mlola[0m][.] 56 EF FNDP 205/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 18910 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 223 secs. Pages in use: 35
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 210/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 18602 attempts, .
[[35mlola[0m][.] 55 EF EXCL 210/1791 35/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 8071612 m, 40377 m/sec, 24153629 t fired, .
[[35mlola[0m][.] 56 EF FNDP 210/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 19374 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 228 secs. Pages in use: 35
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 215/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 19032 attempts, .
[[35mlola[0m][.] 55 EF EXCL 215/1791 36/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 8276862 m, 41050 m/sec, 24781971 t fired, .
[[35mlola[0m][.] 56 EF FNDP 215/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 19838 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 233 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 220/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 19462 attempts, .
[[35mlola[0m][.] 55 EF EXCL 220/1791 37/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 8478114 m, 40250 m/sec, 25381934 t fired, .
[[35mlola[0m][.] 56 EF FNDP 220/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 20301 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 238 secs. Pages in use: 37
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 225/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 19892 attempts, .
[[35mlola[0m][.] 55 EF EXCL 225/1791 38/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 8665930 m, 37563 m/sec, 25941600 t fired, .
[[35mlola[0m][.] 56 EF FNDP 225/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 20765 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 243 secs. Pages in use: 38
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 230/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 20321 attempts, .
[[35mlola[0m][.] 55 EF EXCL 230/1791 39/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 8854033 m, 37620 m/sec, 26506945 t fired, .
[[35mlola[0m][.] 56 EF FNDP 230/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 21230 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 248 secs. Pages in use: 39
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 235/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 20750 attempts, .
[[35mlola[0m][.] 55 EF EXCL 235/1791 40/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 9067947 m, 42782 m/sec, 27159696 t fired, .
[[35mlola[0m][.] 56 EF FNDP 235/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 21692 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 253 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 240/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 21180 attempts, .
[[35mlola[0m][.] 55 EF EXCL 240/1791 41/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 9269989 m, 40408 m/sec, 27768909 t fired, .
[[35mlola[0m][.] 56 EF FNDP 240/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 22155 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 258 secs. Pages in use: 41
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 245/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 21609 attempts, .
[[35mlola[0m][.] 55 EF EXCL 245/1791 41/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 9467961 m, 39594 m/sec, 28359223 t fired, .
[[35mlola[0m][.] 56 EF FNDP 245/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 22619 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 263 secs. Pages in use: 41
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 250/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 22038 attempts, .
[[35mlola[0m][.] 55 EF EXCL 250/1791 42/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 9658972 m, 38202 m/sec, 28931719 t fired, .
[[35mlola[0m][.] 56 EF FNDP 250/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 23083 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 268 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 255/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 22467 attempts, .
[[35mlola[0m][.] 55 EF EXCL 255/1791 43/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 9846537 m, 37513 m/sec, 29490904 t fired, .
[[35mlola[0m][.] 56 EF FNDP 255/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 23545 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 273 secs. Pages in use: 43
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 260/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 22895 attempts, .
[[35mlola[0m][.] 55 EF EXCL 260/1791 44/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 10051545 m, 41001 m/sec, 30118173 t fired, .
[[35mlola[0m][.] 56 EF FNDP 260/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 24009 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 278 secs. Pages in use: 44
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 265/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 23324 attempts, .
[[35mlola[0m][.] 55 EF EXCL 265/1791 45/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 10260947 m, 41880 m/sec, 30744841 t fired, .
[[35mlola[0m][.] 56 EF FNDP 265/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 24473 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 283 secs. Pages in use: 45
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 270/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 23753 attempts, .
[[35mlola[0m][.] 55 EF EXCL 270/1791 46/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 10458699 m, 39550 m/sec, 31339306 t fired, .
[[35mlola[0m][.] 56 EF FNDP 270/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 24936 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 288 secs. Pages in use: 46
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 275/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 24182 attempts, .
[[35mlola[0m][.] 55 EF EXCL 275/1791 47/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 10648014 m, 37863 m/sec, 31907134 t fired, .
[[35mlola[0m][.] 56 EF FNDP 275/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 25399 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 293 secs. Pages in use: 47
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 280/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 24611 attempts, .
[[35mlola[0m][.] 55 EF EXCL 280/1791 47/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 10839243 m, 38245 m/sec, 32478144 t fired, .
[[35mlola[0m][.] 56 EF FNDP 280/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 25863 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 298 secs. Pages in use: 47
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 285/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 25040 attempts, .
[[35mlola[0m][.] 55 EF EXCL 285/1791 48/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 11045163 m, 41184 m/sec, 33108707 t fired, .
[[35mlola[0m][.] 56 EF FNDP 285/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 26326 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 303 secs. Pages in use: 48
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 290/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 25440 attempts, .
[[35mlola[0m][.] 55 EF EXCL 290/1791 49/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 11252775 m, 41522 m/sec, 33732476 t fired, .
[[35mlola[0m][.] 56 EF FNDP 290/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 26792 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 308 secs. Pages in use: 49
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 295/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 25871 attempts, .
[[35mlola[0m][.] 55 EF EXCL 295/1791 50/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 11452970 m, 40039 m/sec, 34332031 t fired, .
[[35mlola[0m][.] 56 EF FNDP 295/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 27255 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 313 secs. Pages in use: 50
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 300/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 26297 attempts, .
[[35mlola[0m][.] 55 EF EXCL 300/1791 51/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 11645641 m, 38534 m/sec, 34910665 t fired, .
[[35mlola[0m][.] 56 EF FNDP 300/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 27693 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 318 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 305/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 26722 attempts, .
[[35mlola[0m][.] 55 EF EXCL 305/1791 52/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 11826601 m, 36192 m/sec, 35449310 t fired, .
[[35mlola[0m][.] 56 EF FNDP 305/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 28156 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 323 secs. Pages in use: 52
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 310/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 27147 attempts, .
[[35mlola[0m][.] 55 EF EXCL 310/1791 53/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 12045993 m, 43878 m/sec, 36122256 t fired, .
[[35mlola[0m][.] 56 EF FNDP 310/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 28619 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 328 secs. Pages in use: 53
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 315/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 27573 attempts, .
[[35mlola[0m][.] 55 EF EXCL 315/1791 53/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 12245899 m, 39981 m/sec, 36722710 t fired, .
[[35mlola[0m][.] 56 EF FNDP 315/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 29083 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 333 secs. Pages in use: 53
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 320/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 28000 attempts, .
[[35mlola[0m][.] 55 EF EXCL 320/1791 54/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 12447511 m, 40322 m/sec, 37325530 t fired, .
[[35mlola[0m][.] 56 EF FNDP 320/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 29547 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 338 secs. Pages in use: 54
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 325/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 28426 attempts, .
[[35mlola[0m][.] 55 EF EXCL 325/1791 55/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 12639151 m, 38328 m/sec, 37898441 t fired, .
[[35mlola[0m][.] 56 EF FNDP 325/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 30009 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 343 secs. Pages in use: 55
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 330/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 28852 attempts, .
[[35mlola[0m][.] 55 EF EXCL 330/1791 56/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 12832344 m, 38638 m/sec, 38480716 t fired, .
[[35mlola[0m][.] 56 EF FNDP 330/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 30473 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 348 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 335/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 29279 attempts, .
[[35mlola[0m][.] 55 EF EXCL 335/1791 57/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 13034153 m, 40361 m/sec, 39086544 t fired, .
[[35mlola[0m][.] 56 EF FNDP 335/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 30937 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 353 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 340/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 29705 attempts, .
[[35mlola[0m][.] 55 EF EXCL 340/1791 58/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 13231811 m, 39531 m/sec, 39692542 t fired, .
[[35mlola[0m][.] 56 EF FNDP 340/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 31401 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 358 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 345/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 30130 attempts, .
[[35mlola[0m][.] 55 EF EXCL 345/1791 59/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 13444397 m, 42517 m/sec, 40326598 t fired, .
[[35mlola[0m][.] 56 EF FNDP 345/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 31864 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 363 secs. Pages in use: 59
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 350/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 30555 attempts, .
[[35mlola[0m][.] 55 EF EXCL 350/1791 59/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 13640560 m, 39232 m/sec, 40913878 t fired, .
[[35mlola[0m][.] 56 EF FNDP 350/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 32328 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 368 secs. Pages in use: 59
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 355/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 30940 attempts, .
[[35mlola[0m][.] 55 EF EXCL 355/1791 60/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 13833360 m, 38560 m/sec, 41493149 t fired, .
[[35mlola[0m][.] 56 EF FNDP 355/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 32791 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 373 secs. Pages in use: 60
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 360/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 31366 attempts, .
[[35mlola[0m][.] 55 EF EXCL 360/1791 61/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 14013801 m, 36088 m/sec, 42028768 t fired, .
[[35mlola[0m][.] 56 EF FNDP 360/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 33254 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 378 secs. Pages in use: 61
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 365/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 31791 attempts, .
[[35mlola[0m][.] 55 EF EXCL 365/1791 62/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 14234105 m, 44060 m/sec, 42699502 t fired, .
[[35mlola[0m][.] 56 EF FNDP 365/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 33716 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 383 secs. Pages in use: 62
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 370/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 32216 attempts, .
[[35mlola[0m][.] 55 EF EXCL 370/1791 63/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 14421550 m, 37489 m/sec, 43267919 t fired, .
[[35mlola[0m][.] 56 EF FNDP 370/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 34179 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 388 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 375/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 32640 attempts, .
[[35mlola[0m][.] 55 EF EXCL 375/1791 64/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 14596641 m, 35018 m/sec, 43789449 t fired, .
[[35mlola[0m][.] 56 EF FNDP 375/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 34641 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 393 secs. Pages in use: 64
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 380/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 33066 attempts, .
[[35mlola[0m][.] 55 EF EXCL 380/1791 64/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 14769278 m, 34527 m/sec, 44299970 t fired, .
[[35mlola[0m][.] 56 EF FNDP 380/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 35104 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 398 secs. Pages in use: 64
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 385/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 33492 attempts, .
[[35mlola[0m][.] 55 EF EXCL 385/1791 65/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 14954681 m, 37080 m/sec, 44843375 t fired, .
[[35mlola[0m][.] 56 EF FNDP 385/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 35567 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 403 secs. Pages in use: 65
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 390/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 33917 attempts, .
[[35mlola[0m][.] 55 EF EXCL 390/1791 66/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 15149686 m, 39001 m/sec, 45444414 t fired, .
[[35mlola[0m][.] 56 EF FNDP 390/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 36030 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 408 secs. Pages in use: 66
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 395/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 34344 attempts, .
[[35mlola[0m][.] 55 EF EXCL 395/1791 67/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 15344389 m, 38940 m/sec, 46041283 t fired, .
[[35mlola[0m][.] 56 EF FNDP 395/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 36492 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 413 secs. Pages in use: 67
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 400/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 34768 attempts, .
[[35mlola[0m][.] 55 EF EXCL 400/1791 68/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 15540499 m, 39222 m/sec, 46640807 t fired, .
[[35mlola[0m][.] 56 EF FNDP 400/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 36954 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 418 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 405/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 35196 attempts, .
[[35mlola[0m][.] 55 EF EXCL 405/1791 68/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 15730267 m, 37953 m/sec, 47214779 t fired, .
[[35mlola[0m][.] 56 EF FNDP 405/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 37416 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 423 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 410/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 35621 attempts, .
[[35mlola[0m][.] 55 EF EXCL 410/1791 69/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 15928836 m, 39713 m/sec, 47827347 t fired, .
[[35mlola[0m][.] 56 EF FNDP 410/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 37880 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 428 secs. Pages in use: 69
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 415/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 36045 attempts, .
[[35mlola[0m][.] 55 EF EXCL 415/1791 70/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 16121263 m, 38485 m/sec, 48411119 t fired, .
[[35mlola[0m][.] 56 EF FNDP 415/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 38344 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 433 secs. Pages in use: 70
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 420/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 36470 attempts, .
[[35mlola[0m][.] 55 EF EXCL 420/1791 71/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 16309251 m, 37597 m/sec, 48977405 t fired, .
[[35mlola[0m][.] 56 EF FNDP 420/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 38808 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 438 secs. Pages in use: 71
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 425/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 36897 attempts, .
[[35mlola[0m][.] 55 EF EXCL 425/1791 72/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 16479426 m, 34035 m/sec, 49481032 t fired, .
[[35mlola[0m][.] 56 EF FNDP 425/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 39271 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 443 secs. Pages in use: 72
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 430/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 37285 attempts, .
[[35mlola[0m][.] 55 EF EXCL 430/1791 72/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 16633497 m, 30814 m/sec, 49937810 t fired, .
[[35mlola[0m][.] 56 EF FNDP 430/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 39685 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 448 secs. Pages in use: 72
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 435/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 37707 attempts, .
[[35mlola[0m][.] 55 EF EXCL 435/1791 73/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 16814177 m, 36136 m/sec, 50477526 t fired, .
[[35mlola[0m][.] 56 EF FNDP 435/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 40136 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 453 secs. Pages in use: 73
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 440/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 38118 attempts, .
[[35mlola[0m][.] 55 EF EXCL 440/1791 74/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 16993194 m, 35803 m/sec, 51028997 t fired, .
[[35mlola[0m][.] 56 EF FNDP 440/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 40561 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 458 secs. Pages in use: 74
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 445/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 38512 attempts, .
[[35mlola[0m][.] 55 EF EXCL 445/1791 75/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 17165642 m, 34489 m/sec, 51554824 t fired, .
[[35mlola[0m][.] 56 EF FNDP 445/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 40990 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 463 secs. Pages in use: 75
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 450/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 38930 attempts, .
[[35mlola[0m][.] 55 EF EXCL 450/1791 75/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 17357228 m, 38317 m/sec, 52145229 t fired, .
[[35mlola[0m][.] 56 EF FNDP 450/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 41435 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 468 secs. Pages in use: 75
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 455/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 39327 attempts, .
[[35mlola[0m][.] 55 EF EXCL 455/1791 76/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 17535751 m, 35704 m/sec, 52694345 t fired, .
[[35mlola[0m][.] 56 EF FNDP 455/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 41852 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 473 secs. Pages in use: 76
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 460/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 39753 attempts, .
[[35mlola[0m][.] 55 EF EXCL 460/1791 77/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 17730458 m, 38941 m/sec, 53288342 t fired, .
[[35mlola[0m][.] 56 EF FNDP 460/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 42315 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 478 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 465/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 40178 attempts, .
[[35mlola[0m][.] 55 EF EXCL 465/1791 78/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 17921490 m, 38206 m/sec, 53872231 t fired, .
[[35mlola[0m][.] 56 EF FNDP 465/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 42779 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 483 secs. Pages in use: 78
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 470/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 40603 attempts, .
[[35mlola[0m][.] 55 EF EXCL 470/1791 79/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 18112833 m, 38268 m/sec, 54454967 t fired, .
[[35mlola[0m][.] 56 EF FNDP 470/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 43242 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 488 secs. Pages in use: 79
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 475/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 41024 attempts, .
[[35mlola[0m][.] 55 EF EXCL 475/1791 79/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 18287679 m, 34969 m/sec, 54976688 t fired, .
[[35mlola[0m][.] 56 EF FNDP 475/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 43701 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 493 secs. Pages in use: 79
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 480/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 41375 attempts, .
[[35mlola[0m][.] 55 EF EXCL 480/1791 80/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 18437320 m, 29928 m/sec, 55419765 t fired, .
[[35mlola[0m][.] 56 EF FNDP 480/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 44106 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 498 secs. Pages in use: 80
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 485/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 41783 attempts, .
[[35mlola[0m][.] 55 EF EXCL 485/1791 81/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 18600932 m, 32722 m/sec, 55908815 t fired, .
[[35mlola[0m][.] 56 EF FNDP 485/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 44547 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 503 secs. Pages in use: 81
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 490/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 42205 attempts, .
[[35mlola[0m][.] 55 EF EXCL 490/1791 82/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 18782227 m, 36259 m/sec, 56453549 t fired, .
[[35mlola[0m][.] 56 EF FNDP 490/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 44991 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 508 secs. Pages in use: 82
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 495/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 42633 attempts, .
[[35mlola[0m][.] 55 EF EXCL 495/1791 82/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 18972782 m, 38111 m/sec, 57039928 t fired, .
[[35mlola[0m][.] 56 EF FNDP 495/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 45453 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 513 secs. Pages in use: 82
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 500/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 43035 attempts, .
[[35mlola[0m][.] 55 EF EXCL 500/1791 83/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 19168110 m, 39065 m/sec, 57640247 t fired, .
[[35mlola[0m][.] 56 EF FNDP 500/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 45915 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 518 secs. Pages in use: 83
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 505/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 43462 attempts, .
[[35mlola[0m][.] 55 EF EXCL 505/1791 84/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 19365698 m, 39517 m/sec, 58249803 t fired, .
[[35mlola[0m][.] 56 EF FNDP 505/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 46378 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 523 secs. Pages in use: 84
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 510/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 43887 attempts, .
[[35mlola[0m][.] 55 EF EXCL 510/1791 85/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 19558303 m, 38521 m/sec, 58839368 t fired, .
[[35mlola[0m][.] 56 EF FNDP 510/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 46841 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 528 secs. Pages in use: 85
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 515/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 44271 attempts, .
[[35mlola[0m][.] 55 EF EXCL 515/1791 86/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 19729395 m, 34218 m/sec, 59363968 t fired, .
[[35mlola[0m][.] 56 EF FNDP 515/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 47248 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 533 secs. Pages in use: 86
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 520/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 44685 attempts, .
[[35mlola[0m][.] 55 EF EXCL 520/1791 87/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 19914267 m, 36974 m/sec, 59931581 t fired, .
[[35mlola[0m][.] 56 EF FNDP 520/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 47691 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 538 secs. Pages in use: 87
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 525/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 45112 attempts, .
[[35mlola[0m][.] 55 EF EXCL 525/1791 87/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 20096765 m, 36499 m/sec, 60487685 t fired, .
[[35mlola[0m][.] 56 EF FNDP 525/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 48131 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 543 secs. Pages in use: 87
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 530/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 45538 attempts, .
[[35mlola[0m][.] 55 EF EXCL 530/1791 88/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 20274927 m, 35632 m/sec, 61022534 t fired, .
[[35mlola[0m][.] 56 EF FNDP 530/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 48594 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 548 secs. Pages in use: 88
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 535/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 45964 attempts, .
[[35mlola[0m][.] 55 EF EXCL 535/1791 89/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 20445749 m, 34164 m/sec, 61532179 t fired, .
[[35mlola[0m][.] 56 EF FNDP 535/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 49057 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 553 secs. Pages in use: 89
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 540/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 46391 attempts, .
[[35mlola[0m][.] 55 EF EXCL 540/1791 90/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 20617747 m, 34399 m/sec, 62045982 t fired, .
[[35mlola[0m][.] 56 EF FNDP 540/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 49519 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 558 secs. Pages in use: 90
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 545/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 46819 attempts, .
[[35mlola[0m][.] 55 EF EXCL 545/1791 90/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 20796858 m, 35822 m/sec, 62578322 t fired, .
[[35mlola[0m][.] 56 EF FNDP 545/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 49982 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 563 secs. Pages in use: 90
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 550/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 47246 attempts, .
[[35mlola[0m][.] 55 EF EXCL 550/1791 91/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 20995097 m, 39647 m/sec, 63195985 t fired, .
[[35mlola[0m][.] 56 EF FNDP 550/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 50446 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 568 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 555/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 47675 attempts, .
[[35mlola[0m][.] 55 EF EXCL 555/1791 92/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 21185156 m, 38011 m/sec, 63778965 t fired, .
[[35mlola[0m][.] 56 EF FNDP 555/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 50909 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 573 secs. Pages in use: 92
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 560/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 48102 attempts, .
[[35mlola[0m][.] 55 EF EXCL 560/1791 93/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 21377305 m, 38429 m/sec, 64365477 t fired, .
[[35mlola[0m][.] 56 EF FNDP 560/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 51372 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 578 secs. Pages in use: 93
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 565/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 48530 attempts, .
[[35mlola[0m][.] 55 EF EXCL 565/1791 94/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 21572294 m, 38997 m/sec, 64970954 t fired, .
[[35mlola[0m][.] 56 EF FNDP 565/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 51834 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 583 secs. Pages in use: 94
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 570/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 48956 attempts, .
[[35mlola[0m][.] 55 EF EXCL 570/1791 95/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 21766256 m, 38792 m/sec, 65567643 t fired, .
[[35mlola[0m][.] 56 EF FNDP 570/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 52297 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 588 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 575/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 49382 attempts, .
[[35mlola[0m][.] 55 EF EXCL 575/1791 95/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 21962337 m, 39216 m/sec, 66168534 t fired, .
[[35mlola[0m][.] 56 EF FNDP 575/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 52759 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 593 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 580/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 49781 attempts, .
[[35mlola[0m][.] 55 EF EXCL 580/1791 96/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 22147738 m, 37080 m/sec, 66729909 t fired, .
[[35mlola[0m][.] 56 EF FNDP 580/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 53223 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 598 secs. Pages in use: 96
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 585/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 50208 attempts, .
[[35mlola[0m][.] 55 EF EXCL 585/1791 97/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 22337876 m, 38027 m/sec, 67311568 t fired, .
[[35mlola[0m][.] 56 EF FNDP 585/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 53686 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 603 secs. Pages in use: 97
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 590/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 50607 attempts, .
[[35mlola[0m][.] 55 EF EXCL 590/1791 98/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 22510285 m, 34481 m/sec, 67829742 t fired, .
[[35mlola[0m][.] 56 EF FNDP 590/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 54150 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 608 secs. Pages in use: 98
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 595/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 51034 attempts, .
[[35mlola[0m][.] 55 EF EXCL 595/1791 98/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 22681685 m, 34280 m/sec, 68340791 t fired, .
[[35mlola[0m][.] 56 EF FNDP 595/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 54612 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 613 secs. Pages in use: 98
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 600/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 51463 attempts, .
[[35mlola[0m][.] 55 EF EXCL 600/1791 99/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 22853327 m, 34328 m/sec, 68858604 t fired, .
[[35mlola[0m][.] 56 EF FNDP 600/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 55075 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 618 secs. Pages in use: 99
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 605/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 51889 attempts, .
[[35mlola[0m][.] 55 EF EXCL 605/1791 100/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 23046754 m, 38685 m/sec, 69446787 t fired, .
[[35mlola[0m][.] 56 EF FNDP 605/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 55538 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 623 secs. Pages in use: 100
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 610/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 52316 attempts, .
[[35mlola[0m][.] 55 EF EXCL 610/1791 101/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 23232041 m, 37057 m/sec, 70015116 t fired, .
[[35mlola[0m][.] 56 EF FNDP 610/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 56001 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 628 secs. Pages in use: 101
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 615/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 52742 attempts, .
[[35mlola[0m][.] 55 EF EXCL 615/1791 102/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 23430532 m, 39698 m/sec, 70630755 t fired, .
[[35mlola[0m][.] 56 EF FNDP 615/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 56464 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 633 secs. Pages in use: 102
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 620/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 53169 attempts, .
[[35mlola[0m][.] 55 EF EXCL 620/1791 103/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 23626346 m, 39162 m/sec, 71235566 t fired, .
[[35mlola[0m][.] 56 EF FNDP 620/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 56927 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 638 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 625/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 53595 attempts, .
[[35mlola[0m][.] 55 EF EXCL 625/1791 103/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 23821050 m, 38940 m/sec, 71836456 t fired, .
[[35mlola[0m][.] 56 EF FNDP 625/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 57389 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 643 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 630/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 54021 attempts, .
[[35mlola[0m][.] 55 EF EXCL 630/1791 104/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 24014317 m, 38653 m/sec, 72432169 t fired, .
[[35mlola[0m][.] 56 EF FNDP 630/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 57854 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 648 secs. Pages in use: 104
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 635/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 54447 attempts, .
[[35mlola[0m][.] 55 EF EXCL 635/1791 105/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 24207901 m, 38716 m/sec, 73028006 t fired, .
[[35mlola[0m][.] 56 EF FNDP 635/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 58316 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 653 secs. Pages in use: 105
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 640/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 54872 attempts, .
[[35mlola[0m][.] 55 EF EXCL 640/1791 106/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 24389988 m, 36417 m/sec, 73578767 t fired, .
[[35mlola[0m][.] 56 EF FNDP 640/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 58781 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 658 secs. Pages in use: 106
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 645/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 55301 attempts, .
[[35mlola[0m][.] 55 EF EXCL 645/1791 107/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 24578583 m, 37719 m/sec, 74153573 t fired, .
[[35mlola[0m][.] 56 EF FNDP 645/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 59244 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 663 secs. Pages in use: 107
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 650/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 55727 attempts, .
[[35mlola[0m][.] 55 EF EXCL 650/1791 107/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 24750824 m, 34448 m/sec, 74672217 t fired, .
[[35mlola[0m][.] 56 EF FNDP 650/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 59708 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 668 secs. Pages in use: 107
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 655/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 56153 attempts, .
[[35mlola[0m][.] 55 EF EXCL 655/1791 108/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 24921449 m, 34125 m/sec, 75181704 t fired, .
[[35mlola[0m][.] 56 EF FNDP 655/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 60170 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 673 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 660/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 56580 attempts, .
[[35mlola[0m][.] 55 EF EXCL 660/1791 109/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 25095756 m, 34861 m/sec, 75707568 t fired, .
[[35mlola[0m][.] 56 EF FNDP 660/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 60634 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 678 secs. Pages in use: 109
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 665/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 57006 attempts, .
[[35mlola[0m][.] 55 EF EXCL 665/1791 110/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 25285107 m, 37870 m/sec, 76284365 t fired, .
[[35mlola[0m][.] 56 EF FNDP 665/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 61097 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 683 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 670/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 57432 attempts, .
[[35mlola[0m][.] 55 EF EXCL 670/1791 111/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 25475784 m, 38135 m/sec, 76872850 t fired, .
[[35mlola[0m][.] 56 EF FNDP 670/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 61561 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 688 secs. Pages in use: 111
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 675/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 57858 attempts, .
[[35mlola[0m][.] 55 EF EXCL 675/1791 111/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 25663150 m, 37473 m/sec, 77450012 t fired, .
[[35mlola[0m][.] 56 EF FNDP 675/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 62024 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 693 secs. Pages in use: 111
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 680/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 58285 attempts, .
[[35mlola[0m][.] 55 EF EXCL 680/1791 112/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 25858418 m, 39053 m/sec, 78049164 t fired, .
[[35mlola[0m][.] 56 EF FNDP 680/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 62487 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 698 secs. Pages in use: 112
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 685/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 58712 attempts, .
[[35mlola[0m][.] 55 EF EXCL 685/1791 113/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 26052136 m, 38743 m/sec, 78649457 t fired, .
[[35mlola[0m][.] 56 EF FNDP 685/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 62949 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 703 secs. Pages in use: 113
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 690/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 59137 attempts, .
[[35mlola[0m][.] 55 EF EXCL 690/1791 114/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 26244877 m, 38548 m/sec, 79244362 t fired, .
[[35mlola[0m][.] 56 EF FNDP 690/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 63412 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 708 secs. Pages in use: 114
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 695/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 59563 attempts, .
[[35mlola[0m][.] 55 EF EXCL 695/1791 115/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 26437104 m, 38445 m/sec, 79834916 t fired, .
[[35mlola[0m][.] 56 EF FNDP 695/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 63875 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 713 secs. Pages in use: 115
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 700/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 59987 attempts, .
[[35mlola[0m][.] 55 EF EXCL 700/1791 115/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 26624793 m, 37537 m/sec, 80412907 t fired, .
[[35mlola[0m][.] 56 EF FNDP 700/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 64338 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 718 secs. Pages in use: 115
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 705/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 60415 attempts, .
[[35mlola[0m][.] 55 EF EXCL 705/1791 116/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 26820753 m, 39192 m/sec, 81016187 t fired, .
[[35mlola[0m][.] 56 EF FNDP 705/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 64800 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 723 secs. Pages in use: 116
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 710/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 60840 attempts, .
[[35mlola[0m][.] 55 EF EXCL 710/1791 117/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 26996742 m, 35197 m/sec, 81547641 t fired, .
[[35mlola[0m][.] 56 EF FNDP 710/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 65263 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 728 secs. Pages in use: 117
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 715/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 61266 attempts, .
[[35mlola[0m][.] 55 EF EXCL 715/1791 118/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 27168581 m, 34367 m/sec, 82063988 t fired, .
[[35mlola[0m][.] 56 EF FNDP 715/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 65727 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 733 secs. Pages in use: 118
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 720/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 61692 attempts, .
[[35mlola[0m][.] 55 EF EXCL 720/1791 119/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 27339695 m, 34222 m/sec, 82579536 t fired, .
[[35mlola[0m][.] 56 EF FNDP 720/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 66189 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 738 secs. Pages in use: 119
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 725/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 62118 attempts, .
[[35mlola[0m][.] 55 EF EXCL 725/1791 119/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 27512047 m, 34470 m/sec, 83096686 t fired, .
[[35mlola[0m][.] 56 EF FNDP 725/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 66652 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 743 secs. Pages in use: 119
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 730/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 62545 attempts, .
[[35mlola[0m][.] 55 EF EXCL 730/1791 120/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 27704325 m, 38455 m/sec, 83687605 t fired, .
[[35mlola[0m][.] 56 EF FNDP 730/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 67116 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 748 secs. Pages in use: 120
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 735/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 62970 attempts, .
[[35mlola[0m][.] 55 EF EXCL 735/1791 121/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 27890453 m, 37225 m/sec, 84261084 t fired, .
[[35mlola[0m][.] 56 EF FNDP 735/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 67580 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 753 secs. Pages in use: 121
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 740/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 63397 attempts, .
[[35mlola[0m][.] 55 EF EXCL 740/1791 122/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 28086574 m, 39224 m/sec, 84867674 t fired, .
[[35mlola[0m][.] 56 EF FNDP 740/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 68043 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 758 secs. Pages in use: 122
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 745/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 63823 attempts, .
[[35mlola[0m][.] 55 EF EXCL 745/1791 123/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 28279087 m, 38502 m/sec, 85465808 t fired, .
[[35mlola[0m][.] 56 EF FNDP 745/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 68507 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 763 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 750/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 64249 attempts, .
[[35mlola[0m][.] 55 EF EXCL 750/1791 123/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 28471731 m, 38528 m/sec, 86061222 t fired, .
[[35mlola[0m][.] 56 EF FNDP 750/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 68969 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 768 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 755/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 64675 attempts, .
[[35mlola[0m][.] 55 EF EXCL 755/1791 124/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 28664018 m, 38457 m/sec, 86653712 t fired, .
[[35mlola[0m][.] 56 EF FNDP 755/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 69432 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 773 secs. Pages in use: 124
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 760/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 65102 attempts, .
[[35mlola[0m][.] 55 EF EXCL 760/1791 125/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 28855657 m, 38327 m/sec, 87240851 t fired, .
[[35mlola[0m][.] 56 EF FNDP 760/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 69895 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 778 secs. Pages in use: 125
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 765/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 65528 attempts, .
[[35mlola[0m][.] 55 EF EXCL 765/1791 126/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 29044225 m, 37713 m/sec, 87826623 t fired, .
[[35mlola[0m][.] 56 EF FNDP 765/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 70359 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 783 secs. Pages in use: 126
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 770/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 65955 attempts, .
[[35mlola[0m][.] 55 EF EXCL 770/1791 127/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 29239486 m, 39052 m/sec, 88427994 t fired, .
[[35mlola[0m][.] 56 EF FNDP 770/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 70820 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 788 secs. Pages in use: 127
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 775/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 66382 attempts, .
[[35mlola[0m][.] 55 EF EXCL 775/1791 127/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 29416958 m, 35494 m/sec, 88964610 t fired, .
[[35mlola[0m][.] 56 EF FNDP 775/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 71283 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 793 secs. Pages in use: 127
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 780/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 66807 attempts, .
[[35mlola[0m][.] 55 EF EXCL 780/1791 128/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 29588924 m, 34393 m/sec, 89483189 t fired, .
[[35mlola[0m][.] 56 EF FNDP 780/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 71746 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 798 secs. Pages in use: 128
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 785/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 67233 attempts, .
[[35mlola[0m][.] 55 EF EXCL 785/1791 129/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 29758861 m, 33987 m/sec, 89993346 t fired, .
[[35mlola[0m][.] 56 EF FNDP 785/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 72209 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 803 secs. Pages in use: 129
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 790/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 67660 attempts, .
[[35mlola[0m][.] 55 EF EXCL 790/1791 130/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 29932559 m, 34739 m/sec, 90518587 t fired, .
[[35mlola[0m][.] 56 EF FNDP 790/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 72670 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 808 secs. Pages in use: 130
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 795/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 68088 attempts, .
[[35mlola[0m][.] 55 EF EXCL 795/1791 131/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 30119690 m, 37426 m/sec, 91088497 t fired, .
[[35mlola[0m][.] 56 EF FNDP 795/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 73133 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 813 secs. Pages in use: 131
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 800/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 68515 attempts, .
[[35mlola[0m][.] 55 EF EXCL 800/1791 131/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 30313898 m, 38841 m/sec, 91694560 t fired, .
[[35mlola[0m][.] 56 EF FNDP 800/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 73597 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 818 secs. Pages in use: 131
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 805/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 68942 attempts, .
[[35mlola[0m][.] 55 EF EXCL 805/1791 132/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 30506032 m, 38426 m/sec, 92286673 t fired, .
[[35mlola[0m][.] 56 EF FNDP 805/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 74059 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 823 secs. Pages in use: 132
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 810/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 69368 attempts, .
[[35mlola[0m][.] 55 EF EXCL 810/1791 133/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 30697317 m, 38257 m/sec, 92878442 t fired, .
[[35mlola[0m][.] 56 EF FNDP 810/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 74523 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 828 secs. Pages in use: 133
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 815/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 69793 attempts, .
[[35mlola[0m][.] 55 EF EXCL 815/1791 134/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 30890102 m, 38557 m/sec, 93474798 t fired, .
[[35mlola[0m][.] 56 EF FNDP 815/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 74985 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 833 secs. Pages in use: 134
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 820/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 70219 attempts, .
[[35mlola[0m][.] 55 EF EXCL 820/1791 135/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 31084355 m, 38850 m/sec, 94075606 t fired, .
[[35mlola[0m][.] 56 EF FNDP 820/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 75448 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 838 secs. Pages in use: 135
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 825/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 70646 attempts, .
[[35mlola[0m][.] 55 EF EXCL 825/1791 135/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 31276773 m, 38483 m/sec, 94674446 t fired, .
[[35mlola[0m][.] 56 EF FNDP 825/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 75911 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 843 secs. Pages in use: 135
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 830/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 71071 attempts, .
[[35mlola[0m][.] 55 EF EXCL 830/1791 136/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 31468832 m, 38411 m/sec, 95267642 t fired, .
[[35mlola[0m][.] 56 EF FNDP 830/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 76375 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 848 secs. Pages in use: 136
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 835/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 71495 attempts, .
[[35mlola[0m][.] 55 EF EXCL 835/1791 137/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 31640305 m, 34294 m/sec, 95782212 t fired, .
[[35mlola[0m][.] 56 EF FNDP 835/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 76838 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 853 secs. Pages in use: 137
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 840/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 71922 attempts, .
[[35mlola[0m][.] 55 EF EXCL 840/1791 138/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 31844096 m, 40758 m/sec, 96413977 t fired, .
[[35mlola[0m][.] 56 EF FNDP 840/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 77301 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 858 secs. Pages in use: 138
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 845/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 72347 attempts, .
[[35mlola[0m][.] 55 EF EXCL 845/1791 139/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 32015880 m, 34356 m/sec, 96936593 t fired, .
[[35mlola[0m][.] 56 EF FNDP 845/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 77764 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 863 secs. Pages in use: 139
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 850/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 72772 attempts, .
[[35mlola[0m][.] 55 EF EXCL 850/1791 139/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 32187677 m, 34359 m/sec, 97456404 t fired, .
[[35mlola[0m][.] 56 EF FNDP 850/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 78226 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 868 secs. Pages in use: 139
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 855/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 73197 attempts, .
[[35mlola[0m][.] 55 EF EXCL 855/1791 140/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 32359381 m, 34340 m/sec, 97974832 t fired, .
[[35mlola[0m][.] 56 EF FNDP 855/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 78689 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 873 secs. Pages in use: 140
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 860/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 73623 attempts, .
[[35mlola[0m][.] 55 EF EXCL 860/1791 141/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 32530757 m, 34275 m/sec, 98493696 t fired, .
[[35mlola[0m][.] 56 EF FNDP 860/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 79151 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 878 secs. Pages in use: 141
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 865/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 74048 attempts, .
[[35mlola[0m][.] 55 EF EXCL 865/1791 142/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 32723850 m, 38618 m/sec, 99083707 t fired, .
[[35mlola[0m][.] 56 EF FNDP 865/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 79613 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 883 secs. Pages in use: 142
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 870/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 74475 attempts, .
[[35mlola[0m][.] 55 EF EXCL 870/1791 143/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 32917112 m, 38652 m/sec, 99683351 t fired, .
[[35mlola[0m][.] 56 EF FNDP 870/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 80076 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 888 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 875/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 74901 attempts, .
[[35mlola[0m][.] 55 EF EXCL 875/1791 143/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 33108393 m, 38256 m/sec, 100275928 t fired, .
[[35mlola[0m][.] 56 EF FNDP 875/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 80540 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 893 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 880/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 75326 attempts, .
[[35mlola[0m][.] 55 EF EXCL 880/1791 144/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 33300166 m, 38354 m/sec, 100870715 t fired, .
[[35mlola[0m][.] 56 EF FNDP 880/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 81002 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 898 secs. Pages in use: 144
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 885/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 75753 attempts, .
[[35mlola[0m][.] 55 EF EXCL 885/1791 145/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 33494252 m, 38817 m/sec, 101471590 t fired, .
[[35mlola[0m][.] 56 EF FNDP 885/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 81466 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 903 secs. Pages in use: 145
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 890/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 76179 attempts, .
[[35mlola[0m][.] 55 EF EXCL 890/1791 146/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 33685973 m, 38344 m/sec, 102068348 t fired, .
[[35mlola[0m][.] 56 EF FNDP 890/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 81929 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 908 secs. Pages in use: 146
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 895/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 76605 attempts, .
[[35mlola[0m][.] 55 EF EXCL 895/1791 147/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 33877874 m, 38380 m/sec, 102662829 t fired, .
[[35mlola[0m][.] 56 EF FNDP 895/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 82391 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 913 secs. Pages in use: 147
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 900/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 77031 attempts, .
[[35mlola[0m][.] 55 EF EXCL 900/1791 147/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 34064492 m, 37323 m/sec, 103238700 t fired, .
[[35mlola[0m][.] 56 EF FNDP 900/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 82854 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 918 secs. Pages in use: 147
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 905/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 77457 attempts, .
[[35mlola[0m][.] 55 EF EXCL 905/1791 148/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 34248524 m, 36806 m/sec, 103799821 t fired, .
[[35mlola[0m][.] 56 EF FNDP 905/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 83317 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 923 secs. Pages in use: 148
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 910/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 77883 attempts, .
[[35mlola[0m][.] 55 EF EXCL 910/1791 149/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 34443933 m, 39081 m/sec, 104407308 t fired, .
[[35mlola[0m][.] 56 EF FNDP 910/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 83779 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 928 secs. Pages in use: 149
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 915/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 78308 attempts, .
[[35mlola[0m][.] 55 EF EXCL 915/1791 150/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 34621550 m, 35523 m/sec, 104944907 t fired, .
[[35mlola[0m][.] 56 EF FNDP 915/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 84240 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 933 secs. Pages in use: 150
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 920/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 78735 attempts, .
[[35mlola[0m][.] 55 EF EXCL 920/1791 151/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 34793177 m, 34325 m/sec, 105465048 t fired, .
[[35mlola[0m][.] 56 EF FNDP 920/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 84702 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 938 secs. Pages in use: 151
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 925/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 79162 attempts, .
[[35mlola[0m][.] 55 EF EXCL 925/1791 151/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 34963599 m, 34084 m/sec, 105980789 t fired, .
[[35mlola[0m][.] 56 EF FNDP 925/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 85165 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 943 secs. Pages in use: 151
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 930/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 79590 attempts, .
[[35mlola[0m][.] 55 EF EXCL 930/1791 152/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 35137049 m, 34690 m/sec, 106508097 t fired, .
[[35mlola[0m][.] 56 EF FNDP 930/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 85629 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 948 secs. Pages in use: 152
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 935/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 80017 attempts, .
[[35mlola[0m][.] 55 EF EXCL 935/1791 153/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 35350811 m, 42752 m/sec, 107153218 t fired, .
[[35mlola[0m][.] 56 EF FNDP 935/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 86093 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 953 secs. Pages in use: 153
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 940/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 80443 attempts, .
[[35mlola[0m][.] 55 EF EXCL 940/1791 154/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 35565884 m, 43014 m/sec, 107805572 t fired, .
[[35mlola[0m][.] 56 EF FNDP 940/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 86556 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 958 secs. Pages in use: 154
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 945/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 80869 attempts, .
[[35mlola[0m][.] 55 EF EXCL 945/1791 155/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 35776933 m, 42209 m/sec, 108448517 t fired, .
[[35mlola[0m][.] 56 EF FNDP 945/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 87019 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 963 secs. Pages in use: 155
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 950/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 81295 attempts, .
[[35mlola[0m][.] 55 EF EXCL 950/1791 156/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 36007191 m, 46051 m/sec, 109150994 t fired, .
[[35mlola[0m][.] 56 EF FNDP 950/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 87482 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 968 secs. Pages in use: 156
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 955/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 81722 attempts, .
[[35mlola[0m][.] 55 EF EXCL 955/1791 157/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 36203369 m, 39235 m/sec, 109748968 t fired, .
[[35mlola[0m][.] 56 EF FNDP 955/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 87945 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 973 secs. Pages in use: 157
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 960/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 82148 attempts, .
[[35mlola[0m][.] 55 EF EXCL 960/1791 157/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 36389415 m, 37209 m/sec, 110308132 t fired, .
[[35mlola[0m][.] 56 EF FNDP 960/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 88409 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 978 secs. Pages in use: 157
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 965/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 82572 attempts, .
[[35mlola[0m][.] 55 EF EXCL 965/1791 158/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 36574710 m, 37059 m/sec, 110869468 t fired, .
[[35mlola[0m][.] 56 EF FNDP 965/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 88873 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 983 secs. Pages in use: 158
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 970/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 82997 attempts, .
[[35mlola[0m][.] 55 EF EXCL 970/1791 159/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 36760531 m, 37164 m/sec, 111433039 t fired, .
[[35mlola[0m][.] 56 EF FNDP 970/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 89335 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 988 secs. Pages in use: 159
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 975/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 83422 attempts, .
[[35mlola[0m][.] 55 EF EXCL 975/1791 160/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 36947685 m, 37430 m/sec, 111998459 t fired, .
[[35mlola[0m][.] 56 EF FNDP 975/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 89798 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 993 secs. Pages in use: 160
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 980/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 83848 attempts, .
[[35mlola[0m][.] 55 EF EXCL 980/1791 161/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 37129106 m, 36284 m/sec, 112551774 t fired, .
[[35mlola[0m][.] 56 EF FNDP 980/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 90260 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 998 secs. Pages in use: 161
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 985/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 84275 attempts, .
[[35mlola[0m][.] 55 EF EXCL 985/1791 161/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 37306409 m, 35460 m/sec, 113079652 t fired, .
[[35mlola[0m][.] 56 EF FNDP 985/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 90723 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1003 secs. Pages in use: 161
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 990/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 84701 attempts, .
[[35mlola[0m][.] 55 EF EXCL 990/1791 162/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 37480845 m, 34887 m/sec, 113614443 t fired, .
[[35mlola[0m][.] 56 EF FNDP 990/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 91186 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1008 secs. Pages in use: 162
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 995/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 85128 attempts, .
[[35mlola[0m][.] 55 EF EXCL 995/1791 163/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 37667461 m, 37323 m/sec, 114188119 t fired, .
[[35mlola[0m][.] 56 EF FNDP 995/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 91651 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1013 secs. Pages in use: 163
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1000/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 85555 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1000/1791 164/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 37859604 m, 38428 m/sec, 114760920 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1000/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 92114 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1018 secs. Pages in use: 164
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1005/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 85982 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1005/1791 165/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 38077423 m, 43563 m/sec, 115422715 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1005/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 92578 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1023 secs. Pages in use: 165
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1010/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 86409 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1010/1791 166/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 38288764 m, 42268 m/sec, 116070321 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1010/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 93040 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1028 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1015/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 86837 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1015/1791 167/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 38507463 m, 43739 m/sec, 116732596 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1015/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 93504 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1033 secs. Pages in use: 167
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1020/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 87262 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1020/1791 167/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 38704290 m, 39365 m/sec, 117340792 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1020/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 93966 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1038 secs. Pages in use: 167
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1025/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 87688 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1025/1791 168/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 38888508 m, 36843 m/sec, 117909985 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1025/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 94412 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1043 secs. Pages in use: 168
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1030/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 88113 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1030/1791 169/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 39100137 m, 42325 m/sec, 118565360 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1030/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 94876 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1048 secs. Pages in use: 169
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1035/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 88538 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1035/1791 170/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 39287092 m, 37391 m/sec, 119127356 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1035/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 95339 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1053 secs. Pages in use: 170
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1040/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 88964 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1040/1791 171/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 39471042 m, 36790 m/sec, 119683847 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1040/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 95801 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1058 secs. Pages in use: 171
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1045/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 89390 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1045/1791 172/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 39653521 m, 36495 m/sec, 120232403 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1045/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 96264 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1063 secs. Pages in use: 172
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1050/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 89816 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1050/1791 172/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 39833457 m, 35987 m/sec, 120767673 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1050/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 96727 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1068 secs. Pages in use: 172
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1055/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 90244 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1055/1791 173/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 40008623 m, 35033 m/sec, 121302524 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1055/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 97191 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1073 secs. Pages in use: 173
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1060/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 90669 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1060/1791 174/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 40194069 m, 37089 m/sec, 121872270 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1060/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 97653 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1078 secs. Pages in use: 174
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1065/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 91097 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1065/1791 175/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 40382400 m, 37666 m/sec, 122443580 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1065/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 98116 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1083 secs. Pages in use: 175
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1070/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 91523 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1070/1791 175/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 40559269 m, 35373 m/sec, 122977614 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1070/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 98579 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1088 secs. Pages in use: 175
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1075/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 91948 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1075/1791 176/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 40730336 m, 34213 m/sec, 123499613 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1075/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 99042 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1093 secs. Pages in use: 176
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1080/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 92365 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1080/1791 177/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 40940237 m, 41980 m/sec, 124126694 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1080/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 99496 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1098 secs. Pages in use: 177
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1085/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 92760 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1085/1791 178/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 41135430 m, 39038 m/sec, 124721478 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1085/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 99914 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1103 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1090/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 93160 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1090/1791 179/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 41330352 m, 38984 m/sec, 125317036 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1090/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 100350 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1108 secs. Pages in use: 179
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1095/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 93580 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1095/1791 180/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 41542900 m, 42509 m/sec, 125964482 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1095/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 100796 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1113 secs. Pages in use: 180
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1100/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 94006 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1100/1791 180/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 41738089 m, 39037 m/sec, 126567180 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1100/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 101258 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1118 secs. Pages in use: 180
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1105/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 94431 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1105/1791 181/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 41920401 m, 36462 m/sec, 127131723 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1105/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 101720 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1123 secs. Pages in use: 181
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1110/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 94845 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1110/1791 182/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 42126739 m, 41267 m/sec, 127769129 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1110/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 102170 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1128 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1115/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 95249 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1115/1791 183/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 42295484 m, 33749 m/sec, 128271571 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1115/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 102593 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1133 secs. Pages in use: 183
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1120/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 95653 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1120/1791 184/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 42464441 m, 33791 m/sec, 128781249 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1120/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 103032 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1138 secs. Pages in use: 184
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1125/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 96079 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1125/1791 184/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 42641202 m, 35352 m/sec, 129316795 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1125/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 103475 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1143 secs. Pages in use: 184
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1130/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 96504 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1130/1791 185/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 42826294 m, 37018 m/sec, 129881563 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1130/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 103938 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1148 secs. Pages in use: 185
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1135/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 96930 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1135/1791 186/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 43013941 m, 37529 m/sec, 130449986 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1135/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 104401 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1153 secs. Pages in use: 186
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1140/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 97356 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1140/1791 187/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 43195255 m, 36262 m/sec, 131000821 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1140/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 104863 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1158 secs. Pages in use: 187
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1145/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 97780 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1145/1791 187/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 43364240 m, 33797 m/sec, 131506421 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1145/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 105326 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1163 secs. Pages in use: 187
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1150/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 98204 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1150/1791 188/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 43549553 m, 37062 m/sec, 132075512 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1150/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 105789 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1168 secs. Pages in use: 188
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1155/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 98630 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1155/1791 189/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 43738924 m, 37874 m/sec, 132651614 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1155/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 106252 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1173 secs. Pages in use: 189
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1160/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 99055 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1160/1791 190/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 43909692 m, 34153 m/sec, 133167275 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1160/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 106714 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1178 secs. Pages in use: 190
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1165/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 99480 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1165/1791 191/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 44131409 m, 44343 m/sec, 133832202 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1165/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 107175 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1183 secs. Pages in use: 191
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1170/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 99905 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1170/1791 192/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 44345004 m, 42719 m/sec, 134485781 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1170/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 107637 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1188 secs. Pages in use: 192
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1175/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 100331 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1175/1791 193/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 44555384 m, 42076 m/sec, 135123381 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1175/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 108100 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1193 secs. Pages in use: 193
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1180/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 100757 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1180/1791 194/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 44771135 m, 43150 m/sec, 135787154 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1180/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 108562 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1198 secs. Pages in use: 194
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1185/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 101182 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1185/1791 194/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 44958793 m, 37531 m/sec, 136364870 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1185/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 109024 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1203 secs. Pages in use: 194
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1190/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 101606 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1190/1791 195/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 45146400 m, 37521 m/sec, 136952053 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1190/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 109487 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1208 secs. Pages in use: 195
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1195/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 102029 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1195/1791 196/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 45353796 m, 41479 m/sec, 137583550 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1195/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 109950 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1213 secs. Pages in use: 196
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1200/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 102454 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1200/1791 197/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 45540590 m, 37358 m/sec, 138146588 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1200/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 110412 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1218 secs. Pages in use: 197
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1205/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 102878 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1205/1791 198/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 45726626 m, 37207 m/sec, 138709383 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1205/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 110875 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1223 secs. Pages in use: 198
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1210/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 103303 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1210/1791 198/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 45907943 m, 36263 m/sec, 139252072 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1210/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 111338 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1228 secs. Pages in use: 198
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1215/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 103729 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1215/1791 199/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 46081986 m, 34808 m/sec, 139774380 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1215/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 111801 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1233 secs. Pages in use: 199
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1220/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 104154 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1220/1791 200/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 46266458 m, 36894 m/sec, 140339192 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1220/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 112264 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1238 secs. Pages in use: 200
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1225/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 104579 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1225/1791 201/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 46454831 m, 37674 m/sec, 140912971 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1225/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 112729 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1243 secs. Pages in use: 201
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1230/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 105006 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1230/1791 202/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 46634684 m, 35970 m/sec, 141456793 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1230/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 113191 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1248 secs. Pages in use: 202
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1235/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 105431 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1235/1791 202/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 46803971 m, 33857 m/sec, 141967807 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1235/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 113654 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1253 secs. Pages in use: 202
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1240/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 105856 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1240/1791 203/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 46993221 m, 37850 m/sec, 142551350 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1240/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 114115 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1258 secs. Pages in use: 203
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1245/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 106280 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1245/1791 204/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 47178105 m, 36976 m/sec, 143102347 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1245/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 114578 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1263 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1250/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 106706 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1250/1791 205/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 47395661 m, 43511 m/sec, 143761449 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1250/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 115040 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1268 secs. Pages in use: 205
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1255/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 107131 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1255/1791 206/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 47609306 m, 42729 m/sec, 144414273 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1255/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 115504 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1273 secs. Pages in use: 206
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1260/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 107556 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1260/1791 207/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 47821025 m, 42343 m/sec, 145055190 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1260/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 115968 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1278 secs. Pages in use: 207
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1265/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 107953 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1265/1791 208/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 48035211 m, 42837 m/sec, 145713254 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1265/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 116433 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1283 secs. Pages in use: 208
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1270/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 108377 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1270/1791 208/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 48224796 m, 37917 m/sec, 146296670 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1270/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 116897 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1288 secs. Pages in use: 208
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1275/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 108802 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1275/1791 209/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 48412894 m, 37619 m/sec, 146883823 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1275/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 117359 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1293 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1280/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 109225 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1280/1791 210/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 48621021 m, 41625 m/sec, 147520900 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1280/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 117822 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1298 secs. Pages in use: 210
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1285/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 109648 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1285/1791 211/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 48809591 m, 37714 m/sec, 148089466 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1285/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 118284 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1303 secs. Pages in use: 211
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1290/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 110072 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1290/1791 212/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 48992035 m, 36488 m/sec, 148637399 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1290/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 118749 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1308 secs. Pages in use: 212
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1295/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 110496 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1295/1791 212/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 49170563 m, 35705 m/sec, 149167389 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1295/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 119211 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1313 secs. Pages in use: 212
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1300/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 110897 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1300/1791 213/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 49350040 m, 35895 m/sec, 149716367 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1300/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 119674 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1318 secs. Pages in use: 213
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1305/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 111322 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1305/1791 214/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 49538131 m, 37618 m/sec, 150291271 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1305/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 120138 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1323 secs. Pages in use: 214
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1310/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 111736 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1310/1791 215/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 49717591 m, 35892 m/sec, 150836453 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1310/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 120586 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1328 secs. Pages in use: 215
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1315/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 112145 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1315/1791 215/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 49868589 m, 30199 m/sec, 151286669 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1315/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 121004 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1333 secs. Pages in use: 215
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1320/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 112552 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1320/1791 216/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 50047129 m, 35708 m/sec, 151837521 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1320/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 121436 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1338 secs. Pages in use: 216
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1325/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 112976 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1325/1791 217/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 50219678 m, 34509 m/sec, 152357639 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1325/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 121881 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1343 secs. Pages in use: 217
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1330/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 113402 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1330/1791 218/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 50390713 m, 34207 m/sec, 152879401 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1330/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 122345 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1348 secs. Pages in use: 218
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1335/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 113828 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1335/1791 219/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 50599245 m, 41706 m/sec, 153505407 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1335/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 122807 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1353 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1340/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 114254 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1340/1791 219/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 50813093 m, 42769 m/sec, 154154586 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1340/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 123269 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1358 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1345/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 114660 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1345/1791 220/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 51016724 m, 40726 m/sec, 154777656 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1345/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 123708 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1363 secs. Pages in use: 220
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1350/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 115070 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1350/1791 221/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 51215766 m, 39808 m/sec, 155378425 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1350/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 124141 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1368 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1355/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 115470 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1355/1791 222/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 51406969 m, 38240 m/sec, 155966429 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1355/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 124565 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1373 secs. Pages in use: 222
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1360/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 115896 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1360/1791 223/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 51594358 m, 37477 m/sec, 156543916 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1360/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 125022 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1378 secs. Pages in use: 223
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1365/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 116287 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1365/1791 224/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 51763131 m, 33754 m/sec, 157069475 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1365/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 125439 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1383 secs. Pages in use: 224
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1370/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 116712 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1370/1791 224/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 51965542 m, 40482 m/sec, 157691530 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1370/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 125883 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1388 secs. Pages in use: 224
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1375/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 117107 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1375/1791 225/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 52127195 m, 32330 m/sec, 158168617 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1375/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 126297 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1393 secs. Pages in use: 225
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1380/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 117517 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1380/1791 226/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 52300357 m, 34632 m/sec, 158694373 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1380/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 126742 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1398 secs. Pages in use: 226
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1385/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 117919 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1385/1791 227/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 52472415 m, 34411 m/sec, 159220579 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1385/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 127162 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1403 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1390/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 118318 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1390/1791 227/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 52646037 m, 34724 m/sec, 159747611 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1390/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 127590 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1408 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1395/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 118741 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1395/1791 228/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 52819873 m, 34767 m/sec, 160259984 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1395/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 128047 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1413 secs. Pages in use: 228
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1400/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 119167 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1400/1791 229/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 52997759 m, 35577 m/sec, 160807848 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1400/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 128508 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1418 secs. Pages in use: 229
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1405/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 119591 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1405/1791 230/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 53187761 m, 38000 m/sec, 161385704 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1405/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 128972 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1423 secs. Pages in use: 230
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1410/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 120015 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1410/1791 230/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 53363623 m, 35172 m/sec, 161913548 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1410/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 129435 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1428 secs. Pages in use: 230
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1415/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 120440 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1415/1791 231/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 53536843 m, 34644 m/sec, 162445115 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1415/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 129898 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1433 secs. Pages in use: 231
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1420/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 120862 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1420/1791 232/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 53727974 m, 38226 m/sec, 163027325 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1420/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 130361 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1438 secs. Pages in use: 232
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1425/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 121287 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1425/1791 233/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 53888282 m, 32061 m/sec, 163509612 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1425/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 130823 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1443 secs. Pages in use: 233
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1430/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 121711 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1430/1791 234/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 54113415 m, 45026 m/sec, 164189363 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1430/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 131285 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1448 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1435/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 122137 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1435/1791 235/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 54327939 m, 42904 m/sec, 164842009 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1435/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 131747 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1453 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1440/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 122561 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1440/1791 235/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 54534126 m, 41237 m/sec, 165468922 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1440/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 132208 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1458 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1445/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 122986 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1445/1791 236/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 54761269 m, 45428 m/sec, 166163003 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1445/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 132670 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1463 secs. Pages in use: 236
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1450/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 123411 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1450/1791 237/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 54952637 m, 38273 m/sec, 166741850 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1450/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 133133 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1468 secs. Pages in use: 237
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1455/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 123835 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1455/1791 238/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 55130924 m, 35657 m/sec, 167301587 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1455/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 133596 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1473 secs. Pages in use: 238
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1460/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 124259 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1460/1791 239/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 55338795 m, 41574 m/sec, 167948270 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1460/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 134057 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1478 secs. Pages in use: 239
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1465/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 124683 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1465/1791 240/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 55535913 m, 39423 m/sec, 168546950 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1465/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 134520 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1483 secs. Pages in use: 240
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1470/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 125109 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1470/1791 241/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 55725629 m, 37943 m/sec, 169118681 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1470/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 134984 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1488 secs. Pages in use: 241
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1475/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 125534 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1475/1791 241/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 55910431 m, 36960 m/sec, 169676245 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1475/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 135446 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1493 secs. Pages in use: 241
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1480/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 125960 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1480/1791 242/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 56085328 m, 34979 m/sec, 170194809 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1480/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 135907 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1498 secs. Pages in use: 242
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1485/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 126387 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1485/1791 243/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 56268041 m, 36542 m/sec, 170754331 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1485/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 136369 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1503 secs. Pages in use: 243
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1490/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 126813 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1490/1791 244/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 56458356 m, 38063 m/sec, 171332857 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1490/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 136832 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1508 secs. Pages in use: 244
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1495/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 127237 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1495/1791 245/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 56636532 m, 35635 m/sec, 171868959 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1495/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 137295 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1513 secs. Pages in use: 245
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1500/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 127660 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1500/1791 245/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 56809064 m, 34506 m/sec, 172393922 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1500/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 137758 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1518 secs. Pages in use: 245
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1505/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 128083 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1505/1791 246/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 57001072 m, 38401 m/sec, 172979737 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1505/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 138220 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1523 secs. Pages in use: 246
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1510/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 128506 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1510/1791 247/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 57174886 m, 34762 m/sec, 173497668 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1510/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 138684 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1528 secs. Pages in use: 247
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1515/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 128931 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1515/1791 248/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 57350758 m, 35174 m/sec, 174047064 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1515/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 139146 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1533 secs. Pages in use: 248
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1520/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 129356 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1520/1791 248/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 57546227 m, 39093 m/sec, 174630865 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1520/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 139610 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1538 secs. Pages in use: 248
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1525/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 129780 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1525/1791 249/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 57762686 m, 43291 m/sec, 175285893 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1525/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 140073 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1543 secs. Pages in use: 249
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1530/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 130204 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1530/1791 250/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 57977655 m, 42993 m/sec, 175940879 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1530/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 140536 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1548 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1535/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 130628 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1535/1791 251/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 58187161 m, 41901 m/sec, 176574423 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1535/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 140999 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1553 secs. Pages in use: 251
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1540/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 131053 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1540/1791 252/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 58409903 m, 44548 m/sec, 177257570 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1540/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 141462 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1558 secs. Pages in use: 252
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1545/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 131477 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1545/1791 253/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 58599492 m, 37917 m/sec, 177842863 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1545/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 141924 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1563 secs. Pages in use: 253
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1550/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 131902 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1550/1791 254/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 58779178 m, 35937 m/sec, 178392294 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1550/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 142388 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1568 secs. Pages in use: 254
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1555/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 132325 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1555/1791 255/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 58984518 m, 41068 m/sec, 179037954 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1555/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 142851 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1573 secs. Pages in use: 255
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1560/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 132750 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1560/1791 255/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 59177546 m, 38605 m/sec, 179615821 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1560/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 143313 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1578 secs. Pages in use: 255
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1565/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 133174 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1565/1791 256/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 59368078 m, 38106 m/sec, 180192502 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1565/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 143775 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1583 secs. Pages in use: 256
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-10: AG false findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-14: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 1570/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 133599 attempts, .
[[35mlola[0m][.] 55 EF EXCL 1570/1791 257/2000 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-05 59556192 m, 37622 m/sec, 180762167 t fired, .
[[35mlola[0m][.] 56 EF FNDP 1570/3582 0/5 BridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-06 144239 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1588 secs. Pages in use: 257
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-02: AG false state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-ReachabilityCardinality-2024-08: INITIAL true preprocessing[0m
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BridgeAndVehicles-PT-V50P50N10"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is BridgeAndVehicles-PT-V50P50N10, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r049-tajo-171620400400254"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/BridgeAndVehicles-PT-V50P50N10.tgz
mv BridgeAndVehicles-PT-V50P50N10 execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;