About the Execution of LoLA for BridgeAndVehicles-PT-V50P50N10
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 0.000 | 1773093.00 | 0.00 | 0.00 | [undef] | Cannot compute |
Execution Chart
Sorry, for this execution, no execution chart could be reported.
Trace from the execution
Formatting '/mnt/tpsp/fkordon/mcc2024-input.r049-tajo-171620400400250.qcow2', fmt=qcow2 size=4294967296 backing_file='/mnt/tpsp/fkordon/mcc2024-input.qcow2' backing_fmt='qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is BridgeAndVehicles-PT-V50P50N10, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r049-tajo-171620400400250
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 3.2M
-rw-r--r-- 1 mcc users 18K Apr 13 02:30 CTLCardinality.txt
-rw-r--r-- 1 mcc users 107K Apr 13 02:30 CTLCardinality.xml
-rw-r--r-- 1 mcc users 129K Apr 13 02:26 CTLFireability.txt
-rw-r--r-- 1 mcc users 529K Apr 13 02:26 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 7.4K Apr 22 14:30 LTLCardinality.txt
-rw-r--r-- 1 mcc users 34K Apr 22 14:30 LTLCardinality.xml
-rw-r--r-- 1 mcc users 77K Apr 22 14:30 LTLFireability.txt
-rw-r--r-- 1 mcc users 227K Apr 22 14:30 LTLFireability.xml
-rw-r--r-- 1 mcc users 44K Apr 13 02:47 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 264K Apr 13 02:47 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 133K Apr 13 02:42 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 514K Apr 13 02:42 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 3.7K Apr 22 14:30 UpperBounds.txt
-rw-r--r-- 1 mcc users 7.7K Apr 22 14:30 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 10 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 1.1M May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-00
FORMULA_NAME BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-01
FORMULA_NAME BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-02
FORMULA_NAME BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-03
FORMULA_NAME BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-04
FORMULA_NAME BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-05
FORMULA_NAME BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-06
FORMULA_NAME BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-07
FORMULA_NAME BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-08
FORMULA_NAME BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-09
FORMULA_NAME BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-10
FORMULA_NAME BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-11
FORMULA_NAME BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-12
FORMULA_NAME BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-13
FORMULA_NAME BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-14
FORMULA_NAME BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717011909516
BK_STOP 1717013682609
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] LAUNCH task # 28 (type CNST) for 27 BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 28 (type CNST) for BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 22 (type EXCL) for 21 BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 51 (type EQUN) for 12 BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 22 (type EXCL) for BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 61
[[35mlola[0m][I] fired transitions : 61
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 46 (type EXCL) for 45 BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 256 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-04: EG 0 1 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 2/256 2/2000 BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-15 235900 m, 47180 m/sec, 870046 t fired, .
[[35mlola[0m][.] 51 EF STEQ 2/3597 0/5 BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-04 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-04: EG 0 1 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 7/256 4/2000 BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-15 636454 m, 80110 m/sec, 2484163 t fired, .
[[35mlola[0m][.] 51 EF STEQ 7/3597 0/5 BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-04 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-04: EG 0 1 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 12/256 6/2000 BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-15 988343 m, 70377 m/sec, 4084660 t fired, .
[[35mlola[0m][.] 51 EF STEQ 12/3597 0/5 BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-04 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-04: EG 0 1 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 17/256 7/2000 BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-15 1347162 m, 71763 m/sec, 5690065 t fired, .
[[35mlola[0m][.] 51 EF STEQ 17/3597 0/5 BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-04 sara not yet started (preprocessing).
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[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 51 (type EQUN) for BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-04
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-04: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 37 CTL EXCL 15/278 11/2000 BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-12 2099791 m, 134939 m/sec, 9088098 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 5/308 4/2000 BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-10 751822 m, 150364 m/sec, 1627723 t fired, .
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[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 848627
[[35mlola[0m][I] fired transitions : 1849386
[[35mlola[0m][I] time used : 5
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[[35mlola[0m][I] FINISHED task # 25 (type EXCL) for BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 422
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[[35mlola[0m][I] time used : 0
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[[35mlola[0m][.] 19 CTL EXCL 5/395 2/2000 BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-06 215826 m, 43165 m/sec, 2365434 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 10/395 3/2000 BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-06 462345 m, 49303 m/sec, 5036215 t fired, .
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[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-04: EG 0 1 0 0 2 0 0 0
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[[35mlola[0m][.] BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] 19 CTL EXCL 15/395 4/2000 BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-06 706155 m, 48762 m/sec, 7588439 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 20/395 5/2000 BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-06 951508 m, 49070 m/sec, 10030259 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 25/395 7/2000 BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-06 1233689 m, 56436 m/sec, 12604182 t fired, .
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[[35mlola[0m][I] markings : 1296439
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[[35mlola[0m][I] FINISHED task # 16 (type EXCL) for BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-05
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[[35mlola[0m][.] 7 CTL EXCL 4/548 3/2000 BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-02 464430 m, 92886 m/sec, 974738 t fired, .
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[[35mlola[0m][.] 7 CTL EXCL 164/548 95/2000 BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-02 18561944 m, 122803 m/sec, 42959482 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 45/548 24/2000 BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-01 4571419 m, 96224 m/sec, 15732785 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 320/548 151/2000 BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-01 29646827 m, 72792 m/sec, 105927245 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 330/548 155/2000 BridgeAndVehicles-PT-V50P50N10-CTLFireability-2024-01 30436206 m, 76480 m/sec, 108781179 t fired, .
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========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BridgeAndVehicles-PT-V50P50N10"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is BridgeAndVehicles-PT-V50P50N10, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r049-tajo-171620400400250"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/BridgeAndVehicles-PT-V50P50N10.tgz
mv BridgeAndVehicles-PT-V50P50N10 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;