MCC'2024- Execution of r049-tajo-171620400400236

About the Execution of LoLA for BridgeAndVehicles-PT-V50P20N20

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
16204.151	786570.00	1736875.00	459.20	F????F??F???????	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/mnt/tpsp/fkordon/mcc2024-input.r049-tajo-171620400400236.qcow2', fmt=qcow2 size=4294967296 backing_file='/mnt/tpsp/fkordon/mcc2024-input.qcow2' backing_fmt='qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
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...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is BridgeAndVehicles-PT-V50P20N20, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r049-tajo-171620400400236
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 7.2M
-rw-r--r-- 1 mcc users 25K Apr 13 00:55 CTLCardinality.txt
-rw-r--r-- 1 mcc users 153K Apr 13 00:55 CTLCardinality.xml
-rw-r--r-- 1 mcc users 226K Apr 13 00:50 CTLFireability.txt
-rw-r--r-- 1 mcc users 875K Apr 13 00:50 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 11K Apr 22 14:29 LTLCardinality.txt
-rw-r--r-- 1 mcc users 42K Apr 22 14:29 LTLCardinality.xml
-rw-r--r-- 1 mcc users 68K Apr 22 14:29 LTLFireability.txt
-rw-r--r-- 1 mcc users 195K Apr 22 14:29 LTLFireability.xml
-rw-r--r-- 1 mcc users 20K Apr 13 01:34 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 149K Apr 13 01:34 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 723K Apr 13 01:29 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 2.8M Apr 13 01:29 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Apr 22 14:29 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Apr 22 14:29 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 10 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 1.9M May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME BridgeAndVehicles-PT-V50P20N20-LTLFireability-00
FORMULA_NAME BridgeAndVehicles-PT-V50P20N20-LTLFireability-01
FORMULA_NAME BridgeAndVehicles-PT-V50P20N20-LTLFireability-02
FORMULA_NAME BridgeAndVehicles-PT-V50P20N20-LTLFireability-03
FORMULA_NAME BridgeAndVehicles-PT-V50P20N20-LTLFireability-04
FORMULA_NAME BridgeAndVehicles-PT-V50P20N20-LTLFireability-05
FORMULA_NAME BridgeAndVehicles-PT-V50P20N20-LTLFireability-06
FORMULA_NAME BridgeAndVehicles-PT-V50P20N20-LTLFireability-07
FORMULA_NAME BridgeAndVehicles-PT-V50P20N20-LTLFireability-08
FORMULA_NAME BridgeAndVehicles-PT-V50P20N20-LTLFireability-09
FORMULA_NAME BridgeAndVehicles-PT-V50P20N20-LTLFireability-10
FORMULA_NAME BridgeAndVehicles-PT-V50P20N20-LTLFireability-11
FORMULA_NAME BridgeAndVehicles-PT-V50P20N20-LTLFireability-12
FORMULA_NAME BridgeAndVehicles-PT-V50P20N20-LTLFireability-13
FORMULA_NAME BridgeAndVehicles-PT-V50P20N20-LTLFireability-14
FORMULA_NAME BridgeAndVehicles-PT-V50P20N20-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1717011122636

FORMULA BridgeAndVehicles-PT-V50P20N20-LTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V50P20N20-LTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V50P20N20-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1717011909206

--------------------
content from stderr:

[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 29 (type EXCL) for 28 BridgeAndVehicles-PT-V50P20N20-LTLFireability-08
[[35mlola[0m][I] time limit : 199 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 29 (type EXCL) for BridgeAndVehicles-PT-V50P20N20-LTLFireability-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 414
[[35mlola[0m][I] fired transitions : 414
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 16 (type EXCL) for 15 BridgeAndVehicles-PT-V50P20N20-LTLFireability-05
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 60 (type EQUN) for 34 BridgeAndVehicles-PT-V50P20N20-LTLFireability-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 16 (type EXCL) for BridgeAndVehicles-PT-V50P20N20-LTLFireability-05
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 413
[[35mlola[0m][I] fired transitions : 413
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 BridgeAndVehicles-PT-V50P20N20-LTLFireability-00
[[35mlola[0m][I] time limit : 224 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for BridgeAndVehicles-PT-V50P20N20-LTLFireability-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 413
[[35mlola[0m][I] fired transitions : 413
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 57 (type EXCL) for 34 BridgeAndVehicles-PT-V50P20N20-LTLFireability-10
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 57 (type EXCL) for BridgeAndVehicles-PT-V50P20N20-LTLFireability-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 60 (type EQUN) for BridgeAndVehicles-PT-V50P20N20-LTLFireability-10 (obsolete)
[[35mlola[0m][I] LAUNCH task # 62 (type EXCL) for 34 BridgeAndVehicles-PT-V50P20N20-LTLFireability-10
[[35mlola[0m][I] time limit : 256 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 65 (type EQUN) for 34 BridgeAndVehicles-PT-V50P20N20-LTLFireability-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 70 (type EQUN) for 25 BridgeAndVehicles-PT-V50P20N20-LTLFireability-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 72 (type FNDP) for 18 BridgeAndVehicles-PT-V50P20N20-LTLFireability-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 60 (type EQUN) for BridgeAndVehicles-PT-V50P20N20-LTLFireability-10
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 65 (type EQUN) for BridgeAndVehicles-PT-V50P20N20-LTLFireability-10
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 79 (type EQUN) for 18 BridgeAndVehicles-PT-V50P20N20-LTLFireability-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 79 (type EQUN) for BridgeAndVehicles-PT-V50P20N20-LTLFireability-06
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 73 (type EQUN) for 18 BridgeAndVehicles-PT-V50P20N20-LTLFireability-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-06: CONJ 0 2 2 0 3 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-07: F 0 1 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-10: CONJ 0 0 1 0 5 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-14: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 EG EXCL 2/256 1/2000 BridgeAndVehicles-PT-V50P20N20-LTLFireability-10 18610 m, 3722 m/sec, 44929 t fired, .
[[35mlola[0m][.] 70 EF STEQ 2/3596 0/5 BridgeAndVehicles-PT-V50P20N20-LTLFireability-07 sara not yet started (preprocessing).
[[35mlola[0m][.] 72 EF FNDP 2/3596 0/5 BridgeAndVehicles-PT-V50P20N20-LTLFireability-06 132 attempts, .
[[35mlola[0m][.] 73 EF STEQ 1/3595 0/5 BridgeAndVehicles-PT-V50P20N20-LTLFireability-06 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 6 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 4 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-06: CONJ 0 2 2 0 3 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-07: F 0 1 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-10: CONJ 0 0 1 0 5 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-14: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 EG EXCL 7/256 1/2000 BridgeAndVehicles-PT-V50P20N20-LTLFireability-10 78178 m, 11913 m/sec, 208758 t fired, .
[[35mlola[0m][.] 70 EF STEQ 7/3596 0/5 BridgeAndVehicles-PT-V50P20N20-LTLFireability-07 sara not yet started (preprocessing).
[[35mlola[0m][.] 72 EF FNDP 7/3596 0/5 BridgeAndVehicles-PT-V50P20N20-LTLFireability-06 557 attempts, .
[[35mlola[0m][.] 73 EF STEQ 6/3595 0/5 BridgeAndVehicles-PT-V50P20N20-LTLFireability-06 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 11 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 4 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-06: CONJ 0 2 2 0 3 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-07: F 0 1 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-10: CONJ 0 0 1 0 5 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-14: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 EG EXCL 12/256 1/2000 BridgeAndVehicles-PT-V50P20N20-LTLFireability-10 150167 m, 14397 m/sec, 400551 t fired, .
[[35mlola[0m][.] 70 EF STEQ 12/3596 0/5 BridgeAndVehicles-PT-V50P20N20-LTLFireability-07 sara not yet started (preprocessing).
[[35mlola[0m][.] 72 EF FNDP 12/3596 0/5 BridgeAndVehicles-PT-V50P20N20-LTLFireability-06 937 attempts, .
[[35mlola[0m][.] 73 EF STEQ 11/3595 0/5 BridgeAndVehicles-PT-V50P20N20-LTLFireability-06 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 16 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 4 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 73 (type EQUN) for BridgeAndVehicles-PT-V50P20N20-LTLFireability-06
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-06: CONJ 0 2 1 0 4 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-07: F 0 1 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-10: CONJ 0 0 1 0 5 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-14: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 EG EXCL 17/256 2/2000 BridgeAndVehicles-PT-V50P20N20-LTLFireability-10 244983 m, 18963 m/sec, 643061 t fired, .
[[35mlola[0m][.] 70 EF STEQ 17/3596 0/5 BridgeAndVehicles-PT-V50P20N20-LTLFireability-07 sara not yet started (preprocessing).
[[35mlola[0m][.] 72 EF FNDP 17/3596 0/5 BridgeAndVehicles-PT-V50P20N20-LTLFireability-06 1287 attempts, .
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[[35mlola[0m][I] LAUNCH task # 54 (type EXCL) for 53 BridgeAndVehicles-PT-V50P20N20-LTLFireability-15
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[[35mlola[0m][I] FINISHED task # 54 (type EXCL) for BridgeAndVehicles-PT-V50P20N20-LTLFireability-15
[[35mlola[0m][I] result : false
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[[35mlola[0m][I] LAUNCH task # 51 (type EXCL) for 50 BridgeAndVehicles-PT-V50P20N20-LTLFireability-14
[[35mlola[0m][I] time limit : 298 sec
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[[35mlola[0m][I] FINISHED task # 51 (type EXCL) for BridgeAndVehicles-PT-V50P20N20-LTLFireability-14
[[35mlola[0m][I] result : false
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[[35mlola[0m][I] LAUNCH task # 48 (type EXCL) for 47 BridgeAndVehicles-PT-V50P20N20-LTLFireability-13
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[[35mlola[0m][.] 48 LTL EXCL 4/325 4/2000 BridgeAndVehicles-PT-V50P20N20-LTLFireability-13 548665 m, 109733 m/sec, 1791435 t fired, .
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[[35mlola[0m][.] 72 EF FNDP 22/3596 0/5 BridgeAndVehicles-PT-V50P20N20-LTLFireability-06 1614 attempts, .
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[[35mlola[0m][.] 48 LTL EXCL 9/325 9/2000 BridgeAndVehicles-PT-V50P20N20-LTLFireability-13 1234573 m, 137181 m/sec, 4044517 t fired, .
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[[35mlola[0m][.] 72 EF FNDP 27/3596 0/5 BridgeAndVehicles-PT-V50P20N20-LTLFireability-06 1945 attempts, .
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[[35mlola[0m][.] 48 LTL EXCL 14/325 14/2000 BridgeAndVehicles-PT-V50P20N20-LTLFireability-13 1993390 m, 151763 m/sec, 6626493 t fired, .
[[35mlola[0m][.] 72 EF FNDP 32/3596 0/5 BridgeAndVehicles-PT-V50P20N20-LTLFireability-06 2280 attempts, .
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[[35mlola[0m][.] 48 LTL EXCL 19/325 19/2000 BridgeAndVehicles-PT-V50P20N20-LTLFireability-13 2764439 m, 154209 m/sec, 9185495 t fired, .
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[[35mlola[0m][.] 48 LTL EXCL 24/325 24/2000 BridgeAndVehicles-PT-V50P20N20-LTLFireability-13 3488451 m, 144802 m/sec, 11845300 t fired, .
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[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 90/580 79/2000 BridgeAndVehicles-PT-V50P20N20-LTLFireability-01 10797610 m, 101046 m/sec, 38288448 t fired, .
[[35mlola[0m][.] 72 EF FNDP 782/3596 0/5 BridgeAndVehicles-PT-V50P20N20-LTLFireability-06 49037 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 786 secs. Pages in use: 738
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 412 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BridgeAndVehicles-PT-V50P20N20"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is BridgeAndVehicles-PT-V50P20N20, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r049-tajo-171620400400236"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/BridgeAndVehicles-PT-V50P20N20.tgz
mv BridgeAndVehicles-PT-V50P20N20 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;